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1/*
2 * Copyright (C) 2013, NVIDIA Corporation. All rights reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sub license,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the
12 * next paragraph) shall be included in all copies or substantial portions
13 * of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 */
23
24#include <linux/delay.h>
25#include <linux/gpio/consumer.h>
26#include <linux/iopoll.h>
27#include <linux/module.h>
28#include <linux/of_platform.h>
29#include <linux/platform_device.h>
30#include <linux/regulator/consumer.h>
31
32#include <video/display_timing.h>
33#include <video/of_display_timing.h>
34#include <video/videomode.h>
35
36#include <drm/drm_crtc.h>
37#include <drm/drm_device.h>
38#include <drm/drm_mipi_dsi.h>
39#include <drm/drm_panel.h>
40
41/**
42 * @modes: Pointer to array of fixed modes appropriate for this panel. If
43 * only one mode then this can just be the address of this the mode.
44 * NOTE: cannot be used with "timings" and also if this is specified
45 * then you cannot override the mode in the device tree.
46 * @num_modes: Number of elements in modes array.
47 * @timings: Pointer to array of display timings. NOTE: cannot be used with
48 * "modes" and also these will be used to validate a device tree
49 * override if one is present.
50 * @num_timings: Number of elements in timings array.
51 * @bpc: Bits per color.
52 * @size: Structure containing the physical size of this panel.
53 * @delay: Structure containing various delay values for this panel.
54 * @bus_format: See MEDIA_BUS_FMT_... defines.
55 * @bus_flags: See DRM_BUS_FLAG_... defines.
56 */
57struct panel_desc {
58 const struct drm_display_mode *modes;
59 unsigned int num_modes;
60 const struct display_timing *timings;
61 unsigned int num_timings;
62
63 unsigned int bpc;
64
65 /**
66 * @width: width (in millimeters) of the panel's active display area
67 * @height: height (in millimeters) of the panel's active display area
68 */
69 struct {
70 unsigned int width;
71 unsigned int height;
72 } size;
73
74 /**
75 * @prepare: the time (in milliseconds) that it takes for the panel to
76 * become ready and start receiving video data
77 * @hpd_absent_delay: Add this to the prepare delay if we know Hot
78 * Plug Detect isn't used.
79 * @enable: the time (in milliseconds) that it takes for the panel to
80 * display the first valid frame after starting to receive
81 * video data
82 * @disable: the time (in milliseconds) that it takes for the panel to
83 * turn the display off (no content is visible)
84 * @unprepare: the time (in milliseconds) that it takes for the panel
85 * to power itself down completely
86 */
87 struct {
88 unsigned int prepare;
89 unsigned int hpd_absent_delay;
90 unsigned int enable;
91 unsigned int disable;
92 unsigned int unprepare;
93 } delay;
94
95 u32 bus_format;
96 u32 bus_flags;
97 int connector_type;
98};
99
100struct panel_simple {
101 struct drm_panel base;
102 bool prepared;
103 bool enabled;
104 bool no_hpd;
105
106 const struct panel_desc *desc;
107
108 struct regulator *supply;
109 struct i2c_adapter *ddc;
110
111 struct gpio_desc *enable_gpio;
112 struct gpio_desc *hpd_gpio;
113
114 struct drm_display_mode override_mode;
115};
116
117static inline struct panel_simple *to_panel_simple(struct drm_panel *panel)
118{
119 return container_of(panel, struct panel_simple, base);
120}
121
122static unsigned int panel_simple_get_timings_modes(struct panel_simple *panel,
123 struct drm_connector *connector)
124{
125 struct drm_display_mode *mode;
126 unsigned int i, num = 0;
127
128 for (i = 0; i < panel->desc->num_timings; i++) {
129 const struct display_timing *dt = &panel->desc->timings[i];
130 struct videomode vm;
131
132 videomode_from_timing(dt, &vm);
133 mode = drm_mode_create(connector->dev);
134 if (!mode) {
135 dev_err(panel->base.dev, "failed to add mode %ux%u\n",
136 dt->hactive.typ, dt->vactive.typ);
137 continue;
138 }
139
140 drm_display_mode_from_videomode(&vm, mode);
141
142 mode->type |= DRM_MODE_TYPE_DRIVER;
143
144 if (panel->desc->num_timings == 1)
145 mode->type |= DRM_MODE_TYPE_PREFERRED;
146
147 drm_mode_probed_add(connector, mode);
148 num++;
149 }
150
151 return num;
152}
153
154static unsigned int panel_simple_get_display_modes(struct panel_simple *panel,
155 struct drm_connector *connector)
156{
157 struct drm_display_mode *mode;
158 unsigned int i, num = 0;
159
160 for (i = 0; i < panel->desc->num_modes; i++) {
161 const struct drm_display_mode *m = &panel->desc->modes[i];
162
163 mode = drm_mode_duplicate(connector->dev, m);
164 if (!mode) {
165 dev_err(panel->base.dev, "failed to add mode %ux%u@%u\n",
166 m->hdisplay, m->vdisplay,
167 drm_mode_vrefresh(m));
168 continue;
169 }
170
171 mode->type |= DRM_MODE_TYPE_DRIVER;
172
173 if (panel->desc->num_modes == 1)
174 mode->type |= DRM_MODE_TYPE_PREFERRED;
175
176 drm_mode_set_name(mode);
177
178 drm_mode_probed_add(connector, mode);
179 num++;
180 }
181
182 return num;
183}
184
185static int panel_simple_get_non_edid_modes(struct panel_simple *panel,
186 struct drm_connector *connector)
187{
188 struct drm_display_mode *mode;
189 bool has_override = panel->override_mode.type;
190 unsigned int num = 0;
191
192 if (!panel->desc)
193 return 0;
194
195 if (has_override) {
196 mode = drm_mode_duplicate(connector->dev,
197 &panel->override_mode);
198 if (mode) {
199 drm_mode_probed_add(connector, mode);
200 num = 1;
201 } else {
202 dev_err(panel->base.dev, "failed to add override mode\n");
203 }
204 }
205
206 /* Only add timings if override was not there or failed to validate */
207 if (num == 0 && panel->desc->num_timings)
208 num = panel_simple_get_timings_modes(panel, connector);
209
210 /*
211 * Only add fixed modes if timings/override added no mode.
212 *
213 * We should only ever have either the display timings specified
214 * or a fixed mode. Anything else is rather bogus.
215 */
216 WARN_ON(panel->desc->num_timings && panel->desc->num_modes);
217 if (num == 0)
218 num = panel_simple_get_display_modes(panel, connector);
219
220 connector->display_info.bpc = panel->desc->bpc;
221 connector->display_info.width_mm = panel->desc->size.width;
222 connector->display_info.height_mm = panel->desc->size.height;
223 if (panel->desc->bus_format)
224 drm_display_info_set_bus_formats(&connector->display_info,
225 &panel->desc->bus_format, 1);
226 connector->display_info.bus_flags = panel->desc->bus_flags;
227
228 return num;
229}
230
231static int panel_simple_disable(struct drm_panel *panel)
232{
233 struct panel_simple *p = to_panel_simple(panel);
234
235 if (!p->enabled)
236 return 0;
237
238 if (p->desc->delay.disable)
239 msleep(p->desc->delay.disable);
240
241 p->enabled = false;
242
243 return 0;
244}
245
246static int panel_simple_unprepare(struct drm_panel *panel)
247{
248 struct panel_simple *p = to_panel_simple(panel);
249
250 if (!p->prepared)
251 return 0;
252
253 gpiod_set_value_cansleep(p->enable_gpio, 0);
254
255 regulator_disable(p->supply);
256
257 if (p->desc->delay.unprepare)
258 msleep(p->desc->delay.unprepare);
259
260 p->prepared = false;
261
262 return 0;
263}
264
265static int panel_simple_get_hpd_gpio(struct device *dev,
266 struct panel_simple *p, bool from_probe)
267{
268 int err;
269
270 p->hpd_gpio = devm_gpiod_get_optional(dev, "hpd", GPIOD_IN);
271 if (IS_ERR(p->hpd_gpio)) {
272 err = PTR_ERR(p->hpd_gpio);
273
274 /*
275 * If we're called from probe we won't consider '-EPROBE_DEFER'
276 * to be an error--we'll leave the error code in "hpd_gpio".
277 * When we try to use it we'll try again. This allows for
278 * circular dependencies where the component providing the
279 * hpd gpio needs the panel to init before probing.
280 */
281 if (err != -EPROBE_DEFER || !from_probe) {
282 dev_err(dev, "failed to get 'hpd' GPIO: %d\n", err);
283 return err;
284 }
285 }
286
287 return 0;
288}
289
290static int panel_simple_prepare(struct drm_panel *panel)
291{
292 struct panel_simple *p = to_panel_simple(panel);
293 unsigned int delay;
294 int err;
295 int hpd_asserted;
296
297 if (p->prepared)
298 return 0;
299
300 err = regulator_enable(p->supply);
301 if (err < 0) {
302 dev_err(panel->dev, "failed to enable supply: %d\n", err);
303 return err;
304 }
305
306 gpiod_set_value_cansleep(p->enable_gpio, 1);
307
308 delay = p->desc->delay.prepare;
309 if (p->no_hpd)
310 delay += p->desc->delay.hpd_absent_delay;
311 if (delay)
312 msleep(delay);
313
314 if (p->hpd_gpio) {
315 if (IS_ERR(p->hpd_gpio)) {
316 err = panel_simple_get_hpd_gpio(panel->dev, p, false);
317 if (err)
318 return err;
319 }
320
321 err = readx_poll_timeout(gpiod_get_value_cansleep, p->hpd_gpio,
322 hpd_asserted, hpd_asserted,
323 1000, 2000000);
324 if (hpd_asserted < 0)
325 err = hpd_asserted;
326
327 if (err) {
328 dev_err(panel->dev,
329 "error waiting for hpd GPIO: %d\n", err);
330 return err;
331 }
332 }
333
334 p->prepared = true;
335
336 return 0;
337}
338
339static int panel_simple_enable(struct drm_panel *panel)
340{
341 struct panel_simple *p = to_panel_simple(panel);
342
343 if (p->enabled)
344 return 0;
345
346 if (p->desc->delay.enable)
347 msleep(p->desc->delay.enable);
348
349 p->enabled = true;
350
351 return 0;
352}
353
354static int panel_simple_get_modes(struct drm_panel *panel,
355 struct drm_connector *connector)
356{
357 struct panel_simple *p = to_panel_simple(panel);
358 int num = 0;
359
360 /* probe EDID if a DDC bus is available */
361 if (p->ddc) {
362 struct edid *edid = drm_get_edid(connector, p->ddc);
363
364 drm_connector_update_edid_property(connector, edid);
365 if (edid) {
366 num += drm_add_edid_modes(connector, edid);
367 kfree(edid);
368 }
369 }
370
371 /* add hard-coded panel modes */
372 num += panel_simple_get_non_edid_modes(p, connector);
373
374 return num;
375}
376
377static int panel_simple_get_timings(struct drm_panel *panel,
378 unsigned int num_timings,
379 struct display_timing *timings)
380{
381 struct panel_simple *p = to_panel_simple(panel);
382 unsigned int i;
383
384 if (p->desc->num_timings < num_timings)
385 num_timings = p->desc->num_timings;
386
387 if (timings)
388 for (i = 0; i < num_timings; i++)
389 timings[i] = p->desc->timings[i];
390
391 return p->desc->num_timings;
392}
393
394static const struct drm_panel_funcs panel_simple_funcs = {
395 .disable = panel_simple_disable,
396 .unprepare = panel_simple_unprepare,
397 .prepare = panel_simple_prepare,
398 .enable = panel_simple_enable,
399 .get_modes = panel_simple_get_modes,
400 .get_timings = panel_simple_get_timings,
401};
402
403static struct panel_desc panel_dpi;
404
405static int panel_dpi_probe(struct device *dev,
406 struct panel_simple *panel)
407{
408 struct display_timing *timing;
409 const struct device_node *np;
410 struct panel_desc *desc;
411 unsigned int bus_flags;
412 struct videomode vm;
413 int ret;
414
415 np = dev->of_node;
416 desc = devm_kzalloc(dev, sizeof(*desc), GFP_KERNEL);
417 if (!desc)
418 return -ENOMEM;
419
420 timing = devm_kzalloc(dev, sizeof(*timing), GFP_KERNEL);
421 if (!timing)
422 return -ENOMEM;
423
424 ret = of_get_display_timing(np, "panel-timing", timing);
425 if (ret < 0) {
426 dev_err(dev, "%pOF: no panel-timing node found for \"panel-dpi\" binding\n",
427 np);
428 return ret;
429 }
430
431 desc->timings = timing;
432 desc->num_timings = 1;
433
434 of_property_read_u32(np, "width-mm", &desc->size.width);
435 of_property_read_u32(np, "height-mm", &desc->size.height);
436
437 /* Extract bus_flags from display_timing */
438 bus_flags = 0;
439 vm.flags = timing->flags;
440 drm_bus_flags_from_videomode(&vm, &bus_flags);
441 desc->bus_flags = bus_flags;
442
443 /* We do not know the connector for the DT node, so guess it */
444 desc->connector_type = DRM_MODE_CONNECTOR_DPI;
445
446 panel->desc = desc;
447
448 return 0;
449}
450
451#define PANEL_SIMPLE_BOUNDS_CHECK(to_check, bounds, field) \
452 (to_check->field.typ >= bounds->field.min && \
453 to_check->field.typ <= bounds->field.max)
454static void panel_simple_parse_panel_timing_node(struct device *dev,
455 struct panel_simple *panel,
456 const struct display_timing *ot)
457{
458 const struct panel_desc *desc = panel->desc;
459 struct videomode vm;
460 unsigned int i;
461
462 if (WARN_ON(desc->num_modes)) {
463 dev_err(dev, "Reject override mode: panel has a fixed mode\n");
464 return;
465 }
466 if (WARN_ON(!desc->num_timings)) {
467 dev_err(dev, "Reject override mode: no timings specified\n");
468 return;
469 }
470
471 for (i = 0; i < panel->desc->num_timings; i++) {
472 const struct display_timing *dt = &panel->desc->timings[i];
473
474 if (!PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hactive) ||
475 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hfront_porch) ||
476 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hback_porch) ||
477 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hsync_len) ||
478 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vactive) ||
479 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vfront_porch) ||
480 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vback_porch) ||
481 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vsync_len))
482 continue;
483
484 if (ot->flags != dt->flags)
485 continue;
486
487 videomode_from_timing(ot, &vm);
488 drm_display_mode_from_videomode(&vm, &panel->override_mode);
489 panel->override_mode.type |= DRM_MODE_TYPE_DRIVER |
490 DRM_MODE_TYPE_PREFERRED;
491 break;
492 }
493
494 if (WARN_ON(!panel->override_mode.type))
495 dev_err(dev, "Reject override mode: No display_timing found\n");
496}
497
498static int panel_simple_probe(struct device *dev, const struct panel_desc *desc)
499{
500 struct panel_simple *panel;
501 struct display_timing dt;
502 struct device_node *ddc;
503 int err;
504
505 panel = devm_kzalloc(dev, sizeof(*panel), GFP_KERNEL);
506 if (!panel)
507 return -ENOMEM;
508
509 panel->enabled = false;
510 panel->prepared = false;
511 panel->desc = desc;
512
513 panel->no_hpd = of_property_read_bool(dev->of_node, "no-hpd");
514 if (!panel->no_hpd) {
515 err = panel_simple_get_hpd_gpio(dev, panel, true);
516 if (err)
517 return err;
518 }
519
520 panel->supply = devm_regulator_get(dev, "power");
521 if (IS_ERR(panel->supply))
522 return PTR_ERR(panel->supply);
523
524 panel->enable_gpio = devm_gpiod_get_optional(dev, "enable",
525 GPIOD_OUT_LOW);
526 if (IS_ERR(panel->enable_gpio)) {
527 err = PTR_ERR(panel->enable_gpio);
528 if (err != -EPROBE_DEFER)
529 dev_err(dev, "failed to request GPIO: %d\n", err);
530 return err;
531 }
532
533 ddc = of_parse_phandle(dev->of_node, "ddc-i2c-bus", 0);
534 if (ddc) {
535 panel->ddc = of_find_i2c_adapter_by_node(ddc);
536 of_node_put(ddc);
537
538 if (!panel->ddc)
539 return -EPROBE_DEFER;
540 }
541
542 if (desc == &panel_dpi) {
543 /* Handle the generic panel-dpi binding */
544 err = panel_dpi_probe(dev, panel);
545 if (err)
546 goto free_ddc;
547 } else {
548 if (!of_get_display_timing(dev->of_node, "panel-timing", &dt))
549 panel_simple_parse_panel_timing_node(dev, panel, &dt);
550 }
551
552 if (desc->connector_type == DRM_MODE_CONNECTOR_LVDS) {
553 /* Catch common mistakes for LVDS panels. */
554 WARN_ON(desc->bus_flags &
555 ~(DRM_BUS_FLAG_DE_LOW |
556 DRM_BUS_FLAG_DE_HIGH |
557 DRM_BUS_FLAG_DATA_MSB_TO_LSB |
558 DRM_BUS_FLAG_DATA_LSB_TO_MSB));
559 WARN_ON(desc->bus_format != MEDIA_BUS_FMT_RGB666_1X7X3_SPWG &&
560 desc->bus_format != MEDIA_BUS_FMT_RGB888_1X7X4_SPWG &&
561 desc->bus_format != MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA);
562 WARN_ON(desc->bus_format == MEDIA_BUS_FMT_RGB666_1X7X3_SPWG &&
563 desc->bpc != 6);
564 WARN_ON((desc->bus_format == MEDIA_BUS_FMT_RGB888_1X7X4_SPWG ||
565 desc->bus_format == MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA) &&
566 desc->bpc != 8);
567 }
568
569 drm_panel_init(&panel->base, dev, &panel_simple_funcs,
570 desc->connector_type);
571
572 err = drm_panel_of_backlight(&panel->base);
573 if (err)
574 goto free_ddc;
575
576 err = drm_panel_add(&panel->base);
577 if (err < 0)
578 goto free_ddc;
579
580 dev_set_drvdata(dev, panel);
581
582 return 0;
583
584free_ddc:
585 if (panel->ddc)
586 put_device(&panel->ddc->dev);
587
588 return err;
589}
590
591static int panel_simple_remove(struct device *dev)
592{
593 struct panel_simple *panel = dev_get_drvdata(dev);
594
595 drm_panel_remove(&panel->base);
596 drm_panel_disable(&panel->base);
597 drm_panel_unprepare(&panel->base);
598
599 if (panel->ddc)
600 put_device(&panel->ddc->dev);
601
602 return 0;
603}
604
605static void panel_simple_shutdown(struct device *dev)
606{
607 struct panel_simple *panel = dev_get_drvdata(dev);
608
609 drm_panel_disable(&panel->base);
610 drm_panel_unprepare(&panel->base);
611}
612
613static const struct drm_display_mode ampire_am_480272h3tmqw_t01h_mode = {
614 .clock = 9000,
615 .hdisplay = 480,
616 .hsync_start = 480 + 2,
617 .hsync_end = 480 + 2 + 41,
618 .htotal = 480 + 2 + 41 + 2,
619 .vdisplay = 272,
620 .vsync_start = 272 + 2,
621 .vsync_end = 272 + 2 + 10,
622 .vtotal = 272 + 2 + 10 + 2,
623 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
624};
625
626static const struct panel_desc ampire_am_480272h3tmqw_t01h = {
627 .modes = &ire_am_480272h3tmqw_t01h_mode,
628 .num_modes = 1,
629 .bpc = 8,
630 .size = {
631 .width = 105,
632 .height = 67,
633 },
634 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
635};
636
637static const struct drm_display_mode ampire_am800480r3tmqwa1h_mode = {
638 .clock = 33333,
639 .hdisplay = 800,
640 .hsync_start = 800 + 0,
641 .hsync_end = 800 + 0 + 255,
642 .htotal = 800 + 0 + 255 + 0,
643 .vdisplay = 480,
644 .vsync_start = 480 + 2,
645 .vsync_end = 480 + 2 + 45,
646 .vtotal = 480 + 2 + 45 + 0,
647 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
648};
649
650static const struct panel_desc ampire_am800480r3tmqwa1h = {
651 .modes = &ire_am800480r3tmqwa1h_mode,
652 .num_modes = 1,
653 .bpc = 6,
654 .size = {
655 .width = 152,
656 .height = 91,
657 },
658 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
659};
660
661static const struct display_timing santek_st0700i5y_rbslw_f_timing = {
662 .pixelclock = { 26400000, 33300000, 46800000 },
663 .hactive = { 800, 800, 800 },
664 .hfront_porch = { 16, 210, 354 },
665 .hback_porch = { 45, 36, 6 },
666 .hsync_len = { 1, 10, 40 },
667 .vactive = { 480, 480, 480 },
668 .vfront_porch = { 7, 22, 147 },
669 .vback_porch = { 22, 13, 3 },
670 .vsync_len = { 1, 10, 20 },
671 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW |
672 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE
673};
674
675static const struct panel_desc armadeus_st0700_adapt = {
676 .timings = &santek_st0700i5y_rbslw_f_timing,
677 .num_timings = 1,
678 .bpc = 6,
679 .size = {
680 .width = 154,
681 .height = 86,
682 },
683 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
684 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
685};
686
687static const struct drm_display_mode auo_b101aw03_mode = {
688 .clock = 51450,
689 .hdisplay = 1024,
690 .hsync_start = 1024 + 156,
691 .hsync_end = 1024 + 156 + 8,
692 .htotal = 1024 + 156 + 8 + 156,
693 .vdisplay = 600,
694 .vsync_start = 600 + 16,
695 .vsync_end = 600 + 16 + 6,
696 .vtotal = 600 + 16 + 6 + 16,
697};
698
699static const struct panel_desc auo_b101aw03 = {
700 .modes = &auo_b101aw03_mode,
701 .num_modes = 1,
702 .bpc = 6,
703 .size = {
704 .width = 223,
705 .height = 125,
706 },
707 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
708 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
709 .connector_type = DRM_MODE_CONNECTOR_LVDS,
710};
711
712static const struct display_timing auo_b101ean01_timing = {
713 .pixelclock = { 65300000, 72500000, 75000000 },
714 .hactive = { 1280, 1280, 1280 },
715 .hfront_porch = { 18, 119, 119 },
716 .hback_porch = { 21, 21, 21 },
717 .hsync_len = { 32, 32, 32 },
718 .vactive = { 800, 800, 800 },
719 .vfront_porch = { 4, 4, 4 },
720 .vback_porch = { 8, 8, 8 },
721 .vsync_len = { 18, 20, 20 },
722};
723
724static const struct panel_desc auo_b101ean01 = {
725 .timings = &auo_b101ean01_timing,
726 .num_timings = 1,
727 .bpc = 6,
728 .size = {
729 .width = 217,
730 .height = 136,
731 },
732};
733
734static const struct drm_display_mode auo_b101xtn01_mode = {
735 .clock = 72000,
736 .hdisplay = 1366,
737 .hsync_start = 1366 + 20,
738 .hsync_end = 1366 + 20 + 70,
739 .htotal = 1366 + 20 + 70,
740 .vdisplay = 768,
741 .vsync_start = 768 + 14,
742 .vsync_end = 768 + 14 + 42,
743 .vtotal = 768 + 14 + 42,
744 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
745};
746
747static const struct panel_desc auo_b101xtn01 = {
748 .modes = &auo_b101xtn01_mode,
749 .num_modes = 1,
750 .bpc = 6,
751 .size = {
752 .width = 223,
753 .height = 125,
754 },
755};
756
757static const struct drm_display_mode auo_b116xak01_mode = {
758 .clock = 69300,
759 .hdisplay = 1366,
760 .hsync_start = 1366 + 48,
761 .hsync_end = 1366 + 48 + 32,
762 .htotal = 1366 + 48 + 32 + 10,
763 .vdisplay = 768,
764 .vsync_start = 768 + 4,
765 .vsync_end = 768 + 4 + 6,
766 .vtotal = 768 + 4 + 6 + 15,
767 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
768};
769
770static const struct panel_desc auo_b116xak01 = {
771 .modes = &auo_b116xak01_mode,
772 .num_modes = 1,
773 .bpc = 6,
774 .size = {
775 .width = 256,
776 .height = 144,
777 },
778 .delay = {
779 .hpd_absent_delay = 200,
780 },
781 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
782 .connector_type = DRM_MODE_CONNECTOR_eDP,
783};
784
785static const struct drm_display_mode auo_b116xw03_mode = {
786 .clock = 70589,
787 .hdisplay = 1366,
788 .hsync_start = 1366 + 40,
789 .hsync_end = 1366 + 40 + 40,
790 .htotal = 1366 + 40 + 40 + 32,
791 .vdisplay = 768,
792 .vsync_start = 768 + 10,
793 .vsync_end = 768 + 10 + 12,
794 .vtotal = 768 + 10 + 12 + 6,
795 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
796};
797
798static const struct panel_desc auo_b116xw03 = {
799 .modes = &auo_b116xw03_mode,
800 .num_modes = 1,
801 .bpc = 6,
802 .size = {
803 .width = 256,
804 .height = 144,
805 },
806 .delay = {
807 .enable = 400,
808 },
809 .bus_flags = DRM_BUS_FLAG_SYNC_DRIVE_NEGEDGE,
810 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
811 .connector_type = DRM_MODE_CONNECTOR_eDP,
812};
813
814static const struct drm_display_mode auo_b133xtn01_mode = {
815 .clock = 69500,
816 .hdisplay = 1366,
817 .hsync_start = 1366 + 48,
818 .hsync_end = 1366 + 48 + 32,
819 .htotal = 1366 + 48 + 32 + 20,
820 .vdisplay = 768,
821 .vsync_start = 768 + 3,
822 .vsync_end = 768 + 3 + 6,
823 .vtotal = 768 + 3 + 6 + 13,
824};
825
826static const struct panel_desc auo_b133xtn01 = {
827 .modes = &auo_b133xtn01_mode,
828 .num_modes = 1,
829 .bpc = 6,
830 .size = {
831 .width = 293,
832 .height = 165,
833 },
834};
835
836static const struct drm_display_mode auo_b133htn01_mode = {
837 .clock = 150660,
838 .hdisplay = 1920,
839 .hsync_start = 1920 + 172,
840 .hsync_end = 1920 + 172 + 80,
841 .htotal = 1920 + 172 + 80 + 60,
842 .vdisplay = 1080,
843 .vsync_start = 1080 + 25,
844 .vsync_end = 1080 + 25 + 10,
845 .vtotal = 1080 + 25 + 10 + 10,
846};
847
848static const struct panel_desc auo_b133htn01 = {
849 .modes = &auo_b133htn01_mode,
850 .num_modes = 1,
851 .bpc = 6,
852 .size = {
853 .width = 293,
854 .height = 165,
855 },
856 .delay = {
857 .prepare = 105,
858 .enable = 20,
859 .unprepare = 50,
860 },
861};
862
863static const struct display_timing auo_g070vvn01_timings = {
864 .pixelclock = { 33300000, 34209000, 45000000 },
865 .hactive = { 800, 800, 800 },
866 .hfront_porch = { 20, 40, 200 },
867 .hback_porch = { 87, 40, 1 },
868 .hsync_len = { 1, 48, 87 },
869 .vactive = { 480, 480, 480 },
870 .vfront_porch = { 5, 13, 200 },
871 .vback_porch = { 31, 31, 29 },
872 .vsync_len = { 1, 1, 3 },
873};
874
875static const struct panel_desc auo_g070vvn01 = {
876 .timings = &auo_g070vvn01_timings,
877 .num_timings = 1,
878 .bpc = 8,
879 .size = {
880 .width = 152,
881 .height = 91,
882 },
883 .delay = {
884 .prepare = 200,
885 .enable = 50,
886 .disable = 50,
887 .unprepare = 1000,
888 },
889};
890
891static const struct drm_display_mode auo_g101evn010_mode = {
892 .clock = 68930,
893 .hdisplay = 1280,
894 .hsync_start = 1280 + 82,
895 .hsync_end = 1280 + 82 + 2,
896 .htotal = 1280 + 82 + 2 + 84,
897 .vdisplay = 800,
898 .vsync_start = 800 + 8,
899 .vsync_end = 800 + 8 + 2,
900 .vtotal = 800 + 8 + 2 + 6,
901};
902
903static const struct panel_desc auo_g101evn010 = {
904 .modes = &auo_g101evn010_mode,
905 .num_modes = 1,
906 .bpc = 6,
907 .size = {
908 .width = 216,
909 .height = 135,
910 },
911 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
912 .connector_type = DRM_MODE_CONNECTOR_LVDS,
913};
914
915static const struct drm_display_mode auo_g104sn02_mode = {
916 .clock = 40000,
917 .hdisplay = 800,
918 .hsync_start = 800 + 40,
919 .hsync_end = 800 + 40 + 216,
920 .htotal = 800 + 40 + 216 + 128,
921 .vdisplay = 600,
922 .vsync_start = 600 + 10,
923 .vsync_end = 600 + 10 + 35,
924 .vtotal = 600 + 10 + 35 + 2,
925};
926
927static const struct panel_desc auo_g104sn02 = {
928 .modes = &auo_g104sn02_mode,
929 .num_modes = 1,
930 .bpc = 8,
931 .size = {
932 .width = 211,
933 .height = 158,
934 },
935};
936
937static const struct drm_display_mode auo_g121ean01_mode = {
938 .clock = 66700,
939 .hdisplay = 1280,
940 .hsync_start = 1280 + 58,
941 .hsync_end = 1280 + 58 + 8,
942 .htotal = 1280 + 58 + 8 + 70,
943 .vdisplay = 800,
944 .vsync_start = 800 + 6,
945 .vsync_end = 800 + 6 + 4,
946 .vtotal = 800 + 6 + 4 + 10,
947};
948
949static const struct panel_desc auo_g121ean01 = {
950 .modes = &auo_g121ean01_mode,
951 .num_modes = 1,
952 .bpc = 8,
953 .size = {
954 .width = 261,
955 .height = 163,
956 },
957 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
958 .connector_type = DRM_MODE_CONNECTOR_LVDS,
959};
960
961static const struct display_timing auo_g133han01_timings = {
962 .pixelclock = { 134000000, 141200000, 149000000 },
963 .hactive = { 1920, 1920, 1920 },
964 .hfront_porch = { 39, 58, 77 },
965 .hback_porch = { 59, 88, 117 },
966 .hsync_len = { 28, 42, 56 },
967 .vactive = { 1080, 1080, 1080 },
968 .vfront_porch = { 3, 8, 11 },
969 .vback_porch = { 5, 14, 19 },
970 .vsync_len = { 4, 14, 19 },
971};
972
973static const struct panel_desc auo_g133han01 = {
974 .timings = &auo_g133han01_timings,
975 .num_timings = 1,
976 .bpc = 8,
977 .size = {
978 .width = 293,
979 .height = 165,
980 },
981 .delay = {
982 .prepare = 200,
983 .enable = 50,
984 .disable = 50,
985 .unprepare = 1000,
986 },
987 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA,
988 .connector_type = DRM_MODE_CONNECTOR_LVDS,
989};
990
991static const struct drm_display_mode auo_g156xtn01_mode = {
992 .clock = 76000,
993 .hdisplay = 1366,
994 .hsync_start = 1366 + 33,
995 .hsync_end = 1366 + 33 + 67,
996 .htotal = 1560,
997 .vdisplay = 768,
998 .vsync_start = 768 + 4,
999 .vsync_end = 768 + 4 + 4,
1000 .vtotal = 806,
1001};
1002
1003static const struct panel_desc auo_g156xtn01 = {
1004 .modes = &auo_g156xtn01_mode,
1005 .num_modes = 1,
1006 .bpc = 8,
1007 .size = {
1008 .width = 344,
1009 .height = 194,
1010 },
1011 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1012 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1013};
1014
1015static const struct display_timing auo_g185han01_timings = {
1016 .pixelclock = { 120000000, 144000000, 175000000 },
1017 .hactive = { 1920, 1920, 1920 },
1018 .hfront_porch = { 36, 120, 148 },
1019 .hback_porch = { 24, 88, 108 },
1020 .hsync_len = { 20, 48, 64 },
1021 .vactive = { 1080, 1080, 1080 },
1022 .vfront_porch = { 6, 10, 40 },
1023 .vback_porch = { 2, 5, 20 },
1024 .vsync_len = { 2, 5, 20 },
1025};
1026
1027static const struct panel_desc auo_g185han01 = {
1028 .timings = &auo_g185han01_timings,
1029 .num_timings = 1,
1030 .bpc = 8,
1031 .size = {
1032 .width = 409,
1033 .height = 230,
1034 },
1035 .delay = {
1036 .prepare = 50,
1037 .enable = 200,
1038 .disable = 110,
1039 .unprepare = 1000,
1040 },
1041 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1042 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1043};
1044
1045static const struct display_timing auo_g190ean01_timings = {
1046 .pixelclock = { 90000000, 108000000, 135000000 },
1047 .hactive = { 1280, 1280, 1280 },
1048 .hfront_porch = { 126, 184, 1266 },
1049 .hback_porch = { 84, 122, 844 },
1050 .hsync_len = { 70, 102, 704 },
1051 .vactive = { 1024, 1024, 1024 },
1052 .vfront_porch = { 4, 26, 76 },
1053 .vback_porch = { 2, 8, 25 },
1054 .vsync_len = { 2, 8, 25 },
1055};
1056
1057static const struct panel_desc auo_g190ean01 = {
1058 .timings = &auo_g190ean01_timings,
1059 .num_timings = 1,
1060 .bpc = 8,
1061 .size = {
1062 .width = 376,
1063 .height = 301,
1064 },
1065 .delay = {
1066 .prepare = 50,
1067 .enable = 200,
1068 .disable = 110,
1069 .unprepare = 1000,
1070 },
1071 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1072 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1073};
1074
1075static const struct display_timing auo_p320hvn03_timings = {
1076 .pixelclock = { 106000000, 148500000, 164000000 },
1077 .hactive = { 1920, 1920, 1920 },
1078 .hfront_porch = { 25, 50, 130 },
1079 .hback_porch = { 25, 50, 130 },
1080 .hsync_len = { 20, 40, 105 },
1081 .vactive = { 1080, 1080, 1080 },
1082 .vfront_porch = { 8, 17, 150 },
1083 .vback_porch = { 8, 17, 150 },
1084 .vsync_len = { 4, 11, 100 },
1085};
1086
1087static const struct panel_desc auo_p320hvn03 = {
1088 .timings = &auo_p320hvn03_timings,
1089 .num_timings = 1,
1090 .bpc = 8,
1091 .size = {
1092 .width = 698,
1093 .height = 393,
1094 },
1095 .delay = {
1096 .prepare = 1,
1097 .enable = 450,
1098 .unprepare = 500,
1099 },
1100 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1101 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1102};
1103
1104static const struct drm_display_mode auo_t215hvn01_mode = {
1105 .clock = 148800,
1106 .hdisplay = 1920,
1107 .hsync_start = 1920 + 88,
1108 .hsync_end = 1920 + 88 + 44,
1109 .htotal = 1920 + 88 + 44 + 148,
1110 .vdisplay = 1080,
1111 .vsync_start = 1080 + 4,
1112 .vsync_end = 1080 + 4 + 5,
1113 .vtotal = 1080 + 4 + 5 + 36,
1114};
1115
1116static const struct panel_desc auo_t215hvn01 = {
1117 .modes = &auo_t215hvn01_mode,
1118 .num_modes = 1,
1119 .bpc = 8,
1120 .size = {
1121 .width = 430,
1122 .height = 270,
1123 },
1124 .delay = {
1125 .disable = 5,
1126 .unprepare = 1000,
1127 }
1128};
1129
1130static const struct drm_display_mode avic_tm070ddh03_mode = {
1131 .clock = 51200,
1132 .hdisplay = 1024,
1133 .hsync_start = 1024 + 160,
1134 .hsync_end = 1024 + 160 + 4,
1135 .htotal = 1024 + 160 + 4 + 156,
1136 .vdisplay = 600,
1137 .vsync_start = 600 + 17,
1138 .vsync_end = 600 + 17 + 1,
1139 .vtotal = 600 + 17 + 1 + 17,
1140};
1141
1142static const struct panel_desc avic_tm070ddh03 = {
1143 .modes = &avic_tm070ddh03_mode,
1144 .num_modes = 1,
1145 .bpc = 8,
1146 .size = {
1147 .width = 154,
1148 .height = 90,
1149 },
1150 .delay = {
1151 .prepare = 20,
1152 .enable = 200,
1153 .disable = 200,
1154 },
1155};
1156
1157static const struct drm_display_mode bananapi_s070wv20_ct16_mode = {
1158 .clock = 30000,
1159 .hdisplay = 800,
1160 .hsync_start = 800 + 40,
1161 .hsync_end = 800 + 40 + 48,
1162 .htotal = 800 + 40 + 48 + 40,
1163 .vdisplay = 480,
1164 .vsync_start = 480 + 13,
1165 .vsync_end = 480 + 13 + 3,
1166 .vtotal = 480 + 13 + 3 + 29,
1167};
1168
1169static const struct panel_desc bananapi_s070wv20_ct16 = {
1170 .modes = &bananapi_s070wv20_ct16_mode,
1171 .num_modes = 1,
1172 .bpc = 6,
1173 .size = {
1174 .width = 154,
1175 .height = 86,
1176 },
1177};
1178
1179static const struct drm_display_mode boe_hv070wsa_mode = {
1180 .clock = 42105,
1181 .hdisplay = 1024,
1182 .hsync_start = 1024 + 30,
1183 .hsync_end = 1024 + 30 + 30,
1184 .htotal = 1024 + 30 + 30 + 30,
1185 .vdisplay = 600,
1186 .vsync_start = 600 + 10,
1187 .vsync_end = 600 + 10 + 10,
1188 .vtotal = 600 + 10 + 10 + 10,
1189};
1190
1191static const struct panel_desc boe_hv070wsa = {
1192 .modes = &boe_hv070wsa_mode,
1193 .num_modes = 1,
1194 .size = {
1195 .width = 154,
1196 .height = 90,
1197 },
1198};
1199
1200static const struct drm_display_mode boe_nv101wxmn51_modes[] = {
1201 {
1202 .clock = 71900,
1203 .hdisplay = 1280,
1204 .hsync_start = 1280 + 48,
1205 .hsync_end = 1280 + 48 + 32,
1206 .htotal = 1280 + 48 + 32 + 80,
1207 .vdisplay = 800,
1208 .vsync_start = 800 + 3,
1209 .vsync_end = 800 + 3 + 5,
1210 .vtotal = 800 + 3 + 5 + 24,
1211 },
1212 {
1213 .clock = 57500,
1214 .hdisplay = 1280,
1215 .hsync_start = 1280 + 48,
1216 .hsync_end = 1280 + 48 + 32,
1217 .htotal = 1280 + 48 + 32 + 80,
1218 .vdisplay = 800,
1219 .vsync_start = 800 + 3,
1220 .vsync_end = 800 + 3 + 5,
1221 .vtotal = 800 + 3 + 5 + 24,
1222 },
1223};
1224
1225static const struct panel_desc boe_nv101wxmn51 = {
1226 .modes = boe_nv101wxmn51_modes,
1227 .num_modes = ARRAY_SIZE(boe_nv101wxmn51_modes),
1228 .bpc = 8,
1229 .size = {
1230 .width = 217,
1231 .height = 136,
1232 },
1233 .delay = {
1234 .prepare = 210,
1235 .enable = 50,
1236 .unprepare = 160,
1237 },
1238};
1239
1240/* Also used for boe_nv133fhm_n62 */
1241static const struct drm_display_mode boe_nv133fhm_n61_modes = {
1242 .clock = 147840,
1243 .hdisplay = 1920,
1244 .hsync_start = 1920 + 48,
1245 .hsync_end = 1920 + 48 + 32,
1246 .htotal = 1920 + 48 + 32 + 200,
1247 .vdisplay = 1080,
1248 .vsync_start = 1080 + 3,
1249 .vsync_end = 1080 + 3 + 6,
1250 .vtotal = 1080 + 3 + 6 + 31,
1251};
1252
1253/* Also used for boe_nv133fhm_n62 */
1254static const struct panel_desc boe_nv133fhm_n61 = {
1255 .modes = &boe_nv133fhm_n61_modes,
1256 .num_modes = 1,
1257 .bpc = 6,
1258 .size = {
1259 .width = 294,
1260 .height = 165,
1261 },
1262 .delay = {
1263 /*
1264 * When power is first given to the panel there's a short
1265 * spike on the HPD line. It was explained that this spike
1266 * was until the TCON data download was complete. On
1267 * one system this was measured at 8 ms. We'll put 15 ms
1268 * in the prepare delay just to be safe and take it away
1269 * from the hpd_absent_delay (which would otherwise be 200 ms)
1270 * to handle this. That means:
1271 * - If HPD isn't hooked up you still have 200 ms delay.
1272 * - If HPD is hooked up we won't try to look at it for the
1273 * first 15 ms.
1274 */
1275 .prepare = 15,
1276 .hpd_absent_delay = 185,
1277
1278 .unprepare = 500,
1279 },
1280 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1281 .bus_flags = DRM_BUS_FLAG_DATA_MSB_TO_LSB,
1282 .connector_type = DRM_MODE_CONNECTOR_eDP,
1283};
1284
1285static const struct drm_display_mode boe_nv140fhmn49_modes[] = {
1286 {
1287 .clock = 148500,
1288 .hdisplay = 1920,
1289 .hsync_start = 1920 + 48,
1290 .hsync_end = 1920 + 48 + 32,
1291 .htotal = 2200,
1292 .vdisplay = 1080,
1293 .vsync_start = 1080 + 3,
1294 .vsync_end = 1080 + 3 + 5,
1295 .vtotal = 1125,
1296 },
1297};
1298
1299static const struct panel_desc boe_nv140fhmn49 = {
1300 .modes = boe_nv140fhmn49_modes,
1301 .num_modes = ARRAY_SIZE(boe_nv140fhmn49_modes),
1302 .bpc = 6,
1303 .size = {
1304 .width = 309,
1305 .height = 174,
1306 },
1307 .delay = {
1308 .prepare = 210,
1309 .enable = 50,
1310 .unprepare = 160,
1311 },
1312 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1313 .connector_type = DRM_MODE_CONNECTOR_eDP,
1314};
1315
1316static const struct drm_display_mode cdtech_s043wq26h_ct7_mode = {
1317 .clock = 9000,
1318 .hdisplay = 480,
1319 .hsync_start = 480 + 5,
1320 .hsync_end = 480 + 5 + 5,
1321 .htotal = 480 + 5 + 5 + 40,
1322 .vdisplay = 272,
1323 .vsync_start = 272 + 8,
1324 .vsync_end = 272 + 8 + 8,
1325 .vtotal = 272 + 8 + 8 + 8,
1326 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1327};
1328
1329static const struct panel_desc cdtech_s043wq26h_ct7 = {
1330 .modes = &cdtech_s043wq26h_ct7_mode,
1331 .num_modes = 1,
1332 .bpc = 8,
1333 .size = {
1334 .width = 95,
1335 .height = 54,
1336 },
1337 .bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
1338};
1339
1340/* S070PWS19HP-FC21 2017/04/22 */
1341static const struct drm_display_mode cdtech_s070pws19hp_fc21_mode = {
1342 .clock = 51200,
1343 .hdisplay = 1024,
1344 .hsync_start = 1024 + 160,
1345 .hsync_end = 1024 + 160 + 20,
1346 .htotal = 1024 + 160 + 20 + 140,
1347 .vdisplay = 600,
1348 .vsync_start = 600 + 12,
1349 .vsync_end = 600 + 12 + 3,
1350 .vtotal = 600 + 12 + 3 + 20,
1351 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1352};
1353
1354static const struct panel_desc cdtech_s070pws19hp_fc21 = {
1355 .modes = &cdtech_s070pws19hp_fc21_mode,
1356 .num_modes = 1,
1357 .bpc = 6,
1358 .size = {
1359 .width = 154,
1360 .height = 86,
1361 },
1362 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1363 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
1364 .connector_type = DRM_MODE_CONNECTOR_DPI,
1365};
1366
1367/* S070SWV29HG-DC44 2017/09/21 */
1368static const struct drm_display_mode cdtech_s070swv29hg_dc44_mode = {
1369 .clock = 33300,
1370 .hdisplay = 800,
1371 .hsync_start = 800 + 210,
1372 .hsync_end = 800 + 210 + 2,
1373 .htotal = 800 + 210 + 2 + 44,
1374 .vdisplay = 480,
1375 .vsync_start = 480 + 22,
1376 .vsync_end = 480 + 22 + 2,
1377 .vtotal = 480 + 22 + 2 + 21,
1378 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1379};
1380
1381static const struct panel_desc cdtech_s070swv29hg_dc44 = {
1382 .modes = &cdtech_s070swv29hg_dc44_mode,
1383 .num_modes = 1,
1384 .bpc = 6,
1385 .size = {
1386 .width = 154,
1387 .height = 86,
1388 },
1389 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1390 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
1391 .connector_type = DRM_MODE_CONNECTOR_DPI,
1392};
1393
1394static const struct drm_display_mode cdtech_s070wv95_ct16_mode = {
1395 .clock = 35000,
1396 .hdisplay = 800,
1397 .hsync_start = 800 + 40,
1398 .hsync_end = 800 + 40 + 40,
1399 .htotal = 800 + 40 + 40 + 48,
1400 .vdisplay = 480,
1401 .vsync_start = 480 + 29,
1402 .vsync_end = 480 + 29 + 13,
1403 .vtotal = 480 + 29 + 13 + 3,
1404 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1405};
1406
1407static const struct panel_desc cdtech_s070wv95_ct16 = {
1408 .modes = &cdtech_s070wv95_ct16_mode,
1409 .num_modes = 1,
1410 .bpc = 8,
1411 .size = {
1412 .width = 154,
1413 .height = 85,
1414 },
1415};
1416
1417static const struct drm_display_mode chunghwa_claa070wp03xg_mode = {
1418 .clock = 66770,
1419 .hdisplay = 800,
1420 .hsync_start = 800 + 49,
1421 .hsync_end = 800 + 49 + 33,
1422 .htotal = 800 + 49 + 33 + 17,
1423 .vdisplay = 1280,
1424 .vsync_start = 1280 + 1,
1425 .vsync_end = 1280 + 1 + 7,
1426 .vtotal = 1280 + 1 + 7 + 15,
1427 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
1428};
1429
1430static const struct panel_desc chunghwa_claa070wp03xg = {
1431 .modes = &chunghwa_claa070wp03xg_mode,
1432 .num_modes = 1,
1433 .bpc = 6,
1434 .size = {
1435 .width = 94,
1436 .height = 150,
1437 },
1438 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
1439 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
1440 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1441};
1442
1443static const struct drm_display_mode chunghwa_claa101wa01a_mode = {
1444 .clock = 72070,
1445 .hdisplay = 1366,
1446 .hsync_start = 1366 + 58,
1447 .hsync_end = 1366 + 58 + 58,
1448 .htotal = 1366 + 58 + 58 + 58,
1449 .vdisplay = 768,
1450 .vsync_start = 768 + 4,
1451 .vsync_end = 768 + 4 + 4,
1452 .vtotal = 768 + 4 + 4 + 4,
1453};
1454
1455static const struct panel_desc chunghwa_claa101wa01a = {
1456 .modes = &chunghwa_claa101wa01a_mode,
1457 .num_modes = 1,
1458 .bpc = 6,
1459 .size = {
1460 .width = 220,
1461 .height = 120,
1462 },
1463 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
1464 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
1465 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1466};
1467
1468static const struct drm_display_mode chunghwa_claa101wb01_mode = {
1469 .clock = 69300,
1470 .hdisplay = 1366,
1471 .hsync_start = 1366 + 48,
1472 .hsync_end = 1366 + 48 + 32,
1473 .htotal = 1366 + 48 + 32 + 20,
1474 .vdisplay = 768,
1475 .vsync_start = 768 + 16,
1476 .vsync_end = 768 + 16 + 8,
1477 .vtotal = 768 + 16 + 8 + 16,
1478};
1479
1480static const struct panel_desc chunghwa_claa101wb01 = {
1481 .modes = &chunghwa_claa101wb01_mode,
1482 .num_modes = 1,
1483 .bpc = 6,
1484 .size = {
1485 .width = 223,
1486 .height = 125,
1487 },
1488 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
1489 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
1490 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1491};
1492
1493static const struct drm_display_mode dataimage_scf0700c48ggu18_mode = {
1494 .clock = 33260,
1495 .hdisplay = 800,
1496 .hsync_start = 800 + 40,
1497 .hsync_end = 800 + 40 + 128,
1498 .htotal = 800 + 40 + 128 + 88,
1499 .vdisplay = 480,
1500 .vsync_start = 480 + 10,
1501 .vsync_end = 480 + 10 + 2,
1502 .vtotal = 480 + 10 + 2 + 33,
1503 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
1504};
1505
1506static const struct panel_desc dataimage_scf0700c48ggu18 = {
1507 .modes = &dataimage_scf0700c48ggu18_mode,
1508 .num_modes = 1,
1509 .bpc = 8,
1510 .size = {
1511 .width = 152,
1512 .height = 91,
1513 },
1514 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1515 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
1516};
1517
1518static const struct display_timing dlc_dlc0700yzg_1_timing = {
1519 .pixelclock = { 45000000, 51200000, 57000000 },
1520 .hactive = { 1024, 1024, 1024 },
1521 .hfront_porch = { 100, 106, 113 },
1522 .hback_porch = { 100, 106, 113 },
1523 .hsync_len = { 100, 108, 114 },
1524 .vactive = { 600, 600, 600 },
1525 .vfront_porch = { 8, 11, 15 },
1526 .vback_porch = { 8, 11, 15 },
1527 .vsync_len = { 9, 13, 15 },
1528 .flags = DISPLAY_FLAGS_DE_HIGH,
1529};
1530
1531static const struct panel_desc dlc_dlc0700yzg_1 = {
1532 .timings = &dlc_dlc0700yzg_1_timing,
1533 .num_timings = 1,
1534 .bpc = 6,
1535 .size = {
1536 .width = 154,
1537 .height = 86,
1538 },
1539 .delay = {
1540 .prepare = 30,
1541 .enable = 200,
1542 .disable = 200,
1543 },
1544 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
1545 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1546};
1547
1548static const struct display_timing dlc_dlc1010gig_timing = {
1549 .pixelclock = { 68900000, 71100000, 73400000 },
1550 .hactive = { 1280, 1280, 1280 },
1551 .hfront_porch = { 43, 53, 63 },
1552 .hback_porch = { 43, 53, 63 },
1553 .hsync_len = { 44, 54, 64 },
1554 .vactive = { 800, 800, 800 },
1555 .vfront_porch = { 5, 8, 11 },
1556 .vback_porch = { 5, 8, 11 },
1557 .vsync_len = { 5, 7, 11 },
1558 .flags = DISPLAY_FLAGS_DE_HIGH,
1559};
1560
1561static const struct panel_desc dlc_dlc1010gig = {
1562 .timings = &dlc_dlc1010gig_timing,
1563 .num_timings = 1,
1564 .bpc = 8,
1565 .size = {
1566 .width = 216,
1567 .height = 135,
1568 },
1569 .delay = {
1570 .prepare = 60,
1571 .enable = 150,
1572 .disable = 100,
1573 .unprepare = 60,
1574 },
1575 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1576 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1577};
1578
1579static const struct drm_display_mode edt_et035012dm6_mode = {
1580 .clock = 6500,
1581 .hdisplay = 320,
1582 .hsync_start = 320 + 20,
1583 .hsync_end = 320 + 20 + 30,
1584 .htotal = 320 + 20 + 68,
1585 .vdisplay = 240,
1586 .vsync_start = 240 + 4,
1587 .vsync_end = 240 + 4 + 4,
1588 .vtotal = 240 + 4 + 4 + 14,
1589 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
1590};
1591
1592static const struct panel_desc edt_et035012dm6 = {
1593 .modes = &edt_et035012dm6_mode,
1594 .num_modes = 1,
1595 .bpc = 8,
1596 .size = {
1597 .width = 70,
1598 .height = 52,
1599 },
1600 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1601 .bus_flags = DRM_BUS_FLAG_DE_LOW | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE,
1602};
1603
1604static const struct drm_display_mode edt_etm043080dh6gp_mode = {
1605 .clock = 10870,
1606 .hdisplay = 480,
1607 .hsync_start = 480 + 8,
1608 .hsync_end = 480 + 8 + 4,
1609 .htotal = 480 + 8 + 4 + 41,
1610
1611 /*
1612 * IWG22M: Y resolution changed for "dc_linuxfb" module crashing while
1613 * fb_align
1614 */
1615
1616 .vdisplay = 288,
1617 .vsync_start = 288 + 2,
1618 .vsync_end = 288 + 2 + 4,
1619 .vtotal = 288 + 2 + 4 + 10,
1620};
1621
1622static const struct panel_desc edt_etm043080dh6gp = {
1623 .modes = &edt_etm043080dh6gp_mode,
1624 .num_modes = 1,
1625 .bpc = 8,
1626 .size = {
1627 .width = 100,
1628 .height = 65,
1629 },
1630 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1631 .connector_type = DRM_MODE_CONNECTOR_DPI,
1632};
1633
1634static const struct drm_display_mode edt_etm0430g0dh6_mode = {
1635 .clock = 9000,
1636 .hdisplay = 480,
1637 .hsync_start = 480 + 2,
1638 .hsync_end = 480 + 2 + 41,
1639 .htotal = 480 + 2 + 41 + 2,
1640 .vdisplay = 272,
1641 .vsync_start = 272 + 2,
1642 .vsync_end = 272 + 2 + 10,
1643 .vtotal = 272 + 2 + 10 + 2,
1644 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1645};
1646
1647static const struct panel_desc edt_etm0430g0dh6 = {
1648 .modes = &edt_etm0430g0dh6_mode,
1649 .num_modes = 1,
1650 .bpc = 6,
1651 .size = {
1652 .width = 95,
1653 .height = 54,
1654 },
1655};
1656
1657static const struct drm_display_mode edt_et057090dhu_mode = {
1658 .clock = 25175,
1659 .hdisplay = 640,
1660 .hsync_start = 640 + 16,
1661 .hsync_end = 640 + 16 + 30,
1662 .htotal = 640 + 16 + 30 + 114,
1663 .vdisplay = 480,
1664 .vsync_start = 480 + 10,
1665 .vsync_end = 480 + 10 + 3,
1666 .vtotal = 480 + 10 + 3 + 32,
1667 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
1668};
1669
1670static const struct panel_desc edt_et057090dhu = {
1671 .modes = &edt_et057090dhu_mode,
1672 .num_modes = 1,
1673 .bpc = 6,
1674 .size = {
1675 .width = 115,
1676 .height = 86,
1677 },
1678 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1679 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE,
1680 .connector_type = DRM_MODE_CONNECTOR_DPI,
1681};
1682
1683static const struct drm_display_mode edt_etm0700g0dh6_mode = {
1684 .clock = 33260,
1685 .hdisplay = 800,
1686 .hsync_start = 800 + 40,
1687 .hsync_end = 800 + 40 + 128,
1688 .htotal = 800 + 40 + 128 + 88,
1689 .vdisplay = 480,
1690 .vsync_start = 480 + 10,
1691 .vsync_end = 480 + 10 + 2,
1692 .vtotal = 480 + 10 + 2 + 33,
1693 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1694};
1695
1696static const struct panel_desc edt_etm0700g0dh6 = {
1697 .modes = &edt_etm0700g0dh6_mode,
1698 .num_modes = 1,
1699 .bpc = 6,
1700 .size = {
1701 .width = 152,
1702 .height = 91,
1703 },
1704 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1705 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE,
1706};
1707
1708static const struct panel_desc edt_etm0700g0bdh6 = {
1709 .modes = &edt_etm0700g0dh6_mode,
1710 .num_modes = 1,
1711 .bpc = 6,
1712 .size = {
1713 .width = 152,
1714 .height = 91,
1715 },
1716 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1717 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
1718};
1719
1720static const struct display_timing evervision_vgg804821_timing = {
1721 .pixelclock = { 27600000, 33300000, 50000000 },
1722 .hactive = { 800, 800, 800 },
1723 .hfront_porch = { 40, 66, 70 },
1724 .hback_porch = { 40, 67, 70 },
1725 .hsync_len = { 40, 67, 70 },
1726 .vactive = { 480, 480, 480 },
1727 .vfront_porch = { 6, 10, 10 },
1728 .vback_porch = { 7, 11, 11 },
1729 .vsync_len = { 7, 11, 11 },
1730 .flags = DISPLAY_FLAGS_HSYNC_HIGH | DISPLAY_FLAGS_VSYNC_HIGH |
1731 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_NEGEDGE |
1732 DISPLAY_FLAGS_SYNC_NEGEDGE,
1733};
1734
1735static const struct panel_desc evervision_vgg804821 = {
1736 .timings = &evervision_vgg804821_timing,
1737 .num_timings = 1,
1738 .bpc = 8,
1739 .size = {
1740 .width = 108,
1741 .height = 64,
1742 },
1743 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1744 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE,
1745};
1746
1747static const struct drm_display_mode foxlink_fl500wvr00_a0t_mode = {
1748 .clock = 32260,
1749 .hdisplay = 800,
1750 .hsync_start = 800 + 168,
1751 .hsync_end = 800 + 168 + 64,
1752 .htotal = 800 + 168 + 64 + 88,
1753 .vdisplay = 480,
1754 .vsync_start = 480 + 37,
1755 .vsync_end = 480 + 37 + 2,
1756 .vtotal = 480 + 37 + 2 + 8,
1757};
1758
1759static const struct panel_desc foxlink_fl500wvr00_a0t = {
1760 .modes = &foxlink_fl500wvr00_a0t_mode,
1761 .num_modes = 1,
1762 .bpc = 8,
1763 .size = {
1764 .width = 108,
1765 .height = 65,
1766 },
1767 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1768};
1769
1770static const struct drm_display_mode frida_frd350h54004_modes[] = {
1771 { /* 60 Hz */
1772 .clock = 6000,
1773 .hdisplay = 320,
1774 .hsync_start = 320 + 44,
1775 .hsync_end = 320 + 44 + 16,
1776 .htotal = 320 + 44 + 16 + 20,
1777 .vdisplay = 240,
1778 .vsync_start = 240 + 2,
1779 .vsync_end = 240 + 2 + 6,
1780 .vtotal = 240 + 2 + 6 + 2,
1781 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1782 },
1783 { /* 50 Hz */
1784 .clock = 5400,
1785 .hdisplay = 320,
1786 .hsync_start = 320 + 56,
1787 .hsync_end = 320 + 56 + 16,
1788 .htotal = 320 + 56 + 16 + 40,
1789 .vdisplay = 240,
1790 .vsync_start = 240 + 2,
1791 .vsync_end = 240 + 2 + 6,
1792 .vtotal = 240 + 2 + 6 + 2,
1793 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1794 },
1795};
1796
1797static const struct panel_desc frida_frd350h54004 = {
1798 .modes = frida_frd350h54004_modes,
1799 .num_modes = ARRAY_SIZE(frida_frd350h54004_modes),
1800 .bpc = 8,
1801 .size = {
1802 .width = 77,
1803 .height = 64,
1804 },
1805 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1806 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
1807 .connector_type = DRM_MODE_CONNECTOR_DPI,
1808};
1809
1810static const struct drm_display_mode friendlyarm_hd702e_mode = {
1811 .clock = 67185,
1812 .hdisplay = 800,
1813 .hsync_start = 800 + 20,
1814 .hsync_end = 800 + 20 + 24,
1815 .htotal = 800 + 20 + 24 + 20,
1816 .vdisplay = 1280,
1817 .vsync_start = 1280 + 4,
1818 .vsync_end = 1280 + 4 + 8,
1819 .vtotal = 1280 + 4 + 8 + 4,
1820 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
1821};
1822
1823static const struct panel_desc friendlyarm_hd702e = {
1824 .modes = &friendlyarm_hd702e_mode,
1825 .num_modes = 1,
1826 .size = {
1827 .width = 94,
1828 .height = 151,
1829 },
1830};
1831
1832static const struct drm_display_mode giantplus_gpg482739qs5_mode = {
1833 .clock = 9000,
1834 .hdisplay = 480,
1835 .hsync_start = 480 + 5,
1836 .hsync_end = 480 + 5 + 1,
1837 .htotal = 480 + 5 + 1 + 40,
1838 .vdisplay = 272,
1839 .vsync_start = 272 + 8,
1840 .vsync_end = 272 + 8 + 1,
1841 .vtotal = 272 + 8 + 1 + 8,
1842};
1843
1844static const struct panel_desc giantplus_gpg482739qs5 = {
1845 .modes = &giantplus_gpg482739qs5_mode,
1846 .num_modes = 1,
1847 .bpc = 8,
1848 .size = {
1849 .width = 95,
1850 .height = 54,
1851 },
1852 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1853};
1854
1855static const struct display_timing giantplus_gpm940b0_timing = {
1856 .pixelclock = { 13500000, 27000000, 27500000 },
1857 .hactive = { 320, 320, 320 },
1858 .hfront_porch = { 14, 686, 718 },
1859 .hback_porch = { 50, 70, 255 },
1860 .hsync_len = { 1, 1, 1 },
1861 .vactive = { 240, 240, 240 },
1862 .vfront_porch = { 1, 1, 179 },
1863 .vback_porch = { 1, 21, 31 },
1864 .vsync_len = { 1, 1, 6 },
1865 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW,
1866};
1867
1868static const struct panel_desc giantplus_gpm940b0 = {
1869 .timings = &giantplus_gpm940b0_timing,
1870 .num_timings = 1,
1871 .bpc = 8,
1872 .size = {
1873 .width = 60,
1874 .height = 45,
1875 },
1876 .bus_format = MEDIA_BUS_FMT_RGB888_3X8,
1877 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE,
1878};
1879
1880static const struct display_timing hannstar_hsd070pww1_timing = {
1881 .pixelclock = { 64300000, 71100000, 82000000 },
1882 .hactive = { 1280, 1280, 1280 },
1883 .hfront_porch = { 1, 1, 10 },
1884 .hback_porch = { 1, 1, 10 },
1885 /*
1886 * According to the data sheet, the minimum horizontal blanking interval
1887 * is 54 clocks (1 + 52 + 1), but tests with a Nitrogen6X have shown the
1888 * minimum working horizontal blanking interval to be 60 clocks.
1889 */
1890 .hsync_len = { 58, 158, 661 },
1891 .vactive = { 800, 800, 800 },
1892 .vfront_porch = { 1, 1, 10 },
1893 .vback_porch = { 1, 1, 10 },
1894 .vsync_len = { 1, 21, 203 },
1895 .flags = DISPLAY_FLAGS_DE_HIGH,
1896};
1897
1898static const struct panel_desc hannstar_hsd070pww1 = {
1899 .timings = &hannstar_hsd070pww1_timing,
1900 .num_timings = 1,
1901 .bpc = 6,
1902 .size = {
1903 .width = 151,
1904 .height = 94,
1905 },
1906 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
1907 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1908};
1909
1910static const struct display_timing hannstar_hsd100pxn1_timing = {
1911 .pixelclock = { 55000000, 65000000, 75000000 },
1912 .hactive = { 1024, 1024, 1024 },
1913 .hfront_porch = { 40, 40, 40 },
1914 .hback_porch = { 220, 220, 220 },
1915 .hsync_len = { 20, 60, 100 },
1916 .vactive = { 768, 768, 768 },
1917 .vfront_porch = { 7, 7, 7 },
1918 .vback_porch = { 21, 21, 21 },
1919 .vsync_len = { 10, 10, 10 },
1920 .flags = DISPLAY_FLAGS_DE_HIGH,
1921};
1922
1923static const struct panel_desc hannstar_hsd100pxn1 = {
1924 .timings = &hannstar_hsd100pxn1_timing,
1925 .num_timings = 1,
1926 .bpc = 6,
1927 .size = {
1928 .width = 203,
1929 .height = 152,
1930 },
1931 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
1932 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1933};
1934
1935static const struct drm_display_mode hitachi_tx23d38vm0caa_mode = {
1936 .clock = 33333,
1937 .hdisplay = 800,
1938 .hsync_start = 800 + 85,
1939 .hsync_end = 800 + 85 + 86,
1940 .htotal = 800 + 85 + 86 + 85,
1941 .vdisplay = 480,
1942 .vsync_start = 480 + 16,
1943 .vsync_end = 480 + 16 + 13,
1944 .vtotal = 480 + 16 + 13 + 16,
1945};
1946
1947static const struct panel_desc hitachi_tx23d38vm0caa = {
1948 .modes = &hitachi_tx23d38vm0caa_mode,
1949 .num_modes = 1,
1950 .bpc = 6,
1951 .size = {
1952 .width = 195,
1953 .height = 117,
1954 },
1955 .delay = {
1956 .enable = 160,
1957 .disable = 160,
1958 },
1959};
1960
1961static const struct drm_display_mode innolux_at043tn24_mode = {
1962 .clock = 9000,
1963 .hdisplay = 480,
1964 .hsync_start = 480 + 2,
1965 .hsync_end = 480 + 2 + 41,
1966 .htotal = 480 + 2 + 41 + 2,
1967 .vdisplay = 272,
1968 .vsync_start = 272 + 2,
1969 .vsync_end = 272 + 2 + 10,
1970 .vtotal = 272 + 2 + 10 + 2,
1971 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1972};
1973
1974static const struct panel_desc innolux_at043tn24 = {
1975 .modes = &innolux_at043tn24_mode,
1976 .num_modes = 1,
1977 .bpc = 8,
1978 .size = {
1979 .width = 95,
1980 .height = 54,
1981 },
1982 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1983 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
1984};
1985
1986static const struct drm_display_mode innolux_at070tn92_mode = {
1987 .clock = 33333,
1988 .hdisplay = 800,
1989 .hsync_start = 800 + 210,
1990 .hsync_end = 800 + 210 + 20,
1991 .htotal = 800 + 210 + 20 + 46,
1992 .vdisplay = 480,
1993 .vsync_start = 480 + 22,
1994 .vsync_end = 480 + 22 + 10,
1995 .vtotal = 480 + 22 + 23 + 10,
1996};
1997
1998static const struct panel_desc innolux_at070tn92 = {
1999 .modes = &innolux_at070tn92_mode,
2000 .num_modes = 1,
2001 .size = {
2002 .width = 154,
2003 .height = 86,
2004 },
2005 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2006};
2007
2008static const struct display_timing innolux_g070y2_l01_timing = {
2009 .pixelclock = { 28000000, 29500000, 32000000 },
2010 .hactive = { 800, 800, 800 },
2011 .hfront_porch = { 61, 91, 141 },
2012 .hback_porch = { 60, 90, 140 },
2013 .hsync_len = { 12, 12, 12 },
2014 .vactive = { 480, 480, 480 },
2015 .vfront_porch = { 4, 9, 30 },
2016 .vback_porch = { 4, 8, 28 },
2017 .vsync_len = { 2, 2, 2 },
2018 .flags = DISPLAY_FLAGS_DE_HIGH,
2019};
2020
2021static const struct panel_desc innolux_g070y2_l01 = {
2022 .timings = &innolux_g070y2_l01_timing,
2023 .num_timings = 1,
2024 .bpc = 6,
2025 .size = {
2026 .width = 152,
2027 .height = 91,
2028 },
2029 .delay = {
2030 .prepare = 10,
2031 .enable = 100,
2032 .disable = 100,
2033 .unprepare = 800,
2034 },
2035 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2036 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2037};
2038
2039static const struct display_timing innolux_g101ice_l01_timing = {
2040 .pixelclock = { 60400000, 71100000, 74700000 },
2041 .hactive = { 1280, 1280, 1280 },
2042 .hfront_porch = { 41, 80, 100 },
2043 .hback_porch = { 40, 79, 99 },
2044 .hsync_len = { 1, 1, 1 },
2045 .vactive = { 800, 800, 800 },
2046 .vfront_porch = { 5, 11, 14 },
2047 .vback_porch = { 4, 11, 14 },
2048 .vsync_len = { 1, 1, 1 },
2049 .flags = DISPLAY_FLAGS_DE_HIGH,
2050};
2051
2052static const struct panel_desc innolux_g101ice_l01 = {
2053 .timings = &innolux_g101ice_l01_timing,
2054 .num_timings = 1,
2055 .bpc = 8,
2056 .size = {
2057 .width = 217,
2058 .height = 135,
2059 },
2060 .delay = {
2061 .enable = 200,
2062 .disable = 200,
2063 },
2064 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2065 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2066};
2067
2068static const struct display_timing innolux_g121i1_l01_timing = {
2069 .pixelclock = { 67450000, 71000000, 74550000 },
2070 .hactive = { 1280, 1280, 1280 },
2071 .hfront_porch = { 40, 80, 160 },
2072 .hback_porch = { 39, 79, 159 },
2073 .hsync_len = { 1, 1, 1 },
2074 .vactive = { 800, 800, 800 },
2075 .vfront_porch = { 5, 11, 100 },
2076 .vback_porch = { 4, 11, 99 },
2077 .vsync_len = { 1, 1, 1 },
2078};
2079
2080static const struct panel_desc innolux_g121i1_l01 = {
2081 .timings = &innolux_g121i1_l01_timing,
2082 .num_timings = 1,
2083 .bpc = 6,
2084 .size = {
2085 .width = 261,
2086 .height = 163,
2087 },
2088 .delay = {
2089 .enable = 200,
2090 .disable = 20,
2091 },
2092 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2093 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2094};
2095
2096static const struct drm_display_mode innolux_g121x1_l03_mode = {
2097 .clock = 65000,
2098 .hdisplay = 1024,
2099 .hsync_start = 1024 + 0,
2100 .hsync_end = 1024 + 1,
2101 .htotal = 1024 + 0 + 1 + 320,
2102 .vdisplay = 768,
2103 .vsync_start = 768 + 38,
2104 .vsync_end = 768 + 38 + 1,
2105 .vtotal = 768 + 38 + 1 + 0,
2106 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
2107};
2108
2109static const struct panel_desc innolux_g121x1_l03 = {
2110 .modes = &innolux_g121x1_l03_mode,
2111 .num_modes = 1,
2112 .bpc = 6,
2113 .size = {
2114 .width = 246,
2115 .height = 185,
2116 },
2117 .delay = {
2118 .enable = 200,
2119 .unprepare = 200,
2120 .disable = 400,
2121 },
2122};
2123
2124/*
2125 * Datasheet specifies that at 60 Hz refresh rate:
2126 * - total horizontal time: { 1506, 1592, 1716 }
2127 * - total vertical time: { 788, 800, 868 }
2128 *
2129 * ...but doesn't go into exactly how that should be split into a front
2130 * porch, back porch, or sync length. For now we'll leave a single setting
2131 * here which allows a bit of tweaking of the pixel clock at the expense of
2132 * refresh rate.
2133 */
2134static const struct display_timing innolux_n116bge_timing = {
2135 .pixelclock = { 72600000, 76420000, 80240000 },
2136 .hactive = { 1366, 1366, 1366 },
2137 .hfront_porch = { 136, 136, 136 },
2138 .hback_porch = { 60, 60, 60 },
2139 .hsync_len = { 30, 30, 30 },
2140 .vactive = { 768, 768, 768 },
2141 .vfront_porch = { 8, 8, 8 },
2142 .vback_porch = { 12, 12, 12 },
2143 .vsync_len = { 12, 12, 12 },
2144 .flags = DISPLAY_FLAGS_VSYNC_LOW | DISPLAY_FLAGS_HSYNC_LOW,
2145};
2146
2147static const struct panel_desc innolux_n116bge = {
2148 .timings = &innolux_n116bge_timing,
2149 .num_timings = 1,
2150 .bpc = 6,
2151 .size = {
2152 .width = 256,
2153 .height = 144,
2154 },
2155};
2156
2157static const struct drm_display_mode innolux_n156bge_l21_mode = {
2158 .clock = 69300,
2159 .hdisplay = 1366,
2160 .hsync_start = 1366 + 16,
2161 .hsync_end = 1366 + 16 + 34,
2162 .htotal = 1366 + 16 + 34 + 50,
2163 .vdisplay = 768,
2164 .vsync_start = 768 + 2,
2165 .vsync_end = 768 + 2 + 6,
2166 .vtotal = 768 + 2 + 6 + 12,
2167};
2168
2169static const struct panel_desc innolux_n156bge_l21 = {
2170 .modes = &innolux_n156bge_l21_mode,
2171 .num_modes = 1,
2172 .bpc = 6,
2173 .size = {
2174 .width = 344,
2175 .height = 193,
2176 },
2177 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
2178 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
2179 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2180};
2181
2182static const struct drm_display_mode innolux_p120zdg_bf1_mode = {
2183 .clock = 206016,
2184 .hdisplay = 2160,
2185 .hsync_start = 2160 + 48,
2186 .hsync_end = 2160 + 48 + 32,
2187 .htotal = 2160 + 48 + 32 + 80,
2188 .vdisplay = 1440,
2189 .vsync_start = 1440 + 3,
2190 .vsync_end = 1440 + 3 + 10,
2191 .vtotal = 1440 + 3 + 10 + 27,
2192 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
2193};
2194
2195static const struct panel_desc innolux_p120zdg_bf1 = {
2196 .modes = &innolux_p120zdg_bf1_mode,
2197 .num_modes = 1,
2198 .bpc = 8,
2199 .size = {
2200 .width = 254,
2201 .height = 169,
2202 },
2203 .delay = {
2204 .hpd_absent_delay = 200,
2205 .unprepare = 500,
2206 },
2207};
2208
2209static const struct drm_display_mode innolux_zj070na_01p_mode = {
2210 .clock = 51501,
2211 .hdisplay = 1024,
2212 .hsync_start = 1024 + 128,
2213 .hsync_end = 1024 + 128 + 64,
2214 .htotal = 1024 + 128 + 64 + 128,
2215 .vdisplay = 600,
2216 .vsync_start = 600 + 16,
2217 .vsync_end = 600 + 16 + 4,
2218 .vtotal = 600 + 16 + 4 + 16,
2219};
2220
2221static const struct panel_desc innolux_zj070na_01p = {
2222 .modes = &innolux_zj070na_01p_mode,
2223 .num_modes = 1,
2224 .bpc = 6,
2225 .size = {
2226 .width = 154,
2227 .height = 90,
2228 },
2229};
2230
2231static const struct drm_display_mode ivo_m133nwf4_r0_mode = {
2232 .clock = 138778,
2233 .hdisplay = 1920,
2234 .hsync_start = 1920 + 24,
2235 .hsync_end = 1920 + 24 + 48,
2236 .htotal = 1920 + 24 + 48 + 88,
2237 .vdisplay = 1080,
2238 .vsync_start = 1080 + 3,
2239 .vsync_end = 1080 + 3 + 12,
2240 .vtotal = 1080 + 3 + 12 + 17,
2241 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
2242};
2243
2244static const struct panel_desc ivo_m133nwf4_r0 = {
2245 .modes = &ivo_m133nwf4_r0_mode,
2246 .num_modes = 1,
2247 .bpc = 8,
2248 .size = {
2249 .width = 294,
2250 .height = 165,
2251 },
2252 .delay = {
2253 .hpd_absent_delay = 200,
2254 .unprepare = 500,
2255 },
2256 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2257 .bus_flags = DRM_BUS_FLAG_DATA_MSB_TO_LSB,
2258 .connector_type = DRM_MODE_CONNECTOR_eDP,
2259};
2260
2261static const struct display_timing koe_tx14d24vm1bpa_timing = {
2262 .pixelclock = { 5580000, 5850000, 6200000 },
2263 .hactive = { 320, 320, 320 },
2264 .hfront_porch = { 30, 30, 30 },
2265 .hback_porch = { 30, 30, 30 },
2266 .hsync_len = { 1, 5, 17 },
2267 .vactive = { 240, 240, 240 },
2268 .vfront_porch = { 6, 6, 6 },
2269 .vback_porch = { 5, 5, 5 },
2270 .vsync_len = { 1, 2, 11 },
2271 .flags = DISPLAY_FLAGS_DE_HIGH,
2272};
2273
2274static const struct panel_desc koe_tx14d24vm1bpa = {
2275 .timings = &koe_tx14d24vm1bpa_timing,
2276 .num_timings = 1,
2277 .bpc = 6,
2278 .size = {
2279 .width = 115,
2280 .height = 86,
2281 },
2282};
2283
2284static const struct display_timing koe_tx26d202vm0bwa_timing = {
2285 .pixelclock = { 151820000, 156720000, 159780000 },
2286 .hactive = { 1920, 1920, 1920 },
2287 .hfront_porch = { 105, 130, 142 },
2288 .hback_porch = { 45, 70, 82 },
2289 .hsync_len = { 30, 30, 30 },
2290 .vactive = { 1200, 1200, 1200},
2291 .vfront_porch = { 3, 5, 10 },
2292 .vback_porch = { 2, 5, 10 },
2293 .vsync_len = { 5, 5, 5 },
2294};
2295
2296static const struct panel_desc koe_tx26d202vm0bwa = {
2297 .timings = &koe_tx26d202vm0bwa_timing,
2298 .num_timings = 1,
2299 .bpc = 8,
2300 .size = {
2301 .width = 217,
2302 .height = 136,
2303 },
2304 .delay = {
2305 .prepare = 1000,
2306 .enable = 1000,
2307 .unprepare = 1000,
2308 .disable = 1000,
2309 },
2310 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2311 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
2312 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2313};
2314
2315static const struct display_timing koe_tx31d200vm0baa_timing = {
2316 .pixelclock = { 39600000, 43200000, 48000000 },
2317 .hactive = { 1280, 1280, 1280 },
2318 .hfront_porch = { 16, 36, 56 },
2319 .hback_porch = { 16, 36, 56 },
2320 .hsync_len = { 8, 8, 8 },
2321 .vactive = { 480, 480, 480 },
2322 .vfront_porch = { 6, 21, 33 },
2323 .vback_porch = { 6, 21, 33 },
2324 .vsync_len = { 8, 8, 8 },
2325 .flags = DISPLAY_FLAGS_DE_HIGH,
2326};
2327
2328static const struct panel_desc koe_tx31d200vm0baa = {
2329 .timings = &koe_tx31d200vm0baa_timing,
2330 .num_timings = 1,
2331 .bpc = 6,
2332 .size = {
2333 .width = 292,
2334 .height = 109,
2335 },
2336 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
2337 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2338};
2339
2340static const struct display_timing kyo_tcg121xglp_timing = {
2341 .pixelclock = { 52000000, 65000000, 71000000 },
2342 .hactive = { 1024, 1024, 1024 },
2343 .hfront_porch = { 2, 2, 2 },
2344 .hback_porch = { 2, 2, 2 },
2345 .hsync_len = { 86, 124, 244 },
2346 .vactive = { 768, 768, 768 },
2347 .vfront_porch = { 2, 2, 2 },
2348 .vback_porch = { 2, 2, 2 },
2349 .vsync_len = { 6, 34, 73 },
2350 .flags = DISPLAY_FLAGS_DE_HIGH,
2351};
2352
2353static const struct panel_desc kyo_tcg121xglp = {
2354 .timings = &kyo_tcg121xglp_timing,
2355 .num_timings = 1,
2356 .bpc = 8,
2357 .size = {
2358 .width = 246,
2359 .height = 184,
2360 },
2361 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2362 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2363};
2364
2365static const struct drm_display_mode lemaker_bl035_rgb_002_mode = {
2366 .clock = 7000,
2367 .hdisplay = 320,
2368 .hsync_start = 320 + 20,
2369 .hsync_end = 320 + 20 + 30,
2370 .htotal = 320 + 20 + 30 + 38,
2371 .vdisplay = 240,
2372 .vsync_start = 240 + 4,
2373 .vsync_end = 240 + 4 + 3,
2374 .vtotal = 240 + 4 + 3 + 15,
2375};
2376
2377static const struct panel_desc lemaker_bl035_rgb_002 = {
2378 .modes = &lemaker_bl035_rgb_002_mode,
2379 .num_modes = 1,
2380 .size = {
2381 .width = 70,
2382 .height = 52,
2383 },
2384 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2385 .bus_flags = DRM_BUS_FLAG_DE_LOW,
2386};
2387
2388static const struct drm_display_mode lg_lb070wv8_mode = {
2389 .clock = 33246,
2390 .hdisplay = 800,
2391 .hsync_start = 800 + 88,
2392 .hsync_end = 800 + 88 + 80,
2393 .htotal = 800 + 88 + 80 + 88,
2394 .vdisplay = 480,
2395 .vsync_start = 480 + 10,
2396 .vsync_end = 480 + 10 + 25,
2397 .vtotal = 480 + 10 + 25 + 10,
2398};
2399
2400static const struct panel_desc lg_lb070wv8 = {
2401 .modes = &lg_lb070wv8_mode,
2402 .num_modes = 1,
2403 .bpc = 8,
2404 .size = {
2405 .width = 151,
2406 .height = 91,
2407 },
2408 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2409 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2410};
2411
2412static const struct drm_display_mode lg_lp079qx1_sp0v_mode = {
2413 .clock = 200000,
2414 .hdisplay = 1536,
2415 .hsync_start = 1536 + 12,
2416 .hsync_end = 1536 + 12 + 16,
2417 .htotal = 1536 + 12 + 16 + 48,
2418 .vdisplay = 2048,
2419 .vsync_start = 2048 + 8,
2420 .vsync_end = 2048 + 8 + 4,
2421 .vtotal = 2048 + 8 + 4 + 8,
2422 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
2423};
2424
2425static const struct panel_desc lg_lp079qx1_sp0v = {
2426 .modes = &lg_lp079qx1_sp0v_mode,
2427 .num_modes = 1,
2428 .size = {
2429 .width = 129,
2430 .height = 171,
2431 },
2432};
2433
2434static const struct drm_display_mode lg_lp097qx1_spa1_mode = {
2435 .clock = 205210,
2436 .hdisplay = 2048,
2437 .hsync_start = 2048 + 150,
2438 .hsync_end = 2048 + 150 + 5,
2439 .htotal = 2048 + 150 + 5 + 5,
2440 .vdisplay = 1536,
2441 .vsync_start = 1536 + 3,
2442 .vsync_end = 1536 + 3 + 1,
2443 .vtotal = 1536 + 3 + 1 + 9,
2444};
2445
2446static const struct panel_desc lg_lp097qx1_spa1 = {
2447 .modes = &lg_lp097qx1_spa1_mode,
2448 .num_modes = 1,
2449 .size = {
2450 .width = 208,
2451 .height = 147,
2452 },
2453};
2454
2455static const struct drm_display_mode lg_lp120up1_mode = {
2456 .clock = 162300,
2457 .hdisplay = 1920,
2458 .hsync_start = 1920 + 40,
2459 .hsync_end = 1920 + 40 + 40,
2460 .htotal = 1920 + 40 + 40+ 80,
2461 .vdisplay = 1280,
2462 .vsync_start = 1280 + 4,
2463 .vsync_end = 1280 + 4 + 4,
2464 .vtotal = 1280 + 4 + 4 + 12,
2465};
2466
2467static const struct panel_desc lg_lp120up1 = {
2468 .modes = &lg_lp120up1_mode,
2469 .num_modes = 1,
2470 .bpc = 8,
2471 .size = {
2472 .width = 267,
2473 .height = 183,
2474 },
2475 .connector_type = DRM_MODE_CONNECTOR_eDP,
2476};
2477
2478static const struct drm_display_mode lg_lp129qe_mode = {
2479 .clock = 285250,
2480 .hdisplay = 2560,
2481 .hsync_start = 2560 + 48,
2482 .hsync_end = 2560 + 48 + 32,
2483 .htotal = 2560 + 48 + 32 + 80,
2484 .vdisplay = 1700,
2485 .vsync_start = 1700 + 3,
2486 .vsync_end = 1700 + 3 + 10,
2487 .vtotal = 1700 + 3 + 10 + 36,
2488};
2489
2490static const struct panel_desc lg_lp129qe = {
2491 .modes = &lg_lp129qe_mode,
2492 .num_modes = 1,
2493 .bpc = 8,
2494 .size = {
2495 .width = 272,
2496 .height = 181,
2497 },
2498};
2499
2500static const struct display_timing logictechno_lt161010_2nh_timing = {
2501 .pixelclock = { 26400000, 33300000, 46800000 },
2502 .hactive = { 800, 800, 800 },
2503 .hfront_porch = { 16, 210, 354 },
2504 .hback_porch = { 46, 46, 46 },
2505 .hsync_len = { 1, 20, 40 },
2506 .vactive = { 480, 480, 480 },
2507 .vfront_porch = { 7, 22, 147 },
2508 .vback_porch = { 23, 23, 23 },
2509 .vsync_len = { 1, 10, 20 },
2510 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW |
2511 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE |
2512 DISPLAY_FLAGS_SYNC_POSEDGE,
2513};
2514
2515static const struct panel_desc logictechno_lt161010_2nh = {
2516 .timings = &logictechno_lt161010_2nh_timing,
2517 .num_timings = 1,
2518 .size = {
2519 .width = 154,
2520 .height = 86,
2521 },
2522 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
2523 .bus_flags = DRM_BUS_FLAG_DE_HIGH |
2524 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE |
2525 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE,
2526 .connector_type = DRM_MODE_CONNECTOR_DPI,
2527};
2528
2529static const struct display_timing logictechno_lt170410_2whc_timing = {
2530 .pixelclock = { 68900000, 71100000, 73400000 },
2531 .hactive = { 1280, 1280, 1280 },
2532 .hfront_porch = { 23, 60, 71 },
2533 .hback_porch = { 23, 60, 71 },
2534 .hsync_len = { 15, 40, 47 },
2535 .vactive = { 800, 800, 800 },
2536 .vfront_porch = { 5, 7, 10 },
2537 .vback_porch = { 5, 7, 10 },
2538 .vsync_len = { 6, 9, 12 },
2539 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW |
2540 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE |
2541 DISPLAY_FLAGS_SYNC_POSEDGE,
2542};
2543
2544static const struct panel_desc logictechno_lt170410_2whc = {
2545 .timings = &logictechno_lt170410_2whc_timing,
2546 .num_timings = 1,
2547 .size = {
2548 .width = 217,
2549 .height = 136,
2550 },
2551 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2552 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
2553 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2554};
2555
2556static const struct drm_display_mode mitsubishi_aa070mc01_mode = {
2557 .clock = 30400,
2558 .hdisplay = 800,
2559 .hsync_start = 800 + 0,
2560 .hsync_end = 800 + 1,
2561 .htotal = 800 + 0 + 1 + 160,
2562 .vdisplay = 480,
2563 .vsync_start = 480 + 0,
2564 .vsync_end = 480 + 48 + 1,
2565 .vtotal = 480 + 48 + 1 + 0,
2566 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
2567};
2568
2569static const struct drm_display_mode logicpd_type_28_mode = {
2570 .clock = 9107,
2571 .hdisplay = 480,
2572 .hsync_start = 480 + 3,
2573 .hsync_end = 480 + 3 + 42,
2574 .htotal = 480 + 3 + 42 + 2,
2575
2576 .vdisplay = 272,
2577 .vsync_start = 272 + 2,
2578 .vsync_end = 272 + 2 + 11,
2579 .vtotal = 272 + 2 + 11 + 3,
2580 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
2581};
2582
2583static const struct panel_desc logicpd_type_28 = {
2584 .modes = &logicpd_type_28_mode,
2585 .num_modes = 1,
2586 .bpc = 8,
2587 .size = {
2588 .width = 105,
2589 .height = 67,
2590 },
2591 .delay = {
2592 .prepare = 200,
2593 .enable = 200,
2594 .unprepare = 200,
2595 .disable = 200,
2596 },
2597 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2598 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE |
2599 DRM_BUS_FLAG_SYNC_DRIVE_NEGEDGE,
2600 .connector_type = DRM_MODE_CONNECTOR_DPI,
2601};
2602
2603static const struct panel_desc mitsubishi_aa070mc01 = {
2604 .modes = &mitsubishi_aa070mc01_mode,
2605 .num_modes = 1,
2606 .bpc = 8,
2607 .size = {
2608 .width = 152,
2609 .height = 91,
2610 },
2611
2612 .delay = {
2613 .enable = 200,
2614 .unprepare = 200,
2615 .disable = 400,
2616 },
2617 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2618 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2619 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
2620};
2621
2622static const struct display_timing nec_nl12880bc20_05_timing = {
2623 .pixelclock = { 67000000, 71000000, 75000000 },
2624 .hactive = { 1280, 1280, 1280 },
2625 .hfront_porch = { 2, 30, 30 },
2626 .hback_porch = { 6, 100, 100 },
2627 .hsync_len = { 2, 30, 30 },
2628 .vactive = { 800, 800, 800 },
2629 .vfront_porch = { 5, 5, 5 },
2630 .vback_porch = { 11, 11, 11 },
2631 .vsync_len = { 7, 7, 7 },
2632};
2633
2634static const struct panel_desc nec_nl12880bc20_05 = {
2635 .timings = &nec_nl12880bc20_05_timing,
2636 .num_timings = 1,
2637 .bpc = 8,
2638 .size = {
2639 .width = 261,
2640 .height = 163,
2641 },
2642 .delay = {
2643 .enable = 50,
2644 .disable = 50,
2645 },
2646 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2647 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2648};
2649
2650static const struct drm_display_mode nec_nl4827hc19_05b_mode = {
2651 .clock = 10870,
2652 .hdisplay = 480,
2653 .hsync_start = 480 + 2,
2654 .hsync_end = 480 + 2 + 41,
2655 .htotal = 480 + 2 + 41 + 2,
2656 .vdisplay = 272,
2657 .vsync_start = 272 + 2,
2658 .vsync_end = 272 + 2 + 4,
2659 .vtotal = 272 + 2 + 4 + 2,
2660 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
2661};
2662
2663static const struct panel_desc nec_nl4827hc19_05b = {
2664 .modes = &nec_nl4827hc19_05b_mode,
2665 .num_modes = 1,
2666 .bpc = 8,
2667 .size = {
2668 .width = 95,
2669 .height = 54,
2670 },
2671 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2672 .bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
2673};
2674
2675static const struct drm_display_mode netron_dy_e231732_mode = {
2676 .clock = 66000,
2677 .hdisplay = 1024,
2678 .hsync_start = 1024 + 160,
2679 .hsync_end = 1024 + 160 + 70,
2680 .htotal = 1024 + 160 + 70 + 90,
2681 .vdisplay = 600,
2682 .vsync_start = 600 + 127,
2683 .vsync_end = 600 + 127 + 20,
2684 .vtotal = 600 + 127 + 20 + 3,
2685};
2686
2687static const struct panel_desc netron_dy_e231732 = {
2688 .modes = &netron_dy_e231732_mode,
2689 .num_modes = 1,
2690 .size = {
2691 .width = 154,
2692 .height = 87,
2693 },
2694 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
2695};
2696
2697static const struct drm_display_mode neweast_wjfh116008a_modes[] = {
2698 {
2699 .clock = 138500,
2700 .hdisplay = 1920,
2701 .hsync_start = 1920 + 48,
2702 .hsync_end = 1920 + 48 + 32,
2703 .htotal = 1920 + 48 + 32 + 80,
2704 .vdisplay = 1080,
2705 .vsync_start = 1080 + 3,
2706 .vsync_end = 1080 + 3 + 5,
2707 .vtotal = 1080 + 3 + 5 + 23,
2708 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
2709 }, {
2710 .clock = 110920,
2711 .hdisplay = 1920,
2712 .hsync_start = 1920 + 48,
2713 .hsync_end = 1920 + 48 + 32,
2714 .htotal = 1920 + 48 + 32 + 80,
2715 .vdisplay = 1080,
2716 .vsync_start = 1080 + 3,
2717 .vsync_end = 1080 + 3 + 5,
2718 .vtotal = 1080 + 3 + 5 + 23,
2719 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
2720 }
2721};
2722
2723static const struct panel_desc neweast_wjfh116008a = {
2724 .modes = neweast_wjfh116008a_modes,
2725 .num_modes = 2,
2726 .bpc = 6,
2727 .size = {
2728 .width = 260,
2729 .height = 150,
2730 },
2731 .delay = {
2732 .prepare = 110,
2733 .enable = 20,
2734 .unprepare = 500,
2735 },
2736 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
2737 .connector_type = DRM_MODE_CONNECTOR_eDP,
2738};
2739
2740static const struct drm_display_mode newhaven_nhd_43_480272ef_atxl_mode = {
2741 .clock = 9000,
2742 .hdisplay = 480,
2743 .hsync_start = 480 + 2,
2744 .hsync_end = 480 + 2 + 41,
2745 .htotal = 480 + 2 + 41 + 2,
2746 .vdisplay = 272,
2747 .vsync_start = 272 + 2,
2748 .vsync_end = 272 + 2 + 10,
2749 .vtotal = 272 + 2 + 10 + 2,
2750 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
2751};
2752
2753static const struct panel_desc newhaven_nhd_43_480272ef_atxl = {
2754 .modes = &newhaven_nhd_43_480272ef_atxl_mode,
2755 .num_modes = 1,
2756 .bpc = 8,
2757 .size = {
2758 .width = 95,
2759 .height = 54,
2760 },
2761 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2762 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE |
2763 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE,
2764 .connector_type = DRM_MODE_CONNECTOR_DPI,
2765};
2766
2767static const struct display_timing nlt_nl192108ac18_02d_timing = {
2768 .pixelclock = { 130000000, 148350000, 163000000 },
2769 .hactive = { 1920, 1920, 1920 },
2770 .hfront_porch = { 80, 100, 100 },
2771 .hback_porch = { 100, 120, 120 },
2772 .hsync_len = { 50, 60, 60 },
2773 .vactive = { 1080, 1080, 1080 },
2774 .vfront_porch = { 12, 30, 30 },
2775 .vback_porch = { 4, 10, 10 },
2776 .vsync_len = { 4, 5, 5 },
2777};
2778
2779static const struct panel_desc nlt_nl192108ac18_02d = {
2780 .timings = &nlt_nl192108ac18_02d_timing,
2781 .num_timings = 1,
2782 .bpc = 8,
2783 .size = {
2784 .width = 344,
2785 .height = 194,
2786 },
2787 .delay = {
2788 .unprepare = 500,
2789 },
2790 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2791 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2792};
2793
2794static const struct drm_display_mode nvd_9128_mode = {
2795 .clock = 29500,
2796 .hdisplay = 800,
2797 .hsync_start = 800 + 130,
2798 .hsync_end = 800 + 130 + 98,
2799 .htotal = 800 + 0 + 130 + 98,
2800 .vdisplay = 480,
2801 .vsync_start = 480 + 10,
2802 .vsync_end = 480 + 10 + 50,
2803 .vtotal = 480 + 0 + 10 + 50,
2804};
2805
2806static const struct panel_desc nvd_9128 = {
2807 .modes = &nvd_9128_mode,
2808 .num_modes = 1,
2809 .bpc = 8,
2810 .size = {
2811 .width = 156,
2812 .height = 88,
2813 },
2814 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2815 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2816};
2817
2818static const struct display_timing okaya_rs800480t_7x0gp_timing = {
2819 .pixelclock = { 30000000, 30000000, 40000000 },
2820 .hactive = { 800, 800, 800 },
2821 .hfront_porch = { 40, 40, 40 },
2822 .hback_porch = { 40, 40, 40 },
2823 .hsync_len = { 1, 48, 48 },
2824 .vactive = { 480, 480, 480 },
2825 .vfront_porch = { 13, 13, 13 },
2826 .vback_porch = { 29, 29, 29 },
2827 .vsync_len = { 3, 3, 3 },
2828 .flags = DISPLAY_FLAGS_DE_HIGH,
2829};
2830
2831static const struct panel_desc okaya_rs800480t_7x0gp = {
2832 .timings = &okaya_rs800480t_7x0gp_timing,
2833 .num_timings = 1,
2834 .bpc = 6,
2835 .size = {
2836 .width = 154,
2837 .height = 87,
2838 },
2839 .delay = {
2840 .prepare = 41,
2841 .enable = 50,
2842 .unprepare = 41,
2843 .disable = 50,
2844 },
2845 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
2846};
2847
2848static const struct drm_display_mode olimex_lcd_olinuxino_43ts_mode = {
2849 .clock = 9000,
2850 .hdisplay = 480,
2851 .hsync_start = 480 + 5,
2852 .hsync_end = 480 + 5 + 30,
2853 .htotal = 480 + 5 + 30 + 10,
2854 .vdisplay = 272,
2855 .vsync_start = 272 + 8,
2856 .vsync_end = 272 + 8 + 5,
2857 .vtotal = 272 + 8 + 5 + 3,
2858};
2859
2860static const struct panel_desc olimex_lcd_olinuxino_43ts = {
2861 .modes = &olimex_lcd_olinuxino_43ts_mode,
2862 .num_modes = 1,
2863 .size = {
2864 .width = 95,
2865 .height = 54,
2866 },
2867 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2868};
2869
2870/*
2871 * 800x480 CVT. The panel appears to be quite accepting, at least as far as
2872 * pixel clocks, but this is the timing that was being used in the Adafruit
2873 * installation instructions.
2874 */
2875static const struct drm_display_mode ontat_yx700wv03_mode = {
2876 .clock = 29500,
2877 .hdisplay = 800,
2878 .hsync_start = 824,
2879 .hsync_end = 896,
2880 .htotal = 992,
2881 .vdisplay = 480,
2882 .vsync_start = 483,
2883 .vsync_end = 493,
2884 .vtotal = 500,
2885 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
2886};
2887
2888/*
2889 * Specification at:
2890 * https://www.adafruit.com/images/product-files/2406/c3163.pdf
2891 */
2892static const struct panel_desc ontat_yx700wv03 = {
2893 .modes = &ontat_yx700wv03_mode,
2894 .num_modes = 1,
2895 .bpc = 8,
2896 .size = {
2897 .width = 154,
2898 .height = 83,
2899 },
2900 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
2901};
2902
2903static const struct drm_display_mode ortustech_com37h3m_mode = {
2904 .clock = 22230,
2905 .hdisplay = 480,
2906 .hsync_start = 480 + 40,
2907 .hsync_end = 480 + 40 + 10,
2908 .htotal = 480 + 40 + 10 + 40,
2909 .vdisplay = 640,
2910 .vsync_start = 640 + 4,
2911 .vsync_end = 640 + 4 + 2,
2912 .vtotal = 640 + 4 + 2 + 4,
2913 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
2914};
2915
2916static const struct panel_desc ortustech_com37h3m = {
2917 .modes = &ortustech_com37h3m_mode,
2918 .num_modes = 1,
2919 .bpc = 8,
2920 .size = {
2921 .width = 56, /* 56.16mm */
2922 .height = 75, /* 74.88mm */
2923 },
2924 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2925 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE |
2926 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE,
2927};
2928
2929static const struct drm_display_mode ortustech_com43h4m85ulc_mode = {
2930 .clock = 25000,
2931 .hdisplay = 480,
2932 .hsync_start = 480 + 10,
2933 .hsync_end = 480 + 10 + 10,
2934 .htotal = 480 + 10 + 10 + 15,
2935 .vdisplay = 800,
2936 .vsync_start = 800 + 3,
2937 .vsync_end = 800 + 3 + 3,
2938 .vtotal = 800 + 3 + 3 + 3,
2939};
2940
2941static const struct panel_desc ortustech_com43h4m85ulc = {
2942 .modes = &ortustech_com43h4m85ulc_mode,
2943 .num_modes = 1,
2944 .bpc = 8,
2945 .size = {
2946 .width = 56,
2947 .height = 93,
2948 },
2949 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2950 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
2951 .connector_type = DRM_MODE_CONNECTOR_DPI,
2952};
2953
2954static const struct drm_display_mode osddisplays_osd070t1718_19ts_mode = {
2955 .clock = 33000,
2956 .hdisplay = 800,
2957 .hsync_start = 800 + 210,
2958 .hsync_end = 800 + 210 + 30,
2959 .htotal = 800 + 210 + 30 + 16,
2960 .vdisplay = 480,
2961 .vsync_start = 480 + 22,
2962 .vsync_end = 480 + 22 + 13,
2963 .vtotal = 480 + 22 + 13 + 10,
2964 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
2965};
2966
2967static const struct panel_desc osddisplays_osd070t1718_19ts = {
2968 .modes = &osddisplays_osd070t1718_19ts_mode,
2969 .num_modes = 1,
2970 .bpc = 8,
2971 .size = {
2972 .width = 152,
2973 .height = 91,
2974 },
2975 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2976 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE |
2977 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE,
2978 .connector_type = DRM_MODE_CONNECTOR_DPI,
2979};
2980
2981static const struct drm_display_mode pda_91_00156_a0_mode = {
2982 .clock = 33300,
2983 .hdisplay = 800,
2984 .hsync_start = 800 + 1,
2985 .hsync_end = 800 + 1 + 64,
2986 .htotal = 800 + 1 + 64 + 64,
2987 .vdisplay = 480,
2988 .vsync_start = 480 + 1,
2989 .vsync_end = 480 + 1 + 23,
2990 .vtotal = 480 + 1 + 23 + 22,
2991};
2992
2993static const struct panel_desc pda_91_00156_a0 = {
2994 .modes = &pda_91_00156_a0_mode,
2995 .num_modes = 1,
2996 .size = {
2997 .width = 152,
2998 .height = 91,
2999 },
3000 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3001};
3002
3003
3004static const struct drm_display_mode qd43003c0_40_mode = {
3005 .clock = 9000,
3006 .hdisplay = 480,
3007 .hsync_start = 480 + 8,
3008 .hsync_end = 480 + 8 + 4,
3009 .htotal = 480 + 8 + 4 + 39,
3010 .vdisplay = 272,
3011 .vsync_start = 272 + 4,
3012 .vsync_end = 272 + 4 + 10,
3013 .vtotal = 272 + 4 + 10 + 2,
3014};
3015
3016static const struct panel_desc qd43003c0_40 = {
3017 .modes = &qd43003c0_40_mode,
3018 .num_modes = 1,
3019 .bpc = 8,
3020 .size = {
3021 .width = 95,
3022 .height = 53,
3023 },
3024 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3025};
3026
3027static const struct display_timing rocktech_rk070er9427_timing = {
3028 .pixelclock = { 26400000, 33300000, 46800000 },
3029 .hactive = { 800, 800, 800 },
3030 .hfront_porch = { 16, 210, 354 },
3031 .hback_porch = { 46, 46, 46 },
3032 .hsync_len = { 1, 1, 1 },
3033 .vactive = { 480, 480, 480 },
3034 .vfront_porch = { 7, 22, 147 },
3035 .vback_porch = { 23, 23, 23 },
3036 .vsync_len = { 1, 1, 1 },
3037 .flags = DISPLAY_FLAGS_DE_HIGH,
3038};
3039
3040static const struct panel_desc rocktech_rk070er9427 = {
3041 .timings = &rocktech_rk070er9427_timing,
3042 .num_timings = 1,
3043 .bpc = 6,
3044 .size = {
3045 .width = 154,
3046 .height = 86,
3047 },
3048 .delay = {
3049 .prepare = 41,
3050 .enable = 50,
3051 .unprepare = 41,
3052 .disable = 50,
3053 },
3054 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
3055};
3056
3057static const struct drm_display_mode rocktech_rk101ii01d_ct_mode = {
3058 .clock = 71100,
3059 .hdisplay = 1280,
3060 .hsync_start = 1280 + 48,
3061 .hsync_end = 1280 + 48 + 32,
3062 .htotal = 1280 + 48 + 32 + 80,
3063 .vdisplay = 800,
3064 .vsync_start = 800 + 2,
3065 .vsync_end = 800 + 2 + 5,
3066 .vtotal = 800 + 2 + 5 + 16,
3067};
3068
3069static const struct panel_desc rocktech_rk101ii01d_ct = {
3070 .modes = &rocktech_rk101ii01d_ct_mode,
3071 .num_modes = 1,
3072 .size = {
3073 .width = 217,
3074 .height = 136,
3075 },
3076 .delay = {
3077 .prepare = 50,
3078 .disable = 50,
3079 },
3080 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
3081 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
3082 .connector_type = DRM_MODE_CONNECTOR_LVDS,
3083};
3084
3085static const struct drm_display_mode samsung_lsn122dl01_c01_mode = {
3086 .clock = 271560,
3087 .hdisplay = 2560,
3088 .hsync_start = 2560 + 48,
3089 .hsync_end = 2560 + 48 + 32,
3090 .htotal = 2560 + 48 + 32 + 80,
3091 .vdisplay = 1600,
3092 .vsync_start = 1600 + 2,
3093 .vsync_end = 1600 + 2 + 5,
3094 .vtotal = 1600 + 2 + 5 + 57,
3095};
3096
3097static const struct panel_desc samsung_lsn122dl01_c01 = {
3098 .modes = &samsung_lsn122dl01_c01_mode,
3099 .num_modes = 1,
3100 .size = {
3101 .width = 263,
3102 .height = 164,
3103 },
3104};
3105
3106static const struct drm_display_mode samsung_ltn101nt05_mode = {
3107 .clock = 54030,
3108 .hdisplay = 1024,
3109 .hsync_start = 1024 + 24,
3110 .hsync_end = 1024 + 24 + 136,
3111 .htotal = 1024 + 24 + 136 + 160,
3112 .vdisplay = 600,
3113 .vsync_start = 600 + 3,
3114 .vsync_end = 600 + 3 + 6,
3115 .vtotal = 600 + 3 + 6 + 61,
3116};
3117
3118static const struct panel_desc samsung_ltn101nt05 = {
3119 .modes = &samsung_ltn101nt05_mode,
3120 .num_modes = 1,
3121 .bpc = 6,
3122 .size = {
3123 .width = 223,
3124 .height = 125,
3125 },
3126 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
3127 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
3128 .connector_type = DRM_MODE_CONNECTOR_LVDS,
3129};
3130
3131static const struct drm_display_mode samsung_ltn140at29_301_mode = {
3132 .clock = 76300,
3133 .hdisplay = 1366,
3134 .hsync_start = 1366 + 64,
3135 .hsync_end = 1366 + 64 + 48,
3136 .htotal = 1366 + 64 + 48 + 128,
3137 .vdisplay = 768,
3138 .vsync_start = 768 + 2,
3139 .vsync_end = 768 + 2 + 5,
3140 .vtotal = 768 + 2 + 5 + 17,
3141};
3142
3143static const struct panel_desc samsung_ltn140at29_301 = {
3144 .modes = &samsung_ltn140at29_301_mode,
3145 .num_modes = 1,
3146 .bpc = 6,
3147 .size = {
3148 .width = 320,
3149 .height = 187,
3150 },
3151};
3152
3153static const struct display_timing satoz_sat050at40h12r2_timing = {
3154 .pixelclock = {33300000, 33300000, 50000000},
3155 .hactive = {800, 800, 800},
3156 .hfront_porch = {16, 210, 354},
3157 .hback_porch = {46, 46, 46},
3158 .hsync_len = {1, 1, 40},
3159 .vactive = {480, 480, 480},
3160 .vfront_porch = {7, 22, 147},
3161 .vback_porch = {23, 23, 23},
3162 .vsync_len = {1, 1, 20},
3163};
3164
3165static const struct panel_desc satoz_sat050at40h12r2 = {
3166 .timings = &satoz_sat050at40h12r2_timing,
3167 .num_timings = 1,
3168 .bpc = 8,
3169 .size = {
3170 .width = 108,
3171 .height = 65,
3172 },
3173 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
3174 .connector_type = DRM_MODE_CONNECTOR_LVDS,
3175};
3176
3177static const struct drm_display_mode sharp_ld_d5116z01b_mode = {
3178 .clock = 168480,
3179 .hdisplay = 1920,
3180 .hsync_start = 1920 + 48,
3181 .hsync_end = 1920 + 48 + 32,
3182 .htotal = 1920 + 48 + 32 + 80,
3183 .vdisplay = 1280,
3184 .vsync_start = 1280 + 3,
3185 .vsync_end = 1280 + 3 + 10,
3186 .vtotal = 1280 + 3 + 10 + 57,
3187 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
3188};
3189
3190static const struct panel_desc sharp_ld_d5116z01b = {
3191 .modes = &sharp_ld_d5116z01b_mode,
3192 .num_modes = 1,
3193 .bpc = 8,
3194 .size = {
3195 .width = 260,
3196 .height = 120,
3197 },
3198 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3199 .bus_flags = DRM_BUS_FLAG_DATA_MSB_TO_LSB,
3200};
3201
3202static const struct drm_display_mode sharp_lq070y3dg3b_mode = {
3203 .clock = 33260,
3204 .hdisplay = 800,
3205 .hsync_start = 800 + 64,
3206 .hsync_end = 800 + 64 + 128,
3207 .htotal = 800 + 64 + 128 + 64,
3208 .vdisplay = 480,
3209 .vsync_start = 480 + 8,
3210 .vsync_end = 480 + 8 + 2,
3211 .vtotal = 480 + 8 + 2 + 35,
3212 .flags = DISPLAY_FLAGS_PIXDATA_POSEDGE,
3213};
3214
3215static const struct panel_desc sharp_lq070y3dg3b = {
3216 .modes = &sharp_lq070y3dg3b_mode,
3217 .num_modes = 1,
3218 .bpc = 8,
3219 .size = {
3220 .width = 152, /* 152.4mm */
3221 .height = 91, /* 91.4mm */
3222 },
3223 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3224 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE |
3225 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE,
3226};
3227
3228static const struct drm_display_mode sharp_lq035q7db03_mode = {
3229 .clock = 5500,
3230 .hdisplay = 240,
3231 .hsync_start = 240 + 16,
3232 .hsync_end = 240 + 16 + 7,
3233 .htotal = 240 + 16 + 7 + 5,
3234 .vdisplay = 320,
3235 .vsync_start = 320 + 9,
3236 .vsync_end = 320 + 9 + 1,
3237 .vtotal = 320 + 9 + 1 + 7,
3238};
3239
3240static const struct panel_desc sharp_lq035q7db03 = {
3241 .modes = &sharp_lq035q7db03_mode,
3242 .num_modes = 1,
3243 .bpc = 6,
3244 .size = {
3245 .width = 54,
3246 .height = 72,
3247 },
3248 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
3249};
3250
3251static const struct display_timing sharp_lq101k1ly04_timing = {
3252 .pixelclock = { 60000000, 65000000, 80000000 },
3253 .hactive = { 1280, 1280, 1280 },
3254 .hfront_porch = { 20, 20, 20 },
3255 .hback_porch = { 20, 20, 20 },
3256 .hsync_len = { 10, 10, 10 },
3257 .vactive = { 800, 800, 800 },
3258 .vfront_porch = { 4, 4, 4 },
3259 .vback_porch = { 4, 4, 4 },
3260 .vsync_len = { 4, 4, 4 },
3261 .flags = DISPLAY_FLAGS_PIXDATA_POSEDGE,
3262};
3263
3264static const struct panel_desc sharp_lq101k1ly04 = {
3265 .timings = &sharp_lq101k1ly04_timing,
3266 .num_timings = 1,
3267 .bpc = 8,
3268 .size = {
3269 .width = 217,
3270 .height = 136,
3271 },
3272 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA,
3273 .connector_type = DRM_MODE_CONNECTOR_LVDS,
3274};
3275
3276static const struct display_timing sharp_lq123p1jx31_timing = {
3277 .pixelclock = { 252750000, 252750000, 266604720 },
3278 .hactive = { 2400, 2400, 2400 },
3279 .hfront_porch = { 48, 48, 48 },
3280 .hback_porch = { 80, 80, 84 },
3281 .hsync_len = { 32, 32, 32 },
3282 .vactive = { 1600, 1600, 1600 },
3283 .vfront_porch = { 3, 3, 3 },
3284 .vback_porch = { 33, 33, 120 },
3285 .vsync_len = { 10, 10, 10 },
3286 .flags = DISPLAY_FLAGS_VSYNC_LOW | DISPLAY_FLAGS_HSYNC_LOW,
3287};
3288
3289static const struct panel_desc sharp_lq123p1jx31 = {
3290 .timings = &sharp_lq123p1jx31_timing,
3291 .num_timings = 1,
3292 .bpc = 8,
3293 .size = {
3294 .width = 259,
3295 .height = 173,
3296 },
3297 .delay = {
3298 .prepare = 110,
3299 .enable = 50,
3300 .unprepare = 550,
3301 },
3302};
3303
3304static const struct display_timing sharp_ls020b1dd01d_timing = {
3305 .pixelclock = { 2000000, 4200000, 5000000 },
3306 .hactive = { 240, 240, 240 },
3307 .hfront_porch = { 66, 66, 66 },
3308 .hback_porch = { 1, 1, 1 },
3309 .hsync_len = { 1, 1, 1 },
3310 .vactive = { 160, 160, 160 },
3311 .vfront_porch = { 52, 52, 52 },
3312 .vback_porch = { 6, 6, 6 },
3313 .vsync_len = { 10, 10, 10 },
3314 .flags = DISPLAY_FLAGS_HSYNC_HIGH | DISPLAY_FLAGS_VSYNC_LOW,
3315};
3316
3317static const struct panel_desc sharp_ls020b1dd01d = {
3318 .timings = &sharp_ls020b1dd01d_timing,
3319 .num_timings = 1,
3320 .bpc = 6,
3321 .size = {
3322 .width = 42,
3323 .height = 28,
3324 },
3325 .bus_format = MEDIA_BUS_FMT_RGB565_1X16,
3326 .bus_flags = DRM_BUS_FLAG_DE_HIGH
3327 | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE
3328 | DRM_BUS_FLAG_SHARP_SIGNALS,
3329};
3330
3331static const struct drm_display_mode shelly_sca07010_bfn_lnn_mode = {
3332 .clock = 33300,
3333 .hdisplay = 800,
3334 .hsync_start = 800 + 1,
3335 .hsync_end = 800 + 1 + 64,
3336 .htotal = 800 + 1 + 64 + 64,
3337 .vdisplay = 480,
3338 .vsync_start = 480 + 1,
3339 .vsync_end = 480 + 1 + 23,
3340 .vtotal = 480 + 1 + 23 + 22,
3341};
3342
3343static const struct panel_desc shelly_sca07010_bfn_lnn = {
3344 .modes = &shelly_sca07010_bfn_lnn_mode,
3345 .num_modes = 1,
3346 .size = {
3347 .width = 152,
3348 .height = 91,
3349 },
3350 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
3351};
3352
3353static const struct drm_display_mode starry_kr070pe2t_mode = {
3354 .clock = 33000,
3355 .hdisplay = 800,
3356 .hsync_start = 800 + 209,
3357 .hsync_end = 800 + 209 + 1,
3358 .htotal = 800 + 209 + 1 + 45,
3359 .vdisplay = 480,
3360 .vsync_start = 480 + 22,
3361 .vsync_end = 480 + 22 + 1,
3362 .vtotal = 480 + 22 + 1 + 22,
3363};
3364
3365static const struct panel_desc starry_kr070pe2t = {
3366 .modes = &starry_kr070pe2t_mode,
3367 .num_modes = 1,
3368 .bpc = 8,
3369 .size = {
3370 .width = 152,
3371 .height = 86,
3372 },
3373 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3374 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE,
3375 .connector_type = DRM_MODE_CONNECTOR_DPI,
3376};
3377
3378static const struct drm_display_mode starry_kr122ea0sra_mode = {
3379 .clock = 147000,
3380 .hdisplay = 1920,
3381 .hsync_start = 1920 + 16,
3382 .hsync_end = 1920 + 16 + 16,
3383 .htotal = 1920 + 16 + 16 + 32,
3384 .vdisplay = 1200,
3385 .vsync_start = 1200 + 15,
3386 .vsync_end = 1200 + 15 + 2,
3387 .vtotal = 1200 + 15 + 2 + 18,
3388 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
3389};
3390
3391static const struct panel_desc starry_kr122ea0sra = {
3392 .modes = &starry_kr122ea0sra_mode,
3393 .num_modes = 1,
3394 .size = {
3395 .width = 263,
3396 .height = 164,
3397 },
3398 .delay = {
3399 .prepare = 10 + 200,
3400 .enable = 50,
3401 .unprepare = 10 + 500,
3402 },
3403};
3404
3405static const struct drm_display_mode tfc_s9700rtwv43tr_01b_mode = {
3406 .clock = 30000,
3407 .hdisplay = 800,
3408 .hsync_start = 800 + 39,
3409 .hsync_end = 800 + 39 + 47,
3410 .htotal = 800 + 39 + 47 + 39,
3411 .vdisplay = 480,
3412 .vsync_start = 480 + 13,
3413 .vsync_end = 480 + 13 + 2,
3414 .vtotal = 480 + 13 + 2 + 29,
3415};
3416
3417static const struct panel_desc tfc_s9700rtwv43tr_01b = {
3418 .modes = &tfc_s9700rtwv43tr_01b_mode,
3419 .num_modes = 1,
3420 .bpc = 8,
3421 .size = {
3422 .width = 155,
3423 .height = 90,
3424 },
3425 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3426 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
3427};
3428
3429static const struct display_timing tianma_tm070jdhg30_timing = {
3430 .pixelclock = { 62600000, 68200000, 78100000 },
3431 .hactive = { 1280, 1280, 1280 },
3432 .hfront_porch = { 15, 64, 159 },
3433 .hback_porch = { 5, 5, 5 },
3434 .hsync_len = { 1, 1, 256 },
3435 .vactive = { 800, 800, 800 },
3436 .vfront_porch = { 3, 40, 99 },
3437 .vback_porch = { 2, 2, 2 },
3438 .vsync_len = { 1, 1, 128 },
3439 .flags = DISPLAY_FLAGS_DE_HIGH,
3440};
3441
3442static const struct panel_desc tianma_tm070jdhg30 = {
3443 .timings = &tianma_tm070jdhg30_timing,
3444 .num_timings = 1,
3445 .bpc = 8,
3446 .size = {
3447 .width = 151,
3448 .height = 95,
3449 },
3450 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
3451 .connector_type = DRM_MODE_CONNECTOR_LVDS,
3452};
3453
3454static const struct panel_desc tianma_tm070jvhg33 = {
3455 .timings = &tianma_tm070jdhg30_timing,
3456 .num_timings = 1,
3457 .bpc = 8,
3458 .size = {
3459 .width = 150,
3460 .height = 94,
3461 },
3462 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
3463 .connector_type = DRM_MODE_CONNECTOR_LVDS,
3464};
3465
3466static const struct display_timing tianma_tm070rvhg71_timing = {
3467 .pixelclock = { 27700000, 29200000, 39600000 },
3468 .hactive = { 800, 800, 800 },
3469 .hfront_porch = { 12, 40, 212 },
3470 .hback_porch = { 88, 88, 88 },
3471 .hsync_len = { 1, 1, 40 },
3472 .vactive = { 480, 480, 480 },
3473 .vfront_porch = { 1, 13, 88 },
3474 .vback_porch = { 32, 32, 32 },
3475 .vsync_len = { 1, 1, 3 },
3476 .flags = DISPLAY_FLAGS_DE_HIGH,
3477};
3478
3479static const struct panel_desc tianma_tm070rvhg71 = {
3480 .timings = &tianma_tm070rvhg71_timing,
3481 .num_timings = 1,
3482 .bpc = 8,
3483 .size = {
3484 .width = 154,
3485 .height = 86,
3486 },
3487 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
3488 .connector_type = DRM_MODE_CONNECTOR_LVDS,
3489};
3490
3491static const struct drm_display_mode ti_nspire_cx_lcd_mode[] = {
3492 {
3493 .clock = 10000,
3494 .hdisplay = 320,
3495 .hsync_start = 320 + 50,
3496 .hsync_end = 320 + 50 + 6,
3497 .htotal = 320 + 50 + 6 + 38,
3498 .vdisplay = 240,
3499 .vsync_start = 240 + 3,
3500 .vsync_end = 240 + 3 + 1,
3501 .vtotal = 240 + 3 + 1 + 17,
3502 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
3503 },
3504};
3505
3506static const struct panel_desc ti_nspire_cx_lcd_panel = {
3507 .modes = ti_nspire_cx_lcd_mode,
3508 .num_modes = 1,
3509 .bpc = 8,
3510 .size = {
3511 .width = 65,
3512 .height = 49,
3513 },
3514 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3515 .bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE,
3516};
3517
3518static const struct drm_display_mode ti_nspire_classic_lcd_mode[] = {
3519 {
3520 .clock = 10000,
3521 .hdisplay = 320,
3522 .hsync_start = 320 + 6,
3523 .hsync_end = 320 + 6 + 6,
3524 .htotal = 320 + 6 + 6 + 6,
3525 .vdisplay = 240,
3526 .vsync_start = 240 + 0,
3527 .vsync_end = 240 + 0 + 1,
3528 .vtotal = 240 + 0 + 1 + 0,
3529 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
3530 },
3531};
3532
3533static const struct panel_desc ti_nspire_classic_lcd_panel = {
3534 .modes = ti_nspire_classic_lcd_mode,
3535 .num_modes = 1,
3536 /* The grayscale panel has 8 bit for the color .. Y (black) */
3537 .bpc = 8,
3538 .size = {
3539 .width = 71,
3540 .height = 53,
3541 },
3542 /* This is the grayscale bus format */
3543 .bus_format = MEDIA_BUS_FMT_Y8_1X8,
3544 .bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
3545};
3546
3547static const struct drm_display_mode toshiba_lt089ac29000_mode = {
3548 .clock = 79500,
3549 .hdisplay = 1280,
3550 .hsync_start = 1280 + 192,
3551 .hsync_end = 1280 + 192 + 128,
3552 .htotal = 1280 + 192 + 128 + 64,
3553 .vdisplay = 768,
3554 .vsync_start = 768 + 20,
3555 .vsync_end = 768 + 20 + 7,
3556 .vtotal = 768 + 20 + 7 + 3,
3557};
3558
3559static const struct panel_desc toshiba_lt089ac29000 = {
3560 .modes = &toshiba_lt089ac29000_mode,
3561 .num_modes = 1,
3562 .size = {
3563 .width = 194,
3564 .height = 116,
3565 },
3566 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA,
3567 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
3568 .connector_type = DRM_MODE_CONNECTOR_LVDS,
3569};
3570
3571static const struct drm_display_mode tpk_f07a_0102_mode = {
3572 .clock = 33260,
3573 .hdisplay = 800,
3574 .hsync_start = 800 + 40,
3575 .hsync_end = 800 + 40 + 128,
3576 .htotal = 800 + 40 + 128 + 88,
3577 .vdisplay = 480,
3578 .vsync_start = 480 + 10,
3579 .vsync_end = 480 + 10 + 2,
3580 .vtotal = 480 + 10 + 2 + 33,
3581};
3582
3583static const struct panel_desc tpk_f07a_0102 = {
3584 .modes = &tpk_f07a_0102_mode,
3585 .num_modes = 1,
3586 .size = {
3587 .width = 152,
3588 .height = 91,
3589 },
3590 .bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
3591};
3592
3593static const struct drm_display_mode tpk_f10a_0102_mode = {
3594 .clock = 45000,
3595 .hdisplay = 1024,
3596 .hsync_start = 1024 + 176,
3597 .hsync_end = 1024 + 176 + 5,
3598 .htotal = 1024 + 176 + 5 + 88,
3599 .vdisplay = 600,
3600 .vsync_start = 600 + 20,
3601 .vsync_end = 600 + 20 + 5,
3602 .vtotal = 600 + 20 + 5 + 25,
3603};
3604
3605static const struct panel_desc tpk_f10a_0102 = {
3606 .modes = &tpk_f10a_0102_mode,
3607 .num_modes = 1,
3608 .size = {
3609 .width = 223,
3610 .height = 125,
3611 },
3612};
3613
3614static const struct display_timing urt_umsh_8596md_timing = {
3615 .pixelclock = { 33260000, 33260000, 33260000 },
3616 .hactive = { 800, 800, 800 },
3617 .hfront_porch = { 41, 41, 41 },
3618 .hback_porch = { 216 - 128, 216 - 128, 216 - 128 },
3619 .hsync_len = { 71, 128, 128 },
3620 .vactive = { 480, 480, 480 },
3621 .vfront_porch = { 10, 10, 10 },
3622 .vback_porch = { 35 - 2, 35 - 2, 35 - 2 },
3623 .vsync_len = { 2, 2, 2 },
3624 .flags = DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_NEGEDGE |
3625 DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW,
3626};
3627
3628static const struct panel_desc urt_umsh_8596md_lvds = {
3629 .timings = &urt_umsh_8596md_timing,
3630 .num_timings = 1,
3631 .bpc = 6,
3632 .size = {
3633 .width = 152,
3634 .height = 91,
3635 },
3636 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
3637 .connector_type = DRM_MODE_CONNECTOR_LVDS,
3638};
3639
3640static const struct panel_desc urt_umsh_8596md_parallel = {
3641 .timings = &urt_umsh_8596md_timing,
3642 .num_timings = 1,
3643 .bpc = 6,
3644 .size = {
3645 .width = 152,
3646 .height = 91,
3647 },
3648 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
3649};
3650
3651static const struct drm_display_mode vl050_8048nt_c01_mode = {
3652 .clock = 33333,
3653 .hdisplay = 800,
3654 .hsync_start = 800 + 210,
3655 .hsync_end = 800 + 210 + 20,
3656 .htotal = 800 + 210 + 20 + 46,
3657 .vdisplay = 480,
3658 .vsync_start = 480 + 22,
3659 .vsync_end = 480 + 22 + 10,
3660 .vtotal = 480 + 22 + 10 + 23,
3661 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
3662};
3663
3664static const struct panel_desc vl050_8048nt_c01 = {
3665 .modes = &vl050_8048nt_c01_mode,
3666 .num_modes = 1,
3667 .bpc = 8,
3668 .size = {
3669 .width = 120,
3670 .height = 76,
3671 },
3672 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3673 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
3674};
3675
3676static const struct drm_display_mode winstar_wf35ltiacd_mode = {
3677 .clock = 6410,
3678 .hdisplay = 320,
3679 .hsync_start = 320 + 20,
3680 .hsync_end = 320 + 20 + 30,
3681 .htotal = 320 + 20 + 30 + 38,
3682 .vdisplay = 240,
3683 .vsync_start = 240 + 4,
3684 .vsync_end = 240 + 4 + 3,
3685 .vtotal = 240 + 4 + 3 + 15,
3686 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
3687};
3688
3689static const struct panel_desc winstar_wf35ltiacd = {
3690 .modes = &winstar_wf35ltiacd_mode,
3691 .num_modes = 1,
3692 .bpc = 8,
3693 .size = {
3694 .width = 70,
3695 .height = 53,
3696 },
3697 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3698};
3699
3700static const struct drm_display_mode arm_rtsm_mode[] = {
3701 {
3702 .clock = 65000,
3703 .hdisplay = 1024,
3704 .hsync_start = 1024 + 24,
3705 .hsync_end = 1024 + 24 + 136,
3706 .htotal = 1024 + 24 + 136 + 160,
3707 .vdisplay = 768,
3708 .vsync_start = 768 + 3,
3709 .vsync_end = 768 + 3 + 6,
3710 .vtotal = 768 + 3 + 6 + 29,
3711 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
3712 },
3713};
3714
3715static const struct panel_desc arm_rtsm = {
3716 .modes = arm_rtsm_mode,
3717 .num_modes = 1,
3718 .bpc = 8,
3719 .size = {
3720 .width = 400,
3721 .height = 300,
3722 },
3723 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3724};
3725
3726static const struct of_device_id platform_of_match[] = {
3727 {
3728 .compatible = "ampire,am-480272h3tmqw-t01h",
3729 .data = &ire_am_480272h3tmqw_t01h,
3730 }, {
3731 .compatible = "ampire,am800480r3tmqwa1h",
3732 .data = &ire_am800480r3tmqwa1h,
3733 }, {
3734 .compatible = "arm,rtsm-display",
3735 .data = &arm_rtsm,
3736 }, {
3737 .compatible = "armadeus,st0700-adapt",
3738 .data = &armadeus_st0700_adapt,
3739 }, {
3740 .compatible = "auo,b101aw03",
3741 .data = &auo_b101aw03,
3742 }, {
3743 .compatible = "auo,b101ean01",
3744 .data = &auo_b101ean01,
3745 }, {
3746 .compatible = "auo,b101xtn01",
3747 .data = &auo_b101xtn01,
3748 }, {
3749 .compatible = "auo,b116xa01",
3750 .data = &auo_b116xak01,
3751 }, {
3752 .compatible = "auo,b116xw03",
3753 .data = &auo_b116xw03,
3754 }, {
3755 .compatible = "auo,b133htn01",
3756 .data = &auo_b133htn01,
3757 }, {
3758 .compatible = "auo,b133xtn01",
3759 .data = &auo_b133xtn01,
3760 }, {
3761 .compatible = "auo,g070vvn01",
3762 .data = &auo_g070vvn01,
3763 }, {
3764 .compatible = "auo,g101evn010",
3765 .data = &auo_g101evn010,
3766 }, {
3767 .compatible = "auo,g104sn02",
3768 .data = &auo_g104sn02,
3769 }, {
3770 .compatible = "auo,g121ean01",
3771 .data = &auo_g121ean01,
3772 }, {
3773 .compatible = "auo,g133han01",
3774 .data = &auo_g133han01,
3775 }, {
3776 .compatible = "auo,g156xtn01",
3777 .data = &auo_g156xtn01,
3778 }, {
3779 .compatible = "auo,g185han01",
3780 .data = &auo_g185han01,
3781 }, {
3782 .compatible = "auo,g190ean01",
3783 .data = &auo_g190ean01,
3784 }, {
3785 .compatible = "auo,p320hvn03",
3786 .data = &auo_p320hvn03,
3787 }, {
3788 .compatible = "auo,t215hvn01",
3789 .data = &auo_t215hvn01,
3790 }, {
3791 .compatible = "avic,tm070ddh03",
3792 .data = &avic_tm070ddh03,
3793 }, {
3794 .compatible = "bananapi,s070wv20-ct16",
3795 .data = &bananapi_s070wv20_ct16,
3796 }, {
3797 .compatible = "boe,hv070wsa-100",
3798 .data = &boe_hv070wsa
3799 }, {
3800 .compatible = "boe,nv101wxmn51",
3801 .data = &boe_nv101wxmn51,
3802 }, {
3803 .compatible = "boe,nv133fhm-n61",
3804 .data = &boe_nv133fhm_n61,
3805 }, {
3806 .compatible = "boe,nv133fhm-n62",
3807 .data = &boe_nv133fhm_n61,
3808 }, {
3809 .compatible = "boe,nv140fhmn49",
3810 .data = &boe_nv140fhmn49,
3811 }, {
3812 .compatible = "cdtech,s043wq26h-ct7",
3813 .data = &cdtech_s043wq26h_ct7,
3814 }, {
3815 .compatible = "cdtech,s070pws19hp-fc21",
3816 .data = &cdtech_s070pws19hp_fc21,
3817 }, {
3818 .compatible = "cdtech,s070swv29hg-dc44",
3819 .data = &cdtech_s070swv29hg_dc44,
3820 }, {
3821 .compatible = "cdtech,s070wv95-ct16",
3822 .data = &cdtech_s070wv95_ct16,
3823 }, {
3824 .compatible = "chunghwa,claa070wp03xg",
3825 .data = &chunghwa_claa070wp03xg,
3826 }, {
3827 .compatible = "chunghwa,claa101wa01a",
3828 .data = &chunghwa_claa101wa01a
3829 }, {
3830 .compatible = "chunghwa,claa101wb01",
3831 .data = &chunghwa_claa101wb01
3832 }, {
3833 .compatible = "dataimage,scf0700c48ggu18",
3834 .data = &dataimage_scf0700c48ggu18,
3835 }, {
3836 .compatible = "dlc,dlc0700yzg-1",
3837 .data = &dlc_dlc0700yzg_1,
3838 }, {
3839 .compatible = "dlc,dlc1010gig",
3840 .data = &dlc_dlc1010gig,
3841 }, {
3842 .compatible = "edt,et035012dm6",
3843 .data = &edt_et035012dm6,
3844 }, {
3845 .compatible = "edt,etm043080dh6gp",
3846 .data = &edt_etm043080dh6gp,
3847 }, {
3848 .compatible = "edt,etm0430g0dh6",
3849 .data = &edt_etm0430g0dh6,
3850 }, {
3851 .compatible = "edt,et057090dhu",
3852 .data = &edt_et057090dhu,
3853 }, {
3854 .compatible = "edt,et070080dh6",
3855 .data = &edt_etm0700g0dh6,
3856 }, {
3857 .compatible = "edt,etm0700g0dh6",
3858 .data = &edt_etm0700g0dh6,
3859 }, {
3860 .compatible = "edt,etm0700g0bdh6",
3861 .data = &edt_etm0700g0bdh6,
3862 }, {
3863 .compatible = "edt,etm0700g0edh6",
3864 .data = &edt_etm0700g0bdh6,
3865 }, {
3866 .compatible = "evervision,vgg804821",
3867 .data = &evervision_vgg804821,
3868 }, {
3869 .compatible = "foxlink,fl500wvr00-a0t",
3870 .data = &foxlink_fl500wvr00_a0t,
3871 }, {
3872 .compatible = "frida,frd350h54004",
3873 .data = &frida_frd350h54004,
3874 }, {
3875 .compatible = "friendlyarm,hd702e",
3876 .data = &friendlyarm_hd702e,
3877 }, {
3878 .compatible = "giantplus,gpg482739qs5",
3879 .data = &giantplus_gpg482739qs5
3880 }, {
3881 .compatible = "giantplus,gpm940b0",
3882 .data = &giantplus_gpm940b0,
3883 }, {
3884 .compatible = "hannstar,hsd070pww1",
3885 .data = &hannstar_hsd070pww1,
3886 }, {
3887 .compatible = "hannstar,hsd100pxn1",
3888 .data = &hannstar_hsd100pxn1,
3889 }, {
3890 .compatible = "hit,tx23d38vm0caa",
3891 .data = &hitachi_tx23d38vm0caa
3892 }, {
3893 .compatible = "innolux,at043tn24",
3894 .data = &innolux_at043tn24,
3895 }, {
3896 .compatible = "innolux,at070tn92",
3897 .data = &innolux_at070tn92,
3898 }, {
3899 .compatible = "innolux,g070y2-l01",
3900 .data = &innolux_g070y2_l01,
3901 }, {
3902 .compatible = "innolux,g101ice-l01",
3903 .data = &innolux_g101ice_l01
3904 }, {
3905 .compatible = "innolux,g121i1-l01",
3906 .data = &innolux_g121i1_l01
3907 }, {
3908 .compatible = "innolux,g121x1-l03",
3909 .data = &innolux_g121x1_l03,
3910 }, {
3911 .compatible = "innolux,n116bge",
3912 .data = &innolux_n116bge,
3913 }, {
3914 .compatible = "innolux,n156bge-l21",
3915 .data = &innolux_n156bge_l21,
3916 }, {
3917 .compatible = "innolux,p120zdg-bf1",
3918 .data = &innolux_p120zdg_bf1,
3919 }, {
3920 .compatible = "innolux,zj070na-01p",
3921 .data = &innolux_zj070na_01p,
3922 }, {
3923 .compatible = "ivo,m133nwf4-r0",
3924 .data = &ivo_m133nwf4_r0,
3925 }, {
3926 .compatible = "koe,tx14d24vm1bpa",
3927 .data = &koe_tx14d24vm1bpa,
3928 }, {
3929 .compatible = "koe,tx26d202vm0bwa",
3930 .data = &koe_tx26d202vm0bwa,
3931 }, {
3932 .compatible = "koe,tx31d200vm0baa",
3933 .data = &koe_tx31d200vm0baa,
3934 }, {
3935 .compatible = "kyo,tcg121xglp",
3936 .data = &kyo_tcg121xglp,
3937 }, {
3938 .compatible = "lemaker,bl035-rgb-002",
3939 .data = &lemaker_bl035_rgb_002,
3940 }, {
3941 .compatible = "lg,lb070wv8",
3942 .data = &lg_lb070wv8,
3943 }, {
3944 .compatible = "lg,lp079qx1-sp0v",
3945 .data = &lg_lp079qx1_sp0v,
3946 }, {
3947 .compatible = "lg,lp097qx1-spa1",
3948 .data = &lg_lp097qx1_spa1,
3949 }, {
3950 .compatible = "lg,lp120up1",
3951 .data = &lg_lp120up1,
3952 }, {
3953 .compatible = "lg,lp129qe",
3954 .data = &lg_lp129qe,
3955 }, {
3956 .compatible = "logicpd,type28",
3957 .data = &logicpd_type_28,
3958 }, {
3959 .compatible = "logictechno,lt161010-2nhc",
3960 .data = &logictechno_lt161010_2nh,
3961 }, {
3962 .compatible = "logictechno,lt161010-2nhr",
3963 .data = &logictechno_lt161010_2nh,
3964 }, {
3965 .compatible = "logictechno,lt170410-2whc",
3966 .data = &logictechno_lt170410_2whc,
3967 }, {
3968 .compatible = "mitsubishi,aa070mc01-ca1",
3969 .data = &mitsubishi_aa070mc01,
3970 }, {
3971 .compatible = "nec,nl12880bc20-05",
3972 .data = &nec_nl12880bc20_05,
3973 }, {
3974 .compatible = "nec,nl4827hc19-05b",
3975 .data = &nec_nl4827hc19_05b,
3976 }, {
3977 .compatible = "netron-dy,e231732",
3978 .data = &netron_dy_e231732,
3979 }, {
3980 .compatible = "neweast,wjfh116008a",
3981 .data = &neweast_wjfh116008a,
3982 }, {
3983 .compatible = "newhaven,nhd-4.3-480272ef-atxl",
3984 .data = &newhaven_nhd_43_480272ef_atxl,
3985 }, {
3986 .compatible = "nlt,nl192108ac18-02d",
3987 .data = &nlt_nl192108ac18_02d,
3988 }, {
3989 .compatible = "nvd,9128",
3990 .data = &nvd_9128,
3991 }, {
3992 .compatible = "okaya,rs800480t-7x0gp",
3993 .data = &okaya_rs800480t_7x0gp,
3994 }, {
3995 .compatible = "olimex,lcd-olinuxino-43-ts",
3996 .data = &olimex_lcd_olinuxino_43ts,
3997 }, {
3998 .compatible = "ontat,yx700wv03",
3999 .data = &ontat_yx700wv03,
4000 }, {
4001 .compatible = "ortustech,com37h3m05dtc",
4002 .data = &ortustech_com37h3m,
4003 }, {
4004 .compatible = "ortustech,com37h3m99dtc",
4005 .data = &ortustech_com37h3m,
4006 }, {
4007 .compatible = "ortustech,com43h4m85ulc",
4008 .data = &ortustech_com43h4m85ulc,
4009 }, {
4010 .compatible = "osddisplays,osd070t1718-19ts",
4011 .data = &osddisplays_osd070t1718_19ts,
4012 }, {
4013 .compatible = "pda,91-00156-a0",
4014 .data = &pda_91_00156_a0,
4015 }, {
4016 .compatible = "qiaodian,qd43003c0-40",
4017 .data = &qd43003c0_40,
4018 }, {
4019 .compatible = "rocktech,rk070er9427",
4020 .data = &rocktech_rk070er9427,
4021 }, {
4022 .compatible = "rocktech,rk101ii01d-ct",
4023 .data = &rocktech_rk101ii01d_ct,
4024 }, {
4025 .compatible = "samsung,lsn122dl01-c01",
4026 .data = &samsung_lsn122dl01_c01,
4027 }, {
4028 .compatible = "samsung,ltn101nt05",
4029 .data = &samsung_ltn101nt05,
4030 }, {
4031 .compatible = "samsung,ltn140at29-301",
4032 .data = &samsung_ltn140at29_301,
4033 }, {
4034 .compatible = "satoz,sat050at40h12r2",
4035 .data = &satoz_sat050at40h12r2,
4036 }, {
4037 .compatible = "sharp,ld-d5116z01b",
4038 .data = &sharp_ld_d5116z01b,
4039 }, {
4040 .compatible = "sharp,lq035q7db03",
4041 .data = &sharp_lq035q7db03,
4042 }, {
4043 .compatible = "sharp,lq070y3dg3b",
4044 .data = &sharp_lq070y3dg3b,
4045 }, {
4046 .compatible = "sharp,lq101k1ly04",
4047 .data = &sharp_lq101k1ly04,
4048 }, {
4049 .compatible = "sharp,lq123p1jx31",
4050 .data = &sharp_lq123p1jx31,
4051 }, {
4052 .compatible = "sharp,ls020b1dd01d",
4053 .data = &sharp_ls020b1dd01d,
4054 }, {
4055 .compatible = "shelly,sca07010-bfn-lnn",
4056 .data = &shelly_sca07010_bfn_lnn,
4057 }, {
4058 .compatible = "starry,kr070pe2t",
4059 .data = &starry_kr070pe2t,
4060 }, {
4061 .compatible = "starry,kr122ea0sra",
4062 .data = &starry_kr122ea0sra,
4063 }, {
4064 .compatible = "tfc,s9700rtwv43tr-01b",
4065 .data = &tfc_s9700rtwv43tr_01b,
4066 }, {
4067 .compatible = "tianma,tm070jdhg30",
4068 .data = &tianma_tm070jdhg30,
4069 }, {
4070 .compatible = "tianma,tm070jvhg33",
4071 .data = &tianma_tm070jvhg33,
4072 }, {
4073 .compatible = "tianma,tm070rvhg71",
4074 .data = &tianma_tm070rvhg71,
4075 }, {
4076 .compatible = "ti,nspire-cx-lcd-panel",
4077 .data = &ti_nspire_cx_lcd_panel,
4078 }, {
4079 .compatible = "ti,nspire-classic-lcd-panel",
4080 .data = &ti_nspire_classic_lcd_panel,
4081 }, {
4082 .compatible = "toshiba,lt089ac29000",
4083 .data = &toshiba_lt089ac29000,
4084 }, {
4085 .compatible = "tpk,f07a-0102",
4086 .data = &tpk_f07a_0102,
4087 }, {
4088 .compatible = "tpk,f10a-0102",
4089 .data = &tpk_f10a_0102,
4090 }, {
4091 .compatible = "urt,umsh-8596md-t",
4092 .data = &urt_umsh_8596md_parallel,
4093 }, {
4094 .compatible = "urt,umsh-8596md-1t",
4095 .data = &urt_umsh_8596md_parallel,
4096 }, {
4097 .compatible = "urt,umsh-8596md-7t",
4098 .data = &urt_umsh_8596md_parallel,
4099 }, {
4100 .compatible = "urt,umsh-8596md-11t",
4101 .data = &urt_umsh_8596md_lvds,
4102 }, {
4103 .compatible = "urt,umsh-8596md-19t",
4104 .data = &urt_umsh_8596md_lvds,
4105 }, {
4106 .compatible = "urt,umsh-8596md-20t",
4107 .data = &urt_umsh_8596md_parallel,
4108 }, {
4109 .compatible = "vxt,vl050-8048nt-c01",
4110 .data = &vl050_8048nt_c01,
4111 }, {
4112 .compatible = "winstar,wf35ltiacd",
4113 .data = &winstar_wf35ltiacd,
4114 }, {
4115 /* Must be the last entry */
4116 .compatible = "panel-dpi",
4117 .data = &panel_dpi,
4118 }, {
4119 /* sentinel */
4120 }
4121};
4122MODULE_DEVICE_TABLE(of, platform_of_match);
4123
4124static int panel_simple_platform_probe(struct platform_device *pdev)
4125{
4126 const struct of_device_id *id;
4127
4128 id = of_match_node(platform_of_match, pdev->dev.of_node);
4129 if (!id)
4130 return -ENODEV;
4131
4132 return panel_simple_probe(&pdev->dev, id->data);
4133}
4134
4135static int panel_simple_platform_remove(struct platform_device *pdev)
4136{
4137 return panel_simple_remove(&pdev->dev);
4138}
4139
4140static void panel_simple_platform_shutdown(struct platform_device *pdev)
4141{
4142 panel_simple_shutdown(&pdev->dev);
4143}
4144
4145static struct platform_driver panel_simple_platform_driver = {
4146 .driver = {
4147 .name = "panel-simple",
4148 .of_match_table = platform_of_match,
4149 },
4150 .probe = panel_simple_platform_probe,
4151 .remove = panel_simple_platform_remove,
4152 .shutdown = panel_simple_platform_shutdown,
4153};
4154
4155struct panel_desc_dsi {
4156 struct panel_desc desc;
4157
4158 unsigned long flags;
4159 enum mipi_dsi_pixel_format format;
4160 unsigned int lanes;
4161};
4162
4163static const struct drm_display_mode auo_b080uan01_mode = {
4164 .clock = 154500,
4165 .hdisplay = 1200,
4166 .hsync_start = 1200 + 62,
4167 .hsync_end = 1200 + 62 + 4,
4168 .htotal = 1200 + 62 + 4 + 62,
4169 .vdisplay = 1920,
4170 .vsync_start = 1920 + 9,
4171 .vsync_end = 1920 + 9 + 2,
4172 .vtotal = 1920 + 9 + 2 + 8,
4173};
4174
4175static const struct panel_desc_dsi auo_b080uan01 = {
4176 .desc = {
4177 .modes = &auo_b080uan01_mode,
4178 .num_modes = 1,
4179 .bpc = 8,
4180 .size = {
4181 .width = 108,
4182 .height = 272,
4183 },
4184 .connector_type = DRM_MODE_CONNECTOR_DSI,
4185 },
4186 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_CLOCK_NON_CONTINUOUS,
4187 .format = MIPI_DSI_FMT_RGB888,
4188 .lanes = 4,
4189};
4190
4191static const struct drm_display_mode boe_tv080wum_nl0_mode = {
4192 .clock = 160000,
4193 .hdisplay = 1200,
4194 .hsync_start = 1200 + 120,
4195 .hsync_end = 1200 + 120 + 20,
4196 .htotal = 1200 + 120 + 20 + 21,
4197 .vdisplay = 1920,
4198 .vsync_start = 1920 + 21,
4199 .vsync_end = 1920 + 21 + 3,
4200 .vtotal = 1920 + 21 + 3 + 18,
4201 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
4202};
4203
4204static const struct panel_desc_dsi boe_tv080wum_nl0 = {
4205 .desc = {
4206 .modes = &boe_tv080wum_nl0_mode,
4207 .num_modes = 1,
4208 .size = {
4209 .width = 107,
4210 .height = 172,
4211 },
4212 .connector_type = DRM_MODE_CONNECTOR_DSI,
4213 },
4214 .flags = MIPI_DSI_MODE_VIDEO |
4215 MIPI_DSI_MODE_VIDEO_BURST |
4216 MIPI_DSI_MODE_VIDEO_SYNC_PULSE,
4217 .format = MIPI_DSI_FMT_RGB888,
4218 .lanes = 4,
4219};
4220
4221static const struct drm_display_mode lg_ld070wx3_sl01_mode = {
4222 .clock = 71000,
4223 .hdisplay = 800,
4224 .hsync_start = 800 + 32,
4225 .hsync_end = 800 + 32 + 1,
4226 .htotal = 800 + 32 + 1 + 57,
4227 .vdisplay = 1280,
4228 .vsync_start = 1280 + 28,
4229 .vsync_end = 1280 + 28 + 1,
4230 .vtotal = 1280 + 28 + 1 + 14,
4231};
4232
4233static const struct panel_desc_dsi lg_ld070wx3_sl01 = {
4234 .desc = {
4235 .modes = &lg_ld070wx3_sl01_mode,
4236 .num_modes = 1,
4237 .bpc = 8,
4238 .size = {
4239 .width = 94,
4240 .height = 151,
4241 },
4242 .connector_type = DRM_MODE_CONNECTOR_DSI,
4243 },
4244 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_CLOCK_NON_CONTINUOUS,
4245 .format = MIPI_DSI_FMT_RGB888,
4246 .lanes = 4,
4247};
4248
4249static const struct drm_display_mode lg_lh500wx1_sd03_mode = {
4250 .clock = 67000,
4251 .hdisplay = 720,
4252 .hsync_start = 720 + 12,
4253 .hsync_end = 720 + 12 + 4,
4254 .htotal = 720 + 12 + 4 + 112,
4255 .vdisplay = 1280,
4256 .vsync_start = 1280 + 8,
4257 .vsync_end = 1280 + 8 + 4,
4258 .vtotal = 1280 + 8 + 4 + 12,
4259};
4260
4261static const struct panel_desc_dsi lg_lh500wx1_sd03 = {
4262 .desc = {
4263 .modes = &lg_lh500wx1_sd03_mode,
4264 .num_modes = 1,
4265 .bpc = 8,
4266 .size = {
4267 .width = 62,
4268 .height = 110,
4269 },
4270 .connector_type = DRM_MODE_CONNECTOR_DSI,
4271 },
4272 .flags = MIPI_DSI_MODE_VIDEO,
4273 .format = MIPI_DSI_FMT_RGB888,
4274 .lanes = 4,
4275};
4276
4277static const struct drm_display_mode panasonic_vvx10f004b00_mode = {
4278 .clock = 157200,
4279 .hdisplay = 1920,
4280 .hsync_start = 1920 + 154,
4281 .hsync_end = 1920 + 154 + 16,
4282 .htotal = 1920 + 154 + 16 + 32,
4283 .vdisplay = 1200,
4284 .vsync_start = 1200 + 17,
4285 .vsync_end = 1200 + 17 + 2,
4286 .vtotal = 1200 + 17 + 2 + 16,
4287};
4288
4289static const struct panel_desc_dsi panasonic_vvx10f004b00 = {
4290 .desc = {
4291 .modes = &panasonic_vvx10f004b00_mode,
4292 .num_modes = 1,
4293 .bpc = 8,
4294 .size = {
4295 .width = 217,
4296 .height = 136,
4297 },
4298 .connector_type = DRM_MODE_CONNECTOR_DSI,
4299 },
4300 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_SYNC_PULSE |
4301 MIPI_DSI_CLOCK_NON_CONTINUOUS,
4302 .format = MIPI_DSI_FMT_RGB888,
4303 .lanes = 4,
4304};
4305
4306static const struct drm_display_mode lg_acx467akm_7_mode = {
4307 .clock = 150000,
4308 .hdisplay = 1080,
4309 .hsync_start = 1080 + 2,
4310 .hsync_end = 1080 + 2 + 2,
4311 .htotal = 1080 + 2 + 2 + 2,
4312 .vdisplay = 1920,
4313 .vsync_start = 1920 + 2,
4314 .vsync_end = 1920 + 2 + 2,
4315 .vtotal = 1920 + 2 + 2 + 2,
4316};
4317
4318static const struct panel_desc_dsi lg_acx467akm_7 = {
4319 .desc = {
4320 .modes = &lg_acx467akm_7_mode,
4321 .num_modes = 1,
4322 .bpc = 8,
4323 .size = {
4324 .width = 62,
4325 .height = 110,
4326 },
4327 .connector_type = DRM_MODE_CONNECTOR_DSI,
4328 },
4329 .flags = 0,
4330 .format = MIPI_DSI_FMT_RGB888,
4331 .lanes = 4,
4332};
4333
4334static const struct drm_display_mode osd101t2045_53ts_mode = {
4335 .clock = 154500,
4336 .hdisplay = 1920,
4337 .hsync_start = 1920 + 112,
4338 .hsync_end = 1920 + 112 + 16,
4339 .htotal = 1920 + 112 + 16 + 32,
4340 .vdisplay = 1200,
4341 .vsync_start = 1200 + 16,
4342 .vsync_end = 1200 + 16 + 2,
4343 .vtotal = 1200 + 16 + 2 + 16,
4344 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
4345};
4346
4347static const struct panel_desc_dsi osd101t2045_53ts = {
4348 .desc = {
4349 .modes = &osd101t2045_53ts_mode,
4350 .num_modes = 1,
4351 .bpc = 8,
4352 .size = {
4353 .width = 217,
4354 .height = 136,
4355 },
4356 .connector_type = DRM_MODE_CONNECTOR_DSI,
4357 },
4358 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST |
4359 MIPI_DSI_MODE_VIDEO_SYNC_PULSE |
4360 MIPI_DSI_MODE_EOT_PACKET,
4361 .format = MIPI_DSI_FMT_RGB888,
4362 .lanes = 4,
4363};
4364
4365static const struct of_device_id dsi_of_match[] = {
4366 {
4367 .compatible = "auo,b080uan01",
4368 .data = &auo_b080uan01
4369 }, {
4370 .compatible = "boe,tv080wum-nl0",
4371 .data = &boe_tv080wum_nl0
4372 }, {
4373 .compatible = "lg,ld070wx3-sl01",
4374 .data = &lg_ld070wx3_sl01
4375 }, {
4376 .compatible = "lg,lh500wx1-sd03",
4377 .data = &lg_lh500wx1_sd03
4378 }, {
4379 .compatible = "panasonic,vvx10f004b00",
4380 .data = &panasonic_vvx10f004b00
4381 }, {
4382 .compatible = "lg,acx467akm-7",
4383 .data = &lg_acx467akm_7
4384 }, {
4385 .compatible = "osddisplays,osd101t2045-53ts",
4386 .data = &osd101t2045_53ts
4387 }, {
4388 /* sentinel */
4389 }
4390};
4391MODULE_DEVICE_TABLE(of, dsi_of_match);
4392
4393static int panel_simple_dsi_probe(struct mipi_dsi_device *dsi)
4394{
4395 const struct panel_desc_dsi *desc;
4396 const struct of_device_id *id;
4397 int err;
4398
4399 id = of_match_node(dsi_of_match, dsi->dev.of_node);
4400 if (!id)
4401 return -ENODEV;
4402
4403 desc = id->data;
4404
4405 err = panel_simple_probe(&dsi->dev, &desc->desc);
4406 if (err < 0)
4407 return err;
4408
4409 dsi->mode_flags = desc->flags;
4410 dsi->format = desc->format;
4411 dsi->lanes = desc->lanes;
4412
4413 err = mipi_dsi_attach(dsi);
4414 if (err) {
4415 struct panel_simple *panel = dev_get_drvdata(&dsi->dev);
4416
4417 drm_panel_remove(&panel->base);
4418 }
4419
4420 return err;
4421}
4422
4423static int panel_simple_dsi_remove(struct mipi_dsi_device *dsi)
4424{
4425 int err;
4426
4427 err = mipi_dsi_detach(dsi);
4428 if (err < 0)
4429 dev_err(&dsi->dev, "failed to detach from DSI host: %d\n", err);
4430
4431 return panel_simple_remove(&dsi->dev);
4432}
4433
4434static void panel_simple_dsi_shutdown(struct mipi_dsi_device *dsi)
4435{
4436 panel_simple_shutdown(&dsi->dev);
4437}
4438
4439static struct mipi_dsi_driver panel_simple_dsi_driver = {
4440 .driver = {
4441 .name = "panel-simple-dsi",
4442 .of_match_table = dsi_of_match,
4443 },
4444 .probe = panel_simple_dsi_probe,
4445 .remove = panel_simple_dsi_remove,
4446 .shutdown = panel_simple_dsi_shutdown,
4447};
4448
4449static int __init panel_simple_init(void)
4450{
4451 int err;
4452
4453 err = platform_driver_register(&panel_simple_platform_driver);
4454 if (err < 0)
4455 return err;
4456
4457 if (IS_ENABLED(CONFIG_DRM_MIPI_DSI)) {
4458 err = mipi_dsi_driver_register(&panel_simple_dsi_driver);
4459 if (err < 0)
4460 return err;
4461 }
4462
4463 return 0;
4464}
4465module_init(panel_simple_init);
4466
4467static void __exit panel_simple_exit(void)
4468{
4469 if (IS_ENABLED(CONFIG_DRM_MIPI_DSI))
4470 mipi_dsi_driver_unregister(&panel_simple_dsi_driver);
4471
4472 platform_driver_unregister(&panel_simple_platform_driver);
4473}
4474module_exit(panel_simple_exit);
4475
4476MODULE_AUTHOR("Thierry Reding <treding@nvidia.com>");
4477MODULE_DESCRIPTION("DRM Driver for Simple Panels");
4478MODULE_LICENSE("GPL and additional rights");