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1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
4 * Author: Rob Clark <rob@ti.com>
5 */
6
7#include <linux/dma-mapping.h>
8#include <linux/platform_device.h>
9#include <linux/sort.h>
10#include <linux/sys_soc.h>
11
12#include <drm/drm_atomic.h>
13#include <drm/drm_atomic_helper.h>
14#include <drm/drm_bridge.h>
15#include <drm/drm_bridge_connector.h>
16#include <drm/drm_drv.h>
17#include <drm/drm_fb_helper.h>
18#include <drm/drm_file.h>
19#include <drm/drm_ioctl.h>
20#include <drm/drm_panel.h>
21#include <drm/drm_prime.h>
22#include <drm/drm_probe_helper.h>
23#include <drm/drm_vblank.h>
24
25#include "omap_dmm_tiler.h"
26#include "omap_drv.h"
27
28#define DRIVER_NAME MODULE_NAME
29#define DRIVER_DESC "OMAP DRM"
30#define DRIVER_DATE "20110917"
31#define DRIVER_MAJOR 1
32#define DRIVER_MINOR 0
33#define DRIVER_PATCHLEVEL 0
34
35/*
36 * mode config funcs
37 */
38
39/* Notes about mapping DSS and DRM entities:
40 * CRTC: overlay
41 * encoder: manager.. with some extension to allow one primary CRTC
42 * and zero or more video CRTC's to be mapped to one encoder?
43 * connector: dssdev.. manager can be attached/detached from different
44 * devices
45 */
46
47static void omap_atomic_wait_for_completion(struct drm_device *dev,
48 struct drm_atomic_state *old_state)
49{
50 struct drm_crtc_state *new_crtc_state;
51 struct drm_crtc *crtc;
52 unsigned int i;
53 int ret;
54
55 for_each_new_crtc_in_state(old_state, crtc, new_crtc_state, i) {
56 if (!new_crtc_state->active)
57 continue;
58
59 ret = omap_crtc_wait_pending(crtc);
60
61 if (!ret)
62 dev_warn(dev->dev,
63 "atomic complete timeout (pipe %u)!\n", i);
64 }
65}
66
67static void omap_atomic_commit_tail(struct drm_atomic_state *old_state)
68{
69 struct drm_device *dev = old_state->dev;
70 struct omap_drm_private *priv = dev->dev_private;
71
72 priv->dispc_ops->runtime_get(priv->dispc);
73
74 /* Apply the atomic update. */
75 drm_atomic_helper_commit_modeset_disables(dev, old_state);
76
77 if (priv->omaprev != 0x3430) {
78 /* With the current dss dispc implementation we have to enable
79 * the new modeset before we can commit planes. The dispc ovl
80 * configuration relies on the video mode configuration been
81 * written into the HW when the ovl configuration is
82 * calculated.
83 *
84 * This approach is not ideal because after a mode change the
85 * plane update is executed only after the first vblank
86 * interrupt. The dispc implementation should be fixed so that
87 * it is able use uncommitted drm state information.
88 */
89 drm_atomic_helper_commit_modeset_enables(dev, old_state);
90 omap_atomic_wait_for_completion(dev, old_state);
91
92 drm_atomic_helper_commit_planes(dev, old_state, 0);
93
94 drm_atomic_helper_commit_hw_done(old_state);
95 } else {
96 /*
97 * OMAP3 DSS seems to have issues with the work-around above,
98 * resulting in endless sync losts if a crtc is enabled without
99 * a plane. For now, skip the WA for OMAP3.
100 */
101 drm_atomic_helper_commit_planes(dev, old_state, 0);
102
103 drm_atomic_helper_commit_modeset_enables(dev, old_state);
104
105 drm_atomic_helper_commit_hw_done(old_state);
106 }
107
108 /*
109 * Wait for completion of the page flips to ensure that old buffers
110 * can't be touched by the hardware anymore before cleaning up planes.
111 */
112 omap_atomic_wait_for_completion(dev, old_state);
113
114 drm_atomic_helper_cleanup_planes(dev, old_state);
115
116 priv->dispc_ops->runtime_put(priv->dispc);
117}
118
119static const struct drm_mode_config_helper_funcs omap_mode_config_helper_funcs = {
120 .atomic_commit_tail = omap_atomic_commit_tail,
121};
122
123static const struct drm_mode_config_funcs omap_mode_config_funcs = {
124 .fb_create = omap_framebuffer_create,
125 .output_poll_changed = drm_fb_helper_output_poll_changed,
126 .atomic_check = drm_atomic_helper_check,
127 .atomic_commit = drm_atomic_helper_commit,
128};
129
130static void omap_disconnect_pipelines(struct drm_device *ddev)
131{
132 struct omap_drm_private *priv = ddev->dev_private;
133 unsigned int i;
134
135 for (i = 0; i < priv->num_pipes; i++) {
136 struct omap_drm_pipeline *pipe = &priv->pipes[i];
137
138 omapdss_device_disconnect(NULL, pipe->output);
139
140 omapdss_device_put(pipe->output);
141 pipe->output = NULL;
142 }
143
144 memset(&priv->channels, 0, sizeof(priv->channels));
145
146 priv->num_pipes = 0;
147}
148
149static int omap_connect_pipelines(struct drm_device *ddev)
150{
151 struct omap_drm_private *priv = ddev->dev_private;
152 struct omap_dss_device *output = NULL;
153 int r;
154
155 for_each_dss_output(output) {
156 r = omapdss_device_connect(priv->dss, NULL, output);
157 if (r == -EPROBE_DEFER) {
158 omapdss_device_put(output);
159 return r;
160 } else if (r) {
161 dev_warn(output->dev, "could not connect output %s\n",
162 output->name);
163 } else {
164 struct omap_drm_pipeline *pipe;
165
166 pipe = &priv->pipes[priv->num_pipes++];
167 pipe->output = omapdss_device_get(output);
168
169 if (priv->num_pipes == ARRAY_SIZE(priv->pipes)) {
170 /* To balance the 'for_each_dss_output' loop */
171 omapdss_device_put(output);
172 break;
173 }
174 }
175 }
176
177 return 0;
178}
179
180static int omap_compare_pipelines(const void *a, const void *b)
181{
182 const struct omap_drm_pipeline *pipe1 = a;
183 const struct omap_drm_pipeline *pipe2 = b;
184
185 if (pipe1->alias_id > pipe2->alias_id)
186 return 1;
187 else if (pipe1->alias_id < pipe2->alias_id)
188 return -1;
189 return 0;
190}
191
192static int omap_modeset_init_properties(struct drm_device *dev)
193{
194 struct omap_drm_private *priv = dev->dev_private;
195 unsigned int num_planes = priv->dispc_ops->get_num_ovls(priv->dispc);
196
197 priv->zorder_prop = drm_property_create_range(dev, 0, "zorder", 0,
198 num_planes - 1);
199 if (!priv->zorder_prop)
200 return -ENOMEM;
201
202 return 0;
203}
204
205static int omap_display_id(struct omap_dss_device *output)
206{
207 struct device_node *node = NULL;
208
209 if (output->next) {
210 struct omap_dss_device *display = output;
211
212 while (display->next)
213 display = display->next;
214
215 node = display->dev->of_node;
216 } else if (output->bridge) {
217 struct drm_bridge *bridge = output->bridge;
218
219 while (drm_bridge_get_next_bridge(bridge))
220 bridge = drm_bridge_get_next_bridge(bridge);
221
222 node = bridge->of_node;
223 }
224
225 return node ? of_alias_get_id(node, "display") : -ENODEV;
226}
227
228static int omap_modeset_init(struct drm_device *dev)
229{
230 struct omap_drm_private *priv = dev->dev_private;
231 int num_ovls = priv->dispc_ops->get_num_ovls(priv->dispc);
232 int num_mgrs = priv->dispc_ops->get_num_mgrs(priv->dispc);
233 unsigned int i;
234 int ret;
235 u32 plane_crtc_mask;
236
237 if (!omapdss_stack_is_ready())
238 return -EPROBE_DEFER;
239
240 drm_mode_config_init(dev);
241
242 ret = omap_modeset_init_properties(dev);
243 if (ret < 0)
244 return ret;
245
246 /*
247 * This function creates exactly one connector, encoder, crtc,
248 * and primary plane per each connected dss-device. Each
249 * connector->encoder->crtc chain is expected to be separate
250 * and each crtc is connect to a single dss-channel. If the
251 * configuration does not match the expectations or exceeds
252 * the available resources, the configuration is rejected.
253 */
254 ret = omap_connect_pipelines(dev);
255 if (ret < 0)
256 return ret;
257
258 if (priv->num_pipes > num_mgrs || priv->num_pipes > num_ovls) {
259 dev_err(dev->dev, "%s(): Too many connected displays\n",
260 __func__);
261 return -EINVAL;
262 }
263
264 /* Create all planes first. They can all be put to any CRTC. */
265 plane_crtc_mask = (1 << priv->num_pipes) - 1;
266
267 for (i = 0; i < num_ovls; i++) {
268 enum drm_plane_type type = i < priv->num_pipes
269 ? DRM_PLANE_TYPE_PRIMARY
270 : DRM_PLANE_TYPE_OVERLAY;
271 struct drm_plane *plane;
272
273 if (WARN_ON(priv->num_planes >= ARRAY_SIZE(priv->planes)))
274 return -EINVAL;
275
276 plane = omap_plane_init(dev, i, type, plane_crtc_mask);
277 if (IS_ERR(plane))
278 return PTR_ERR(plane);
279
280 priv->planes[priv->num_planes++] = plane;
281 }
282
283 /*
284 * Create the encoders, attach the bridges and get the pipeline alias
285 * IDs.
286 */
287 for (i = 0; i < priv->num_pipes; i++) {
288 struct omap_drm_pipeline *pipe = &priv->pipes[i];
289 int id;
290
291 pipe->encoder = omap_encoder_init(dev, pipe->output);
292 if (!pipe->encoder)
293 return -ENOMEM;
294
295 if (pipe->output->bridge) {
296 ret = drm_bridge_attach(pipe->encoder,
297 pipe->output->bridge, NULL,
298 DRM_BRIDGE_ATTACH_NO_CONNECTOR);
299 if (ret < 0) {
300 dev_err(priv->dev,
301 "unable to attach bridge %pOF\n",
302 pipe->output->bridge->of_node);
303 return ret;
304 }
305 }
306
307 id = omap_display_id(pipe->output);
308 pipe->alias_id = id >= 0 ? id : i;
309 }
310
311 /* Sort the pipelines by DT aliases. */
312 sort(priv->pipes, priv->num_pipes, sizeof(priv->pipes[0]),
313 omap_compare_pipelines, NULL);
314
315 /*
316 * Populate the pipeline lookup table by DISPC channel. Only one display
317 * is allowed per channel.
318 */
319 for (i = 0; i < priv->num_pipes; ++i) {
320 struct omap_drm_pipeline *pipe = &priv->pipes[i];
321 enum omap_channel channel = pipe->output->dispc_channel;
322
323 if (WARN_ON(priv->channels[channel] != NULL))
324 return -EINVAL;
325
326 priv->channels[channel] = pipe;
327 }
328
329 /* Create the connectors and CRTCs. */
330 for (i = 0; i < priv->num_pipes; i++) {
331 struct omap_drm_pipeline *pipe = &priv->pipes[i];
332 struct drm_encoder *encoder = pipe->encoder;
333 struct drm_crtc *crtc;
334
335 if (pipe->output->next) {
336 pipe->connector = omap_connector_init(dev, pipe->output,
337 encoder);
338 if (!pipe->connector)
339 return -ENOMEM;
340 } else {
341 pipe->connector = drm_bridge_connector_init(dev, encoder);
342 if (IS_ERR(pipe->connector)) {
343 dev_err(priv->dev,
344 "unable to create bridge connector for %s\n",
345 pipe->output->name);
346 return PTR_ERR(pipe->connector);
347 }
348 }
349
350 drm_connector_attach_encoder(pipe->connector, encoder);
351
352 if (pipe->output->panel) {
353 ret = drm_panel_attach(pipe->output->panel,
354 pipe->connector);
355 if (ret < 0)
356 return ret;
357 }
358
359 crtc = omap_crtc_init(dev, pipe, priv->planes[i]);
360 if (IS_ERR(crtc))
361 return PTR_ERR(crtc);
362
363 encoder->possible_crtcs = 1 << i;
364 pipe->crtc = crtc;
365 }
366
367 DBG("registered %u planes, %u crtcs/encoders/connectors\n",
368 priv->num_planes, priv->num_pipes);
369
370 dev->mode_config.min_width = 8;
371 dev->mode_config.min_height = 2;
372
373 /*
374 * Note: these values are used for multiple independent things:
375 * connector mode filtering, buffer sizes, crtc sizes...
376 * Use big enough values here to cover all use cases, and do more
377 * specific checking in the respective code paths.
378 */
379 dev->mode_config.max_width = 8192;
380 dev->mode_config.max_height = 8192;
381
382 /* We want the zpos to be normalized */
383 dev->mode_config.normalize_zpos = true;
384
385 dev->mode_config.funcs = &omap_mode_config_funcs;
386 dev->mode_config.helper_private = &omap_mode_config_helper_funcs;
387
388 drm_mode_config_reset(dev);
389
390 omap_drm_irq_install(dev);
391
392 return 0;
393}
394
395static void omap_modeset_fini(struct drm_device *ddev)
396{
397 struct omap_drm_private *priv = ddev->dev_private;
398 unsigned int i;
399
400 omap_drm_irq_uninstall(ddev);
401
402 for (i = 0; i < priv->num_pipes; i++) {
403 struct omap_drm_pipeline *pipe = &priv->pipes[i];
404
405 if (pipe->output->panel)
406 drm_panel_detach(pipe->output->panel);
407 }
408
409 drm_mode_config_cleanup(ddev);
410}
411
412/*
413 * Enable the HPD in external components if supported
414 */
415static void omap_modeset_enable_external_hpd(struct drm_device *ddev)
416{
417 struct omap_drm_private *priv = ddev->dev_private;
418 unsigned int i;
419
420 for (i = 0; i < priv->num_pipes; i++) {
421 struct drm_connector *connector = priv->pipes[i].connector;
422
423 if (!connector)
424 continue;
425
426 if (priv->pipes[i].output->bridge)
427 drm_bridge_connector_enable_hpd(connector);
428 }
429}
430
431/*
432 * Disable the HPD in external components if supported
433 */
434static void omap_modeset_disable_external_hpd(struct drm_device *ddev)
435{
436 struct omap_drm_private *priv = ddev->dev_private;
437 unsigned int i;
438
439 for (i = 0; i < priv->num_pipes; i++) {
440 struct drm_connector *connector = priv->pipes[i].connector;
441
442 if (!connector)
443 continue;
444
445 if (priv->pipes[i].output->bridge)
446 drm_bridge_connector_disable_hpd(connector);
447 }
448}
449
450/*
451 * drm ioctl funcs
452 */
453
454
455static int ioctl_get_param(struct drm_device *dev, void *data,
456 struct drm_file *file_priv)
457{
458 struct omap_drm_private *priv = dev->dev_private;
459 struct drm_omap_param *args = data;
460
461 DBG("%p: param=%llu", dev, args->param);
462
463 switch (args->param) {
464 case OMAP_PARAM_CHIPSET_ID:
465 args->value = priv->omaprev;
466 break;
467 default:
468 DBG("unknown parameter %lld", args->param);
469 return -EINVAL;
470 }
471
472 return 0;
473}
474
475#define OMAP_BO_USER_MASK 0x00ffffff /* flags settable by userspace */
476
477static int ioctl_gem_new(struct drm_device *dev, void *data,
478 struct drm_file *file_priv)
479{
480 struct drm_omap_gem_new *args = data;
481 u32 flags = args->flags & OMAP_BO_USER_MASK;
482
483 VERB("%p:%p: size=0x%08x, flags=%08x", dev, file_priv,
484 args->size.bytes, flags);
485
486 return omap_gem_new_handle(dev, file_priv, args->size, flags,
487 &args->handle);
488}
489
490static int ioctl_gem_info(struct drm_device *dev, void *data,
491 struct drm_file *file_priv)
492{
493 struct drm_omap_gem_info *args = data;
494 struct drm_gem_object *obj;
495 int ret = 0;
496
497 VERB("%p:%p: handle=%d", dev, file_priv, args->handle);
498
499 obj = drm_gem_object_lookup(file_priv, args->handle);
500 if (!obj)
501 return -ENOENT;
502
503 args->size = omap_gem_mmap_size(obj);
504 args->offset = omap_gem_mmap_offset(obj);
505
506 drm_gem_object_put(obj);
507
508 return ret;
509}
510
511static const struct drm_ioctl_desc ioctls[DRM_COMMAND_END - DRM_COMMAND_BASE] = {
512 DRM_IOCTL_DEF_DRV(OMAP_GET_PARAM, ioctl_get_param,
513 DRM_RENDER_ALLOW),
514 DRM_IOCTL_DEF_DRV(OMAP_SET_PARAM, drm_invalid_op,
515 DRM_AUTH | DRM_MASTER | DRM_ROOT_ONLY),
516 DRM_IOCTL_DEF_DRV(OMAP_GEM_NEW, ioctl_gem_new,
517 DRM_RENDER_ALLOW),
518 /* Deprecated, to be removed. */
519 DRM_IOCTL_DEF_DRV(OMAP_GEM_CPU_PREP, drm_noop,
520 DRM_RENDER_ALLOW),
521 /* Deprecated, to be removed. */
522 DRM_IOCTL_DEF_DRV(OMAP_GEM_CPU_FINI, drm_noop,
523 DRM_RENDER_ALLOW),
524 DRM_IOCTL_DEF_DRV(OMAP_GEM_INFO, ioctl_gem_info,
525 DRM_RENDER_ALLOW),
526};
527
528/*
529 * drm driver funcs
530 */
531
532static int dev_open(struct drm_device *dev, struct drm_file *file)
533{
534 file->driver_priv = NULL;
535
536 DBG("open: dev=%p, file=%p", dev, file);
537
538 return 0;
539}
540
541static const struct vm_operations_struct omap_gem_vm_ops = {
542 .fault = omap_gem_fault,
543 .open = drm_gem_vm_open,
544 .close = drm_gem_vm_close,
545};
546
547static const struct file_operations omapdriver_fops = {
548 .owner = THIS_MODULE,
549 .open = drm_open,
550 .unlocked_ioctl = drm_ioctl,
551 .compat_ioctl = drm_compat_ioctl,
552 .release = drm_release,
553 .mmap = omap_gem_mmap,
554 .poll = drm_poll,
555 .read = drm_read,
556 .llseek = noop_llseek,
557};
558
559static struct drm_driver omap_drm_driver = {
560 .driver_features = DRIVER_MODESET | DRIVER_GEM |
561 DRIVER_ATOMIC | DRIVER_RENDER,
562 .open = dev_open,
563 .lastclose = drm_fb_helper_lastclose,
564#ifdef CONFIG_DEBUG_FS
565 .debugfs_init = omap_debugfs_init,
566#endif
567 .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
568 .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
569 .gem_prime_export = omap_gem_prime_export,
570 .gem_prime_import = omap_gem_prime_import,
571 .gem_free_object_unlocked = omap_gem_free_object,
572 .gem_vm_ops = &omap_gem_vm_ops,
573 .dumb_create = omap_gem_dumb_create,
574 .dumb_map_offset = omap_gem_dumb_map_offset,
575 .ioctls = ioctls,
576 .num_ioctls = DRM_OMAP_NUM_IOCTLS,
577 .fops = &omapdriver_fops,
578 .name = DRIVER_NAME,
579 .desc = DRIVER_DESC,
580 .date = DRIVER_DATE,
581 .major = DRIVER_MAJOR,
582 .minor = DRIVER_MINOR,
583 .patchlevel = DRIVER_PATCHLEVEL,
584};
585
586static const struct soc_device_attribute omapdrm_soc_devices[] = {
587 { .family = "OMAP3", .data = (void *)0x3430 },
588 { .family = "OMAP4", .data = (void *)0x4430 },
589 { .family = "OMAP5", .data = (void *)0x5430 },
590 { .family = "DRA7", .data = (void *)0x0752 },
591 { /* sentinel */ }
592};
593
594static int omapdrm_init(struct omap_drm_private *priv, struct device *dev)
595{
596 const struct soc_device_attribute *soc;
597 struct drm_device *ddev;
598 int ret;
599
600 DBG("%s", dev_name(dev));
601
602 /* Allocate and initialize the DRM device. */
603 ddev = drm_dev_alloc(&omap_drm_driver, dev);
604 if (IS_ERR(ddev))
605 return PTR_ERR(ddev);
606
607 priv->ddev = ddev;
608 ddev->dev_private = priv;
609
610 priv->dev = dev;
611 priv->dss = omapdss_get_dss();
612 priv->dispc = dispc_get_dispc(priv->dss);
613 priv->dispc_ops = dispc_get_ops(priv->dss);
614
615 omap_crtc_pre_init(priv);
616
617 soc = soc_device_match(omapdrm_soc_devices);
618 priv->omaprev = soc ? (unsigned int)soc->data : 0;
619 priv->wq = alloc_ordered_workqueue("omapdrm", 0);
620
621 mutex_init(&priv->list_lock);
622 INIT_LIST_HEAD(&priv->obj_list);
623
624 /* Get memory bandwidth limits */
625 if (priv->dispc_ops->get_memory_bandwidth_limit)
626 priv->max_bandwidth =
627 priv->dispc_ops->get_memory_bandwidth_limit(priv->dispc);
628
629 omap_gem_init(ddev);
630
631 ret = omap_modeset_init(ddev);
632 if (ret) {
633 dev_err(priv->dev, "omap_modeset_init failed: ret=%d\n", ret);
634 goto err_gem_deinit;
635 }
636
637 /* Initialize vblank handling, start with all CRTCs disabled. */
638 ret = drm_vblank_init(ddev, priv->num_pipes);
639 if (ret) {
640 dev_err(priv->dev, "could not init vblank\n");
641 goto err_cleanup_modeset;
642 }
643
644 omap_fbdev_init(ddev);
645
646 drm_kms_helper_poll_init(ddev);
647 omap_modeset_enable_external_hpd(ddev);
648
649 /*
650 * Register the DRM device with the core and the connectors with
651 * sysfs.
652 */
653 ret = drm_dev_register(ddev, 0);
654 if (ret)
655 goto err_cleanup_helpers;
656
657 return 0;
658
659err_cleanup_helpers:
660 omap_modeset_disable_external_hpd(ddev);
661 drm_kms_helper_poll_fini(ddev);
662
663 omap_fbdev_fini(ddev);
664err_cleanup_modeset:
665 omap_modeset_fini(ddev);
666err_gem_deinit:
667 omap_gem_deinit(ddev);
668 destroy_workqueue(priv->wq);
669 omap_disconnect_pipelines(ddev);
670 omap_crtc_pre_uninit(priv);
671 drm_dev_put(ddev);
672 return ret;
673}
674
675static void omapdrm_cleanup(struct omap_drm_private *priv)
676{
677 struct drm_device *ddev = priv->ddev;
678
679 DBG("");
680
681 drm_dev_unregister(ddev);
682
683 omap_modeset_disable_external_hpd(ddev);
684 drm_kms_helper_poll_fini(ddev);
685
686 omap_fbdev_fini(ddev);
687
688 drm_atomic_helper_shutdown(ddev);
689
690 omap_modeset_fini(ddev);
691 omap_gem_deinit(ddev);
692
693 destroy_workqueue(priv->wq);
694
695 omap_disconnect_pipelines(ddev);
696 omap_crtc_pre_uninit(priv);
697
698 drm_dev_put(ddev);
699}
700
701static int pdev_probe(struct platform_device *pdev)
702{
703 struct omap_drm_private *priv;
704 int ret;
705
706 if (omapdss_is_initialized() == false)
707 return -EPROBE_DEFER;
708
709 ret = dma_coerce_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
710 if (ret) {
711 dev_err(&pdev->dev, "Failed to set the DMA mask\n");
712 return ret;
713 }
714
715 /* Allocate and initialize the driver private structure. */
716 priv = kzalloc(sizeof(*priv), GFP_KERNEL);
717 if (!priv)
718 return -ENOMEM;
719
720 platform_set_drvdata(pdev, priv);
721
722 ret = omapdrm_init(priv, &pdev->dev);
723 if (ret < 0)
724 kfree(priv);
725
726 return ret;
727}
728
729static int pdev_remove(struct platform_device *pdev)
730{
731 struct omap_drm_private *priv = platform_get_drvdata(pdev);
732
733 omapdrm_cleanup(priv);
734 kfree(priv);
735
736 return 0;
737}
738
739#ifdef CONFIG_PM_SLEEP
740static int omap_drm_suspend(struct device *dev)
741{
742 struct omap_drm_private *priv = dev_get_drvdata(dev);
743 struct drm_device *drm_dev = priv->ddev;
744
745 return drm_mode_config_helper_suspend(drm_dev);
746}
747
748static int omap_drm_resume(struct device *dev)
749{
750 struct omap_drm_private *priv = dev_get_drvdata(dev);
751 struct drm_device *drm_dev = priv->ddev;
752
753 drm_mode_config_helper_resume(drm_dev);
754
755 return omap_gem_resume(drm_dev);
756}
757#endif
758
759static SIMPLE_DEV_PM_OPS(omapdrm_pm_ops, omap_drm_suspend, omap_drm_resume);
760
761static struct platform_driver pdev = {
762 .driver = {
763 .name = "omapdrm",
764 .pm = &omapdrm_pm_ops,
765 },
766 .probe = pdev_probe,
767 .remove = pdev_remove,
768};
769
770static struct platform_driver * const drivers[] = {
771 &omap_dmm_driver,
772 &pdev,
773};
774
775static int __init omap_drm_init(void)
776{
777 DBG("init");
778
779 return platform_register_drivers(drivers, ARRAY_SIZE(drivers));
780}
781
782static void __exit omap_drm_fini(void)
783{
784 DBG("fini");
785
786 platform_unregister_drivers(drivers, ARRAY_SIZE(drivers));
787}
788
789/* need late_initcall() so we load after dss_driver's are loaded */
790late_initcall(omap_drm_init);
791module_exit(omap_drm_fini);
792
793MODULE_AUTHOR("Rob Clark <rob@ti.com>");
794MODULE_DESCRIPTION("OMAP DRM Display Driver");
795MODULE_ALIAS("platform:" DRIVER_NAME);
796MODULE_LICENSE("GPL v2");