1// SPDX-License-Identifier: GPL-2.0
  2
  3#include <linux/acpi.h>
  4#include <linux/bitfield.h>
  5#include <linux/bitops.h>
  6#include <linux/device.h>
  7#include <linux/gpio/driver.h>
  8#include <linux/io.h>
  9#include <linux/ioport.h>
 10#include <linux/kernel.h>
 11#include <linux/module.h>
 12#include <linux/platform_device.h>
 13#include <linux/pm.h>
 14#include <linux/resource.h>
 15#include <linux/spinlock.h>
 16#include <linux/types.h>
 17
 18/*
 19 * There are 3 YU GPIO blocks:
 20 * gpio[0]: HOST_GPIO0->HOST_GPIO31
 21 * gpio[1]: HOST_GPIO32->HOST_GPIO63
 22 * gpio[2]: HOST_GPIO64->HOST_GPIO69
 23 */
 24#define MLXBF2_GPIO_MAX_PINS_PER_BLOCK 32
 25
 26/*
 27 * arm_gpio_lock register:
 28 * bit[31]	lock status: active if set
 29 * bit[15:0]	set lock
 30 * The lock is enabled only if 0xd42f is written to this field
 31 */
 32#define YU_ARM_GPIO_LOCK_ADDR		0x2801088
 33#define YU_ARM_GPIO_LOCK_SIZE		0x8
 34#define YU_LOCK_ACTIVE_BIT(val)		(val >> 31)
 35#define YU_ARM_GPIO_LOCK_ACQUIRE	0xd42f
 36#define YU_ARM_GPIO_LOCK_RELEASE	0x0
 37
 38/*
 39 * gpio[x] block registers and their offset
 40 */
 41#define YU_GPIO_DATAIN			0x04
 42#define YU_GPIO_MODE1			0x08
 43#define YU_GPIO_MODE0			0x0c
 44#define YU_GPIO_DATASET			0x14
 45#define YU_GPIO_DATACLEAR		0x18
 46#define YU_GPIO_MODE1_CLEAR		0x50
 47#define YU_GPIO_MODE0_SET		0x54
 48#define YU_GPIO_MODE0_CLEAR		0x58
 49
 50#ifdef CONFIG_PM
 51struct mlxbf2_gpio_context_save_regs {
 52	u32 gpio_mode0;
 53	u32 gpio_mode1;
 54};
 55#endif
 56
 57/* BlueField-2 gpio block context structure. */
 58struct mlxbf2_gpio_context {
 59	struct gpio_chip gc;
 60
 61	/* YU GPIO blocks address */
 62	void __iomem *gpio_io;
 63
 64#ifdef CONFIG_PM
 65	struct mlxbf2_gpio_context_save_regs *csave_regs;
 66#endif
 67};
 68
 69/* BlueField-2 gpio shared structure. */
 70struct mlxbf2_gpio_param {
 71	void __iomem *io;
 72	struct resource *res;
 73	struct mutex *lock;
 74};
 75
 76static struct resource yu_arm_gpio_lock_res = {
 77	.start = YU_ARM_GPIO_LOCK_ADDR,
 78	.end   = YU_ARM_GPIO_LOCK_ADDR + YU_ARM_GPIO_LOCK_SIZE - 1,
 79	.name  = "YU_ARM_GPIO_LOCK",
 80};
 81
 82static DEFINE_MUTEX(yu_arm_gpio_lock_mutex);
 83
 84static struct mlxbf2_gpio_param yu_arm_gpio_lock_param = {
 85	.res = &yu_arm_gpio_lock_res,
 86	.lock = &yu_arm_gpio_lock_mutex,
 87};
 88
 89/* Request memory region and map yu_arm_gpio_lock resource */
 90static int mlxbf2_gpio_get_lock_res(struct platform_device *pdev)
 91{
 92	struct device *dev = &pdev->dev;
 93	struct resource *res;
 94	resource_size_t size;
 95	int ret = 0;
 96
 97	mutex_lock(yu_arm_gpio_lock_param.lock);
 98
 99	/* Check if the memory map already exists */
100	if (yu_arm_gpio_lock_param.io)
101		goto exit;
102
103	res = yu_arm_gpio_lock_param.res;
104	size = resource_size(res);
105
106	if (!devm_request_mem_region(dev, res->start, size, res->name)) {
107		ret = -EFAULT;
108		goto exit;
109	}
110
111	yu_arm_gpio_lock_param.io = devm_ioremap(dev, res->start, size);
112	if (!yu_arm_gpio_lock_param.io)
113		ret = -ENOMEM;
114
115exit:
116	mutex_unlock(yu_arm_gpio_lock_param.lock);
117
118	return ret;
119}
120
121/*
122 * Acquire the YU arm_gpio_lock to be able to change the direction
123 * mode. If the lock_active bit is already set, return an error.
124 */
125static int mlxbf2_gpio_lock_acquire(struct mlxbf2_gpio_context *gs)
126{
127	u32 arm_gpio_lock_val;
128
129	mutex_lock(yu_arm_gpio_lock_param.lock);
130	spin_lock(&gs->gc.bgpio_lock);
131
132	arm_gpio_lock_val = readl(yu_arm_gpio_lock_param.io);
133
134	/*
135	 * When lock active bit[31] is set, ModeX is write enabled
136	 */
137	if (YU_LOCK_ACTIVE_BIT(arm_gpio_lock_val)) {
138		spin_unlock(&gs->gc.bgpio_lock);
139		mutex_unlock(yu_arm_gpio_lock_param.lock);
140		return -EINVAL;
141	}
142
143	writel(YU_ARM_GPIO_LOCK_ACQUIRE, yu_arm_gpio_lock_param.io);
144
145	return 0;
146}
147
148/*
149 * Release the YU arm_gpio_lock after changing the direction mode.
150 */
151static void mlxbf2_gpio_lock_release(struct mlxbf2_gpio_context *gs)
152	__releases(&gs->gc.bgpio_lock)
153	__releases(yu_arm_gpio_lock_param.lock)
154{
155	writel(YU_ARM_GPIO_LOCK_RELEASE, yu_arm_gpio_lock_param.io);
156	spin_unlock(&gs->gc.bgpio_lock);
157	mutex_unlock(yu_arm_gpio_lock_param.lock);
158}
159
160/*
161 * mode0 and mode1 are both locked by the gpio_lock field.
162 *
163 * Together, mode0 and mode1 define the gpio Mode dependeing also
164 * on Reg_DataOut.
165 *
166 * {mode1,mode0}:{Reg_DataOut=0,Reg_DataOut=1}->{DataOut=0,DataOut=1}
167 *
168 * {0,0}:Reg_DataOut{0,1}->{Z,Z} Input PAD
169 * {0,1}:Reg_DataOut{0,1}->{0,1} Full drive Output PAD
170 * {1,0}:Reg_DataOut{0,1}->{0,Z} 0-set PAD to low, 1-float
171 * {1,1}:Reg_DataOut{0,1}->{Z,1} 0-float, 1-set PAD to high
172 */
173
174/*
175 * Set input direction:
176 * {mode1,mode0} = {0,0}
177 */
178static int mlxbf2_gpio_direction_input(struct gpio_chip *chip,
179				       unsigned int offset)
180{
181	struct mlxbf2_gpio_context *gs = gpiochip_get_data(chip);
182	int ret;
183
184	/*
185	 * Although the arm_gpio_lock was set in the probe function, check again
186	 * if it is still enabled to be able to write to the ModeX registers.
187	 */
188	ret = mlxbf2_gpio_lock_acquire(gs);
189	if (ret < 0)
190		return ret;
191
192	writel(BIT(offset), gs->gpio_io + YU_GPIO_MODE0_CLEAR);
193	writel(BIT(offset), gs->gpio_io + YU_GPIO_MODE1_CLEAR);
194
195	mlxbf2_gpio_lock_release(gs);
196
197	return ret;
198}
199
200/*
201 * Set output direction:
202 * {mode1,mode0} = {0,1}
203 */
204static int mlxbf2_gpio_direction_output(struct gpio_chip *chip,
205					unsigned int offset,
206					int value)
207{
208	struct mlxbf2_gpio_context *gs = gpiochip_get_data(chip);
209	int ret = 0;
210
211	/*
212	 * Although the arm_gpio_lock was set in the probe function,
213	 * check again it is still enabled to be able to write to the
214	 * ModeX registers.
215	 */
216	ret = mlxbf2_gpio_lock_acquire(gs);
217	if (ret < 0)
218		return ret;
219
220	writel(BIT(offset), gs->gpio_io + YU_GPIO_MODE1_CLEAR);
221	writel(BIT(offset), gs->gpio_io + YU_GPIO_MODE0_SET);
222
223	mlxbf2_gpio_lock_release(gs);
224
225	return ret;
226}
227
228/* BlueField-2 GPIO driver initialization routine. */
229static int
230mlxbf2_gpio_probe(struct platform_device *pdev)
231{
232	struct mlxbf2_gpio_context *gs;
233	struct device *dev = &pdev->dev;
234	struct gpio_chip *gc;
235	struct resource *res;
236	unsigned int npins;
237	int ret;
238
239	gs = devm_kzalloc(dev, sizeof(*gs), GFP_KERNEL);
240	if (!gs)
241		return -ENOMEM;
242
243	/* YU GPIO block address */
244	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
245	if (!res)
246		return -ENODEV;
247
248	gs->gpio_io = devm_ioremap(dev, res->start, resource_size(res));
249	if (!gs->gpio_io)
250		return -ENOMEM;
251
252	ret = mlxbf2_gpio_get_lock_res(pdev);
253	if (ret) {
254		dev_err(dev, "Failed to get yu_arm_gpio_lock resource\n");
255		return ret;
256	}
257
258	if (device_property_read_u32(dev, "npins", &npins))
259		npins = MLXBF2_GPIO_MAX_PINS_PER_BLOCK;
260
261	gc = &gs->gc;
262
263	ret = bgpio_init(gc, dev, 4,
264			gs->gpio_io + YU_GPIO_DATAIN,
265			gs->gpio_io + YU_GPIO_DATASET,
266			gs->gpio_io + YU_GPIO_DATACLEAR,
267			NULL,
268			NULL,
269			0);
270
271	gc->direction_input = mlxbf2_gpio_direction_input;
272	gc->direction_output = mlxbf2_gpio_direction_output;
273	gc->ngpio = npins;
274	gc->owner = THIS_MODULE;
275
276	platform_set_drvdata(pdev, gs);
277
278	ret = devm_gpiochip_add_data(dev, &gs->gc, gs);
279	if (ret) {
280		dev_err(dev, "Failed adding memory mapped gpiochip\n");
281		return ret;
282	}
283
284	return 0;
285}
286
287#ifdef CONFIG_PM
288static int mlxbf2_gpio_suspend(struct platform_device *pdev,
289				pm_message_t state)
290{
291	struct mlxbf2_gpio_context *gs = platform_get_drvdata(pdev);
292
293	gs->csave_regs->gpio_mode0 = readl(gs->gpio_io +
294		YU_GPIO_MODE0);
295	gs->csave_regs->gpio_mode1 = readl(gs->gpio_io +
296		YU_GPIO_MODE1);
297
298	return 0;
299}
300
301static int mlxbf2_gpio_resume(struct platform_device *pdev)
302{
303	struct mlxbf2_gpio_context *gs = platform_get_drvdata(pdev);
304
305	writel(gs->csave_regs->gpio_mode0, gs->gpio_io +
306		YU_GPIO_MODE0);
307	writel(gs->csave_regs->gpio_mode1, gs->gpio_io +
308		YU_GPIO_MODE1);
309
310	return 0;
311}
312#endif
313
314static const struct acpi_device_id __maybe_unused mlxbf2_gpio_acpi_match[] = {
315	{ "MLNXBF22", 0 },
316	{},
317};
318MODULE_DEVICE_TABLE(acpi, mlxbf2_gpio_acpi_match);
319
320static struct platform_driver mlxbf2_gpio_driver = {
321	.driver = {
322		.name = "mlxbf2_gpio",
323		.acpi_match_table = ACPI_PTR(mlxbf2_gpio_acpi_match),
324	},
325	.probe    = mlxbf2_gpio_probe,
326#ifdef CONFIG_PM
327	.suspend  = mlxbf2_gpio_suspend,
328	.resume   = mlxbf2_gpio_resume,
329#endif
330};
331
332module_platform_driver(mlxbf2_gpio_driver);
333
334MODULE_DESCRIPTION("Mellanox BlueField-2 GPIO Driver");
335MODULE_AUTHOR("Mellanox Technologies");
336MODULE_LICENSE("GPL v2");