1// SPDX-License-Identifier: GPL-2.0
  2#include <linux/clk-provider.h>
  3#include <linux/mfd/syscon.h>
  4#include <linux/slab.h>
  5
  6#include <dt-bindings/clock/at91.h>
  7
  8#include "pmc.h"
  9
 10struct sck {
 11	char *n;
 12	char *p;
 13	u8 id;
 14};
 15
 16struct pck {
 17	char *n;
 18	u8 id;
 19};
 20
 21static const struct clk_master_characteristics rm9200_mck_characteristics = {
 22	.output = { .min = 0, .max = 80000000 },
 23	.divisors = { 1, 2, 3, 4 },
 24};
 25
 26static u8 rm9200_pll_out[] = { 0, 2 };
 27
 28static const struct clk_range rm9200_pll_outputs[] = {
 29	{ .min = 80000000, .max = 160000000 },
 30	{ .min = 150000000, .max = 180000000 },
 31};
 32
 33static const struct clk_pll_characteristics rm9200_pll_characteristics = {
 34	.input = { .min = 1000000, .max = 32000000 },
 35	.num_output = ARRAY_SIZE(rm9200_pll_outputs),
 36	.output = rm9200_pll_outputs,
 37	.out = rm9200_pll_out,
 38};
 39
 40static const struct sck at91rm9200_systemck[] = {
 41	{ .n = "udpck", .p = "usbck",    .id = 2 },
 42	{ .n = "uhpck", .p = "usbck",    .id = 4 },
 43	{ .n = "pck0",  .p = "prog0",    .id = 8 },
 44	{ .n = "pck1",  .p = "prog1",    .id = 9 },
 45	{ .n = "pck2",  .p = "prog2",    .id = 10 },
 46	{ .n = "pck3",  .p = "prog3",    .id = 11 },
 47};
 48
 49static const struct pck at91rm9200_periphck[] = {
 50	{ .n = "pioA_clk",   .id = 2 },
 51	{ .n = "pioB_clk",   .id = 3 },
 52	{ .n = "pioC_clk",   .id = 4 },
 53	{ .n = "pioD_clk",   .id = 5 },
 54	{ .n = "usart0_clk", .id = 6 },
 55	{ .n = "usart1_clk", .id = 7 },
 56	{ .n = "usart2_clk", .id = 8 },
 57	{ .n = "usart3_clk", .id = 9 },
 58	{ .n = "mci0_clk",   .id = 10 },
 59	{ .n = "udc_clk",    .id = 11 },
 60	{ .n = "twi0_clk",   .id = 12 },
 61	{ .n = "spi0_clk",   .id = 13 },
 62	{ .n = "ssc0_clk",   .id = 14 },
 63	{ .n = "ssc1_clk",   .id = 15 },
 64	{ .n = "ssc2_clk",   .id = 16 },
 65	{ .n = "tc0_clk",    .id = 17 },
 66	{ .n = "tc1_clk",    .id = 18 },
 67	{ .n = "tc2_clk",    .id = 19 },
 68	{ .n = "tc3_clk",    .id = 20 },
 69	{ .n = "tc4_clk",    .id = 21 },
 70	{ .n = "tc5_clk",    .id = 22 },
 71	{ .n = "ohci_clk",   .id = 23 },
 72	{ .n = "macb0_clk",  .id = 24 },
 73};
 74
 75static void __init at91rm9200_pmc_setup(struct device_node *np)
 76{
 77	const char *slowxtal_name, *mainxtal_name;
 78	struct pmc_data *at91rm9200_pmc;
 79	u32 usb_div[] = { 1, 2, 0, 0 };
 80	const char *parent_names[6];
 81	struct regmap *regmap;
 82	struct clk_hw *hw;
 83	int i;
 84	bool bypass;
 85
 86	i = of_property_match_string(np, "clock-names", "slow_xtal");
 87	if (i < 0)
 88		return;
 89
 90	slowxtal_name = of_clk_get_parent_name(np, i);
 91
 92	i = of_property_match_string(np, "clock-names", "main_xtal");
 93	if (i < 0)
 94		return;
 95	mainxtal_name = of_clk_get_parent_name(np, i);
 96
 97	regmap = device_node_to_regmap(np);
 98	if (IS_ERR(regmap))
 99		return;
100
101	at91rm9200_pmc = pmc_data_allocate(PMC_PLLBCK + 1,
102					    nck(at91rm9200_systemck),
103					    nck(at91rm9200_periphck), 0, 4);
104	if (!at91rm9200_pmc)
105		return;
106
107	bypass = of_property_read_bool(np, "atmel,osc-bypass");
108
109	hw = at91_clk_register_main_osc(regmap, "main_osc", mainxtal_name,
110					bypass);
111	if (IS_ERR(hw))
112		goto err_free;
113
114	hw = at91_clk_register_rm9200_main(regmap, "mainck", "main_osc");
115	if (IS_ERR(hw))
116		goto err_free;
117
118	at91rm9200_pmc->chws[PMC_MAIN] = hw;
119
120	hw = at91_clk_register_pll(regmap, "pllack", "mainck", 0,
121				   &at91rm9200_pll_layout,
122				   &rm9200_pll_characteristics);
123	if (IS_ERR(hw))
124		goto err_free;
125
126	at91rm9200_pmc->chws[PMC_PLLACK] = hw;
127
128	hw = at91_clk_register_pll(regmap, "pllbck", "mainck", 1,
129				   &at91rm9200_pll_layout,
130				   &rm9200_pll_characteristics);
131	if (IS_ERR(hw))
132		goto err_free;
133
134	at91rm9200_pmc->chws[PMC_PLLBCK] = hw;
135
136	parent_names[0] = slowxtal_name;
137	parent_names[1] = "mainck";
138	parent_names[2] = "pllack";
139	parent_names[3] = "pllbck";
140	hw = at91_clk_register_master(regmap, "masterck", 4, parent_names,
141				      &at91rm9200_master_layout,
142				      &rm9200_mck_characteristics);
143	if (IS_ERR(hw))
144		goto err_free;
145
146	at91rm9200_pmc->chws[PMC_MCK] = hw;
147
148	hw = at91rm9200_clk_register_usb(regmap, "usbck", "pllbck", usb_div);
149	if (IS_ERR(hw))
150		goto err_free;
151
152	parent_names[0] = slowxtal_name;
153	parent_names[1] = "mainck";
154	parent_names[2] = "pllack";
155	parent_names[3] = "pllbck";
156	for (i = 0; i < 4; i++) {
157		char name[6];
158
159		snprintf(name, sizeof(name), "prog%d", i);
160
161		hw = at91_clk_register_programmable(regmap, name,
162						    parent_names, 4, i,
163						    &at91rm9200_programmable_layout,
164						    NULL);
165		if (IS_ERR(hw))
166			goto err_free;
167
168		at91rm9200_pmc->pchws[i] = hw;
169	}
170
171	for (i = 0; i < ARRAY_SIZE(at91rm9200_systemck); i++) {
172		hw = at91_clk_register_system(regmap, at91rm9200_systemck[i].n,
173					      at91rm9200_systemck[i].p,
174					      at91rm9200_systemck[i].id);
175		if (IS_ERR(hw))
176			goto err_free;
177
178		at91rm9200_pmc->shws[at91rm9200_systemck[i].id] = hw;
179	}
180
181	for (i = 0; i < ARRAY_SIZE(at91rm9200_periphck); i++) {
182		hw = at91_clk_register_peripheral(regmap,
183						  at91rm9200_periphck[i].n,
184						  "masterck",
185						  at91rm9200_periphck[i].id);
186		if (IS_ERR(hw))
187			goto err_free;
188
189		at91rm9200_pmc->phws[at91rm9200_periphck[i].id] = hw;
190	}
191
192	of_clk_add_hw_provider(np, of_clk_hw_pmc_get, at91rm9200_pmc);
193
194	return;
195
196err_free:
197	kfree(at91rm9200_pmc);
198}
199/*
200 * While the TCB can be used as the clocksource, the system timer is most likely
201 * to be used instead. However, the pinctrl driver doesn't support probe
202 * deferring properly. Once this is fixed, this can be switched to a platform
203 * driver.
204 */
205CLK_OF_DECLARE_DRIVER(at91rm9200_pmc, "atmel,at91rm9200-pmc",
206		      at91rm9200_pmc_setup);