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1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 *
4 * Copyright (C) 2015 Nikolay Martynov <mar.kolya@gmail.com>
5 * Copyright (C) 2015 John Crispin <john@phrozen.org>
6 */
7
8#include <linux/kernel.h>
9#include <linux/init.h>
10#include <linux/slab.h>
11#include <linux/sys_soc.h>
12
13#include <asm/mipsregs.h>
14#include <asm/smp-ops.h>
15#include <asm/mips-cps.h>
16#include <asm/mach-ralink/ralink_regs.h>
17#include <asm/mach-ralink/mt7621.h>
18
19#include <pinmux.h>
20
21#include "common.h"
22
23#define MT7621_GPIO_MODE_UART1 1
24#define MT7621_GPIO_MODE_I2C 2
25#define MT7621_GPIO_MODE_UART3_MASK 0x3
26#define MT7621_GPIO_MODE_UART3_SHIFT 3
27#define MT7621_GPIO_MODE_UART3_GPIO 1
28#define MT7621_GPIO_MODE_UART2_MASK 0x3
29#define MT7621_GPIO_MODE_UART2_SHIFT 5
30#define MT7621_GPIO_MODE_UART2_GPIO 1
31#define MT7621_GPIO_MODE_JTAG 7
32#define MT7621_GPIO_MODE_WDT_MASK 0x3
33#define MT7621_GPIO_MODE_WDT_SHIFT 8
34#define MT7621_GPIO_MODE_WDT_GPIO 1
35#define MT7621_GPIO_MODE_PCIE_RST 0
36#define MT7621_GPIO_MODE_PCIE_REF 2
37#define MT7621_GPIO_MODE_PCIE_MASK 0x3
38#define MT7621_GPIO_MODE_PCIE_SHIFT 10
39#define MT7621_GPIO_MODE_PCIE_GPIO 1
40#define MT7621_GPIO_MODE_MDIO_MASK 0x3
41#define MT7621_GPIO_MODE_MDIO_SHIFT 12
42#define MT7621_GPIO_MODE_MDIO_GPIO 1
43#define MT7621_GPIO_MODE_RGMII1 14
44#define MT7621_GPIO_MODE_RGMII2 15
45#define MT7621_GPIO_MODE_SPI_MASK 0x3
46#define MT7621_GPIO_MODE_SPI_SHIFT 16
47#define MT7621_GPIO_MODE_SPI_GPIO 1
48#define MT7621_GPIO_MODE_SDHCI_MASK 0x3
49#define MT7621_GPIO_MODE_SDHCI_SHIFT 18
50#define MT7621_GPIO_MODE_SDHCI_GPIO 1
51
52static struct rt2880_pmx_func uart1_grp[] = { FUNC("uart1", 0, 1, 2) };
53static struct rt2880_pmx_func i2c_grp[] = { FUNC("i2c", 0, 3, 2) };
54static struct rt2880_pmx_func uart3_grp[] = {
55 FUNC("uart3", 0, 5, 4),
56 FUNC("i2s", 2, 5, 4),
57 FUNC("spdif3", 3, 5, 4),
58};
59static struct rt2880_pmx_func uart2_grp[] = {
60 FUNC("uart2", 0, 9, 4),
61 FUNC("pcm", 2, 9, 4),
62 FUNC("spdif2", 3, 9, 4),
63};
64static struct rt2880_pmx_func jtag_grp[] = { FUNC("jtag", 0, 13, 5) };
65static struct rt2880_pmx_func wdt_grp[] = {
66 FUNC("wdt rst", 0, 18, 1),
67 FUNC("wdt refclk", 2, 18, 1),
68};
69static struct rt2880_pmx_func pcie_rst_grp[] = {
70 FUNC("pcie rst", MT7621_GPIO_MODE_PCIE_RST, 19, 1),
71 FUNC("pcie refclk", MT7621_GPIO_MODE_PCIE_REF, 19, 1)
72};
73static struct rt2880_pmx_func mdio_grp[] = { FUNC("mdio", 0, 20, 2) };
74static struct rt2880_pmx_func rgmii2_grp[] = { FUNC("rgmii2", 0, 22, 12) };
75static struct rt2880_pmx_func spi_grp[] = {
76 FUNC("spi", 0, 34, 7),
77 FUNC("nand1", 2, 34, 7),
78};
79static struct rt2880_pmx_func sdhci_grp[] = {
80 FUNC("sdhci", 0, 41, 8),
81 FUNC("nand2", 2, 41, 8),
82};
83static struct rt2880_pmx_func rgmii1_grp[] = { FUNC("rgmii1", 0, 49, 12) };
84
85static struct rt2880_pmx_group mt7621_pinmux_data[] = {
86 GRP("uart1", uart1_grp, 1, MT7621_GPIO_MODE_UART1),
87 GRP("i2c", i2c_grp, 1, MT7621_GPIO_MODE_I2C),
88 GRP_G("uart3", uart3_grp, MT7621_GPIO_MODE_UART3_MASK,
89 MT7621_GPIO_MODE_UART3_GPIO, MT7621_GPIO_MODE_UART3_SHIFT),
90 GRP_G("uart2", uart2_grp, MT7621_GPIO_MODE_UART2_MASK,
91 MT7621_GPIO_MODE_UART2_GPIO, MT7621_GPIO_MODE_UART2_SHIFT),
92 GRP("jtag", jtag_grp, 1, MT7621_GPIO_MODE_JTAG),
93 GRP_G("wdt", wdt_grp, MT7621_GPIO_MODE_WDT_MASK,
94 MT7621_GPIO_MODE_WDT_GPIO, MT7621_GPIO_MODE_WDT_SHIFT),
95 GRP_G("pcie", pcie_rst_grp, MT7621_GPIO_MODE_PCIE_MASK,
96 MT7621_GPIO_MODE_PCIE_GPIO, MT7621_GPIO_MODE_PCIE_SHIFT),
97 GRP_G("mdio", mdio_grp, MT7621_GPIO_MODE_MDIO_MASK,
98 MT7621_GPIO_MODE_MDIO_GPIO, MT7621_GPIO_MODE_MDIO_SHIFT),
99 GRP("rgmii2", rgmii2_grp, 1, MT7621_GPIO_MODE_RGMII2),
100 GRP_G("spi", spi_grp, MT7621_GPIO_MODE_SPI_MASK,
101 MT7621_GPIO_MODE_SPI_GPIO, MT7621_GPIO_MODE_SPI_SHIFT),
102 GRP_G("sdhci", sdhci_grp, MT7621_GPIO_MODE_SDHCI_MASK,
103 MT7621_GPIO_MODE_SDHCI_GPIO, MT7621_GPIO_MODE_SDHCI_SHIFT),
104 GRP("rgmii1", rgmii1_grp, 1, MT7621_GPIO_MODE_RGMII1),
105 { 0 }
106};
107
108phys_addr_t mips_cpc_default_phys_base(void)
109{
110 panic("Cannot detect cpc address");
111}
112
113void __init ralink_of_remap(void)
114{
115 rt_sysc_membase = plat_of_remap_node("mtk,mt7621-sysc");
116 rt_memc_membase = plat_of_remap_node("mtk,mt7621-memc");
117
118 if (!rt_sysc_membase || !rt_memc_membase)
119 panic("Failed to remap core resources");
120}
121
122static void soc_dev_init(struct ralink_soc_info *soc_info, u32 rev)
123{
124 struct soc_device *soc_dev;
125 struct soc_device_attribute *soc_dev_attr;
126
127 soc_dev_attr = kzalloc(sizeof(*soc_dev_attr), GFP_KERNEL);
128 if (!soc_dev_attr)
129 return;
130
131 soc_dev_attr->soc_id = "mt7621";
132 soc_dev_attr->family = "Ralink";
133
134 if (((rev >> CHIP_REV_VER_SHIFT) & CHIP_REV_VER_MASK) == 1 &&
135 (rev & CHIP_REV_ECO_MASK) == 1)
136 soc_dev_attr->revision = "E2";
137 else
138 soc_dev_attr->revision = "E1";
139
140 soc_dev_attr->data = soc_info;
141
142 soc_dev = soc_device_register(soc_dev_attr);
143 if (IS_ERR(soc_dev)) {
144 kfree(soc_dev_attr);
145 return;
146 }
147}
148
149void prom_soc_init(struct ralink_soc_info *soc_info)
150{
151 void __iomem *sysc = (void __iomem *) KSEG1ADDR(MT7621_SYSC_BASE);
152 unsigned char *name = NULL;
153 u32 n0;
154 u32 n1;
155 u32 rev;
156
157 /* Early detection of CMP support */
158 mips_cm_probe();
159 mips_cpc_probe();
160
161 if (mips_cps_numiocu(0)) {
162 /*
163 * mips_cm_probe() wipes out bootloader
164 * config for CM regions and we have to configure them
165 * again. This SoC cannot talk to pamlbus devices
166 * witout proper iocu region set up.
167 *
168 * FIXME: it would be better to do this with values
169 * from DT, but we need this very early because
170 * without this we cannot talk to pretty much anything
171 * including serial.
172 */
173 write_gcr_reg0_base(MT7621_PALMBUS_BASE);
174 write_gcr_reg0_mask(~MT7621_PALMBUS_SIZE |
175 CM_GCR_REGn_MASK_CMTGT_IOCU0);
176 __sync();
177 }
178
179 n0 = __raw_readl(sysc + SYSC_REG_CHIP_NAME0);
180 n1 = __raw_readl(sysc + SYSC_REG_CHIP_NAME1);
181
182 if (n0 == MT7621_CHIP_NAME0 && n1 == MT7621_CHIP_NAME1) {
183 name = "MT7621";
184 soc_info->compatible = "mtk,mt7621-soc";
185 } else {
186 panic("mt7621: unknown SoC, n0:%08x n1:%08x\n", n0, n1);
187 }
188 ralink_soc = MT762X_SOC_MT7621AT;
189 rev = __raw_readl(sysc + SYSC_REG_CHIP_REV);
190
191 snprintf(soc_info->sys_type, RAMIPS_SYS_TYPE_LEN,
192 "MediaTek %s ver:%u eco:%u",
193 name,
194 (rev >> CHIP_REV_VER_SHIFT) & CHIP_REV_VER_MASK,
195 (rev & CHIP_REV_ECO_MASK));
196
197 soc_info->mem_size_min = MT7621_DDR2_SIZE_MIN;
198 soc_info->mem_size_max = MT7621_DDR2_SIZE_MAX;
199 soc_info->mem_base = MT7621_DRAM_BASE;
200
201 rt2880_pinmux_data = mt7621_pinmux_data;
202
203 soc_dev_init(soc_info, rev);
204
205 if (!register_cps_smp_ops())
206 return;
207 if (!register_cmp_smp_ops())
208 return;
209 if (!register_vsmp_smp_ops())
210 return;
211}