1// SPDX-License-Identifier: GPL-2.0
  2/***************************************************************************/
  3
  4/*
  5 *	timers.c -- generic ColdFire hardware timer support.
  6 *
  7 *	Copyright (C) 1999-2008, Greg Ungerer <gerg@snapgear.com>
  8 */
  9
 10/***************************************************************************/
 11
 12#include <linux/kernel.h>
 13#include <linux/init.h>
 14#include <linux/sched.h>
 15#include <linux/interrupt.h>
 16#include <linux/irq.h>
 17#include <linux/profile.h>
 18#include <linux/clocksource.h>
 19#include <asm/io.h>
 20#include <asm/traps.h>
 21#include <asm/machdep.h>
 22#include <asm/coldfire.h>
 23#include <asm/mcftimer.h>
 24#include <asm/mcfsim.h>
 25
 26/***************************************************************************/
 27
 28/*
 29 *	By default use timer1 as the system clock timer.
 30 */
 31#define	FREQ	(MCF_BUSCLK / 16)
 32#define	TA(a)	(MCFTIMER_BASE1 + (a))
 33
 34/*
 35 *	These provide the underlying interrupt vector support.
 36 *	Unfortunately it is a little different on each ColdFire.
 37 */
 38void coldfire_profile_init(void);
 39
 40#if defined(CONFIG_M53xx) || defined(CONFIG_M5441x)
 41#define	__raw_readtrr	__raw_readl
 42#define	__raw_writetrr	__raw_writel
 43#else
 44#define	__raw_readtrr	__raw_readw
 45#define	__raw_writetrr	__raw_writew
 46#endif
 47
 48static u32 mcftmr_cycles_per_jiffy;
 49static u32 mcftmr_cnt;
 50
 51static irq_handler_t timer_interrupt;
 52
 53/***************************************************************************/
 54
 55static void init_timer_irq(void)
 56{
 57#ifdef MCFSIM_ICR_AUTOVEC
 58	/* Timer1 is always used as system timer */
 59	writeb(MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL6 | MCFSIM_ICR_PRI3,
 60		MCFSIM_TIMER1ICR);
 61	mcf_mapirq2imr(MCF_IRQ_TIMER, MCFINTC_TIMER1);
 62
 63#ifdef CONFIG_HIGHPROFILE
 64	/* Timer2 is to be used as a high speed profile timer  */
 65	writeb(MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL7 | MCFSIM_ICR_PRI3,
 66		MCFSIM_TIMER2ICR);
 67	mcf_mapirq2imr(MCF_IRQ_PROFILER, MCFINTC_TIMER2);
 68#endif
 69#endif /* MCFSIM_ICR_AUTOVEC */
 70}
 71
 72/***************************************************************************/
 73
 74static irqreturn_t mcftmr_tick(int irq, void *dummy)
 75{
 76	/* Reset the ColdFire timer */
 77	__raw_writeb(MCFTIMER_TER_CAP | MCFTIMER_TER_REF, TA(MCFTIMER_TER));
 78
 79	mcftmr_cnt += mcftmr_cycles_per_jiffy;
 80	return timer_interrupt(irq, dummy);
 81}
 82
 83/***************************************************************************/
 84
 85static u64 mcftmr_read_clk(struct clocksource *cs)
 86{
 87	unsigned long flags;
 88	u32 cycles;
 89	u16 tcn;
 90
 91	local_irq_save(flags);
 92	tcn = __raw_readw(TA(MCFTIMER_TCN));
 93	cycles = mcftmr_cnt;
 94	local_irq_restore(flags);
 95
 96	return cycles + tcn;
 97}
 98
 99/***************************************************************************/
100
101static struct clocksource mcftmr_clk = {
102	.name	= "tmr",
103	.rating	= 250,
104	.read	= mcftmr_read_clk,
105	.mask	= CLOCKSOURCE_MASK(32),
106	.flags	= CLOCK_SOURCE_IS_CONTINUOUS,
107};
108
109/***************************************************************************/
110
111void hw_timer_init(irq_handler_t handler)
112{
113	int r;
114
115	__raw_writew(MCFTIMER_TMR_DISABLE, TA(MCFTIMER_TMR));
116	mcftmr_cycles_per_jiffy = FREQ / HZ;
117	/*
118	 *	The coldfire timer runs from 0 to TRR included, then 0
119	 *	again and so on.  It counts thus actually TRR + 1 steps
120	 *	for 1 tick, not TRR.  So if you want n cycles,
121	 *	initialize TRR with n - 1.
122	 */
123	__raw_writetrr(mcftmr_cycles_per_jiffy - 1, TA(MCFTIMER_TRR));
124	__raw_writew(MCFTIMER_TMR_ENORI | MCFTIMER_TMR_CLK16 |
125		MCFTIMER_TMR_RESTART | MCFTIMER_TMR_ENABLE, TA(MCFTIMER_TMR));
126
127	clocksource_register_hz(&mcftmr_clk, FREQ);
128
129	timer_interrupt = handler;
130	init_timer_irq();
131	r = request_irq(MCF_IRQ_TIMER, mcftmr_tick, IRQF_TIMER, "timer", NULL);
132	if (r) {
133		pr_err("Failed to request irq %d (timer): %pe\n", MCF_IRQ_TIMER,
134		       ERR_PTR(r));
135	}
136
137#ifdef CONFIG_HIGHPROFILE
138	coldfire_profile_init();
139#endif
140}
141
142/***************************************************************************/
143#ifdef CONFIG_HIGHPROFILE
144/***************************************************************************/
145
146/*
147 *	By default use timer2 as the profiler clock timer.
148 */
149#define	PA(a)	(MCFTIMER_BASE2 + (a))
150
151/*
152 *	Choose a reasonably fast profile timer. Make it an odd value to
153 *	try and get good coverage of kernel operations.
154 */
155#define	PROFILEHZ	1013
156
157/*
158 *	Use the other timer to provide high accuracy profiling info.
159 */
160irqreturn_t coldfire_profile_tick(int irq, void *dummy)
161{
162	/* Reset ColdFire timer2 */
163	__raw_writeb(MCFTIMER_TER_CAP | MCFTIMER_TER_REF, PA(MCFTIMER_TER));
164	if (current->pid)
165		profile_tick(CPU_PROFILING);
166	return IRQ_HANDLED;
167}
168
169/***************************************************************************/
170
171void coldfire_profile_init(void)
172{
173	int ret;
174
175	printk(KERN_INFO "PROFILE: lodging TIMER2 @ %dHz as profile timer\n",
176	       PROFILEHZ);
177
178	/* Set up TIMER 2 as high speed profile clock */
179	__raw_writew(MCFTIMER_TMR_DISABLE, PA(MCFTIMER_TMR));
180
181	__raw_writetrr(((MCF_BUSCLK / 16) / PROFILEHZ), PA(MCFTIMER_TRR));
182	__raw_writew(MCFTIMER_TMR_ENORI | MCFTIMER_TMR_CLK16 |
183		MCFTIMER_TMR_RESTART | MCFTIMER_TMR_ENABLE, PA(MCFTIMER_TMR));
184
185	ret = request_irq(MCF_IRQ_PROFILER, coldfire_profile_tick, IRQF_TIMER,
186			  "profile timer", NULL);
187	if (ret) {
188		pr_err("Failed to request irq %d (profile timer): %pe\n",
189		       MCF_IRQ_PROFILER, ERR_PTR(ret));
190	}
191}
192
193/***************************************************************************/
194#endif	/* CONFIG_HIGHPROFILE */
195/***************************************************************************/