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1/*
2 * twl4030_usb - TWL4030 USB transceiver, talking to OMAP OTG controller
3 *
4 * Copyright (C) 2004-2007 Texas Instruments
5 * Copyright (C) 2008 Nokia Corporation
6 * Contact: Felipe Balbi <felipe.balbi@nokia.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
21 *
22 * Current status:
23 * - HS USB ULPI mode works.
24 * - 3-pin mode support may be added in future.
25 */
26
27#include <linux/module.h>
28#include <linux/init.h>
29#include <linux/interrupt.h>
30#include <linux/platform_device.h>
31#include <linux/spinlock.h>
32#include <linux/workqueue.h>
33#include <linux/io.h>
34#include <linux/delay.h>
35#include <linux/usb/otg.h>
36#include <linux/usb/ulpi.h>
37#include <linux/i2c/twl.h>
38#include <linux/regulator/consumer.h>
39#include <linux/err.h>
40#include <linux/notifier.h>
41#include <linux/slab.h>
42
43/* Register defines */
44
45#define MCPC_CTRL 0x30
46#define MCPC_CTRL_RTSOL (1 << 7)
47#define MCPC_CTRL_EXTSWR (1 << 6)
48#define MCPC_CTRL_EXTSWC (1 << 5)
49#define MCPC_CTRL_VOICESW (1 << 4)
50#define MCPC_CTRL_OUT64K (1 << 3)
51#define MCPC_CTRL_RTSCTSSW (1 << 2)
52#define MCPC_CTRL_HS_UART (1 << 0)
53
54#define MCPC_IO_CTRL 0x33
55#define MCPC_IO_CTRL_MICBIASEN (1 << 5)
56#define MCPC_IO_CTRL_CTS_NPU (1 << 4)
57#define MCPC_IO_CTRL_RXD_PU (1 << 3)
58#define MCPC_IO_CTRL_TXDTYP (1 << 2)
59#define MCPC_IO_CTRL_CTSTYP (1 << 1)
60#define MCPC_IO_CTRL_RTSTYP (1 << 0)
61
62#define MCPC_CTRL2 0x36
63#define MCPC_CTRL2_MCPC_CK_EN (1 << 0)
64
65#define OTHER_FUNC_CTRL 0x80
66#define OTHER_FUNC_CTRL_BDIS_ACON_EN (1 << 4)
67#define OTHER_FUNC_CTRL_FIVEWIRE_MODE (1 << 2)
68
69#define OTHER_IFC_CTRL 0x83
70#define OTHER_IFC_CTRL_OE_INT_EN (1 << 6)
71#define OTHER_IFC_CTRL_CEA2011_MODE (1 << 5)
72#define OTHER_IFC_CTRL_FSLSSERIALMODE_4PIN (1 << 4)
73#define OTHER_IFC_CTRL_HIZ_ULPI_60MHZ_OUT (1 << 3)
74#define OTHER_IFC_CTRL_HIZ_ULPI (1 << 2)
75#define OTHER_IFC_CTRL_ALT_INT_REROUTE (1 << 0)
76
77#define OTHER_INT_EN_RISE 0x86
78#define OTHER_INT_EN_FALL 0x89
79#define OTHER_INT_STS 0x8C
80#define OTHER_INT_LATCH 0x8D
81#define OTHER_INT_VB_SESS_VLD (1 << 7)
82#define OTHER_INT_DM_HI (1 << 6) /* not valid for "latch" reg */
83#define OTHER_INT_DP_HI (1 << 5) /* not valid for "latch" reg */
84#define OTHER_INT_BDIS_ACON (1 << 3) /* not valid for "fall" regs */
85#define OTHER_INT_MANU (1 << 1)
86#define OTHER_INT_ABNORMAL_STRESS (1 << 0)
87
88#define ID_STATUS 0x96
89#define ID_RES_FLOAT (1 << 4)
90#define ID_RES_440K (1 << 3)
91#define ID_RES_200K (1 << 2)
92#define ID_RES_102K (1 << 1)
93#define ID_RES_GND (1 << 0)
94
95#define POWER_CTRL 0xAC
96#define POWER_CTRL_OTG_ENAB (1 << 5)
97
98#define OTHER_IFC_CTRL2 0xAF
99#define OTHER_IFC_CTRL2_ULPI_STP_LOW (1 << 4)
100#define OTHER_IFC_CTRL2_ULPI_TXEN_POL (1 << 3)
101#define OTHER_IFC_CTRL2_ULPI_4PIN_2430 (1 << 2)
102#define OTHER_IFC_CTRL2_USB_INT_OUTSEL_MASK (3 << 0) /* bits 0 and 1 */
103#define OTHER_IFC_CTRL2_USB_INT_OUTSEL_INT1N (0 << 0)
104#define OTHER_IFC_CTRL2_USB_INT_OUTSEL_INT2N (1 << 0)
105
106#define REG_CTRL_EN 0xB2
107#define REG_CTRL_ERROR 0xB5
108#define ULPI_I2C_CONFLICT_INTEN (1 << 0)
109
110#define OTHER_FUNC_CTRL2 0xB8
111#define OTHER_FUNC_CTRL2_VBAT_TIMER_EN (1 << 0)
112
113/* following registers do not have separate _clr and _set registers */
114#define VBUS_DEBOUNCE 0xC0
115#define ID_DEBOUNCE 0xC1
116#define VBAT_TIMER 0xD3
117#define PHY_PWR_CTRL 0xFD
118#define PHY_PWR_PHYPWD (1 << 0)
119#define PHY_CLK_CTRL 0xFE
120#define PHY_CLK_CTRL_CLOCKGATING_EN (1 << 2)
121#define PHY_CLK_CTRL_CLK32K_EN (1 << 1)
122#define REQ_PHY_DPLL_CLK (1 << 0)
123#define PHY_CLK_CTRL_STS 0xFF
124#define PHY_DPLL_CLK (1 << 0)
125
126/* In module TWL4030_MODULE_PM_MASTER */
127#define STS_HW_CONDITIONS 0x0F
128
129/* In module TWL4030_MODULE_PM_RECEIVER */
130#define VUSB_DEDICATED1 0x7D
131#define VUSB_DEDICATED2 0x7E
132#define VUSB1V5_DEV_GRP 0x71
133#define VUSB1V5_TYPE 0x72
134#define VUSB1V5_REMAP 0x73
135#define VUSB1V8_DEV_GRP 0x74
136#define VUSB1V8_TYPE 0x75
137#define VUSB1V8_REMAP 0x76
138#define VUSB3V1_DEV_GRP 0x77
139#define VUSB3V1_TYPE 0x78
140#define VUSB3V1_REMAP 0x79
141
142/* In module TWL4030_MODULE_INTBR */
143#define PMBR1 0x0D
144#define GPIO_USB_4PIN_ULPI_2430C (3 << 0)
145
146struct twl4030_usb {
147 struct otg_transceiver otg;
148 struct device *dev;
149
150 /* TWL4030 internal USB regulator supplies */
151 struct regulator *usb1v5;
152 struct regulator *usb1v8;
153 struct regulator *usb3v1;
154
155 /* for vbus reporting with irqs disabled */
156 spinlock_t lock;
157
158 /* pin configuration */
159 enum twl4030_usb_mode usb_mode;
160
161 int irq;
162 u8 linkstat;
163 bool vbus_supplied;
164 u8 asleep;
165 bool irq_enabled;
166};
167
168/* internal define on top of container_of */
169#define xceiv_to_twl(x) container_of((x), struct twl4030_usb, otg)
170
171/*-------------------------------------------------------------------------*/
172
173static int twl4030_i2c_write_u8_verify(struct twl4030_usb *twl,
174 u8 module, u8 data, u8 address)
175{
176 u8 check;
177
178 if ((twl_i2c_write_u8(module, data, address) >= 0) &&
179 (twl_i2c_read_u8(module, &check, address) >= 0) &&
180 (check == data))
181 return 0;
182 dev_dbg(twl->dev, "Write%d[%d,0x%x] wrote %02x but read %02x\n",
183 1, module, address, check, data);
184
185 /* Failed once: Try again */
186 if ((twl_i2c_write_u8(module, data, address) >= 0) &&
187 (twl_i2c_read_u8(module, &check, address) >= 0) &&
188 (check == data))
189 return 0;
190 dev_dbg(twl->dev, "Write%d[%d,0x%x] wrote %02x but read %02x\n",
191 2, module, address, check, data);
192
193 /* Failed again: Return error */
194 return -EBUSY;
195}
196
197#define twl4030_usb_write_verify(twl, address, data) \
198 twl4030_i2c_write_u8_verify(twl, TWL4030_MODULE_USB, (data), (address))
199
200static inline int twl4030_usb_write(struct twl4030_usb *twl,
201 u8 address, u8 data)
202{
203 int ret = 0;
204
205 ret = twl_i2c_write_u8(TWL4030_MODULE_USB, data, address);
206 if (ret < 0)
207 dev_dbg(twl->dev,
208 "TWL4030:USB:Write[0x%x] Error %d\n", address, ret);
209 return ret;
210}
211
212static inline int twl4030_readb(struct twl4030_usb *twl, u8 module, u8 address)
213{
214 u8 data;
215 int ret = 0;
216
217 ret = twl_i2c_read_u8(module, &data, address);
218 if (ret >= 0)
219 ret = data;
220 else
221 dev_dbg(twl->dev,
222 "TWL4030:readb[0x%x,0x%x] Error %d\n",
223 module, address, ret);
224
225 return ret;
226}
227
228static inline int twl4030_usb_read(struct twl4030_usb *twl, u8 address)
229{
230 return twl4030_readb(twl, TWL4030_MODULE_USB, address);
231}
232
233/*-------------------------------------------------------------------------*/
234
235static inline int
236twl4030_usb_set_bits(struct twl4030_usb *twl, u8 reg, u8 bits)
237{
238 return twl4030_usb_write(twl, ULPI_SET(reg), bits);
239}
240
241static inline int
242twl4030_usb_clear_bits(struct twl4030_usb *twl, u8 reg, u8 bits)
243{
244 return twl4030_usb_write(twl, ULPI_CLR(reg), bits);
245}
246
247/*-------------------------------------------------------------------------*/
248
249static enum usb_xceiv_events twl4030_usb_linkstat(struct twl4030_usb *twl)
250{
251 int status;
252 int linkstat = USB_EVENT_NONE;
253
254 twl->vbus_supplied = false;
255
256 /*
257 * For ID/VBUS sensing, see manual section 15.4.8 ...
258 * except when using only battery backup power, two
259 * comparators produce VBUS_PRES and ID_PRES signals,
260 * which don't match docs elsewhere. But ... BIT(7)
261 * and BIT(2) of STS_HW_CONDITIONS, respectively, do
262 * seem to match up. If either is true the USB_PRES
263 * signal is active, the OTG module is activated, and
264 * its interrupt may be raised (may wake the system).
265 */
266 status = twl4030_readb(twl, TWL4030_MODULE_PM_MASTER,
267 STS_HW_CONDITIONS);
268 if (status < 0)
269 dev_err(twl->dev, "USB link status err %d\n", status);
270 else if (status & (BIT(7) | BIT(2))) {
271 if (status & (BIT(7)))
272 twl->vbus_supplied = true;
273
274 if (status & BIT(2))
275 linkstat = USB_EVENT_ID;
276 else
277 linkstat = USB_EVENT_VBUS;
278 } else
279 linkstat = USB_EVENT_NONE;
280
281 dev_dbg(twl->dev, "HW_CONDITIONS 0x%02x/%d; link %d\n",
282 status, status, linkstat);
283
284 twl->otg.last_event = linkstat;
285
286 /* REVISIT this assumes host and peripheral controllers
287 * are registered, and that both are active...
288 */
289
290 spin_lock_irq(&twl->lock);
291 twl->linkstat = linkstat;
292 if (linkstat == USB_EVENT_ID) {
293 twl->otg.default_a = true;
294 twl->otg.state = OTG_STATE_A_IDLE;
295 } else {
296 twl->otg.default_a = false;
297 twl->otg.state = OTG_STATE_B_IDLE;
298 }
299 spin_unlock_irq(&twl->lock);
300
301 return linkstat;
302}
303
304static void twl4030_usb_set_mode(struct twl4030_usb *twl, int mode)
305{
306 twl->usb_mode = mode;
307
308 switch (mode) {
309 case T2_USB_MODE_ULPI:
310 twl4030_usb_clear_bits(twl, ULPI_IFC_CTRL,
311 ULPI_IFC_CTRL_CARKITMODE);
312 twl4030_usb_set_bits(twl, POWER_CTRL, POWER_CTRL_OTG_ENAB);
313 twl4030_usb_clear_bits(twl, ULPI_FUNC_CTRL,
314 ULPI_FUNC_CTRL_XCVRSEL_MASK |
315 ULPI_FUNC_CTRL_OPMODE_MASK);
316 break;
317 case -1:
318 /* FIXME: power on defaults */
319 break;
320 default:
321 dev_err(twl->dev, "unsupported T2 transceiver mode %d\n",
322 mode);
323 break;
324 };
325}
326
327static void twl4030_i2c_access(struct twl4030_usb *twl, int on)
328{
329 unsigned long timeout;
330 int val = twl4030_usb_read(twl, PHY_CLK_CTRL);
331
332 if (val >= 0) {
333 if (on) {
334 /* enable DPLL to access PHY registers over I2C */
335 val |= REQ_PHY_DPLL_CLK;
336 WARN_ON(twl4030_usb_write_verify(twl, PHY_CLK_CTRL,
337 (u8)val) < 0);
338
339 timeout = jiffies + HZ;
340 while (!(twl4030_usb_read(twl, PHY_CLK_CTRL_STS) &
341 PHY_DPLL_CLK)
342 && time_before(jiffies, timeout))
343 udelay(10);
344 if (!(twl4030_usb_read(twl, PHY_CLK_CTRL_STS) &
345 PHY_DPLL_CLK))
346 dev_err(twl->dev, "Timeout setting T2 HSUSB "
347 "PHY DPLL clock\n");
348 } else {
349 /* let ULPI control the DPLL clock */
350 val &= ~REQ_PHY_DPLL_CLK;
351 WARN_ON(twl4030_usb_write_verify(twl, PHY_CLK_CTRL,
352 (u8)val) < 0);
353 }
354 }
355}
356
357static void __twl4030_phy_power(struct twl4030_usb *twl, int on)
358{
359 u8 pwr = twl4030_usb_read(twl, PHY_PWR_CTRL);
360
361 if (on)
362 pwr &= ~PHY_PWR_PHYPWD;
363 else
364 pwr |= PHY_PWR_PHYPWD;
365
366 WARN_ON(twl4030_usb_write_verify(twl, PHY_PWR_CTRL, pwr) < 0);
367}
368
369static void twl4030_phy_power(struct twl4030_usb *twl, int on)
370{
371 if (on) {
372 regulator_enable(twl->usb3v1);
373 regulator_enable(twl->usb1v8);
374 /*
375 * Disabling usb3v1 regulator (= writing 0 to VUSB3V1_DEV_GRP
376 * in twl4030) resets the VUSB_DEDICATED2 register. This reset
377 * enables VUSB3V1_SLEEP bit that remaps usb3v1 ACTIVE state to
378 * SLEEP. We work around this by clearing the bit after usv3v1
379 * is re-activated. This ensures that VUSB3V1 is really active.
380 */
381 twl_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER, 0,
382 VUSB_DEDICATED2);
383 regulator_enable(twl->usb1v5);
384 __twl4030_phy_power(twl, 1);
385 twl4030_usb_write(twl, PHY_CLK_CTRL,
386 twl4030_usb_read(twl, PHY_CLK_CTRL) |
387 (PHY_CLK_CTRL_CLOCKGATING_EN |
388 PHY_CLK_CTRL_CLK32K_EN));
389 } else {
390 __twl4030_phy_power(twl, 0);
391 regulator_disable(twl->usb1v5);
392 regulator_disable(twl->usb1v8);
393 regulator_disable(twl->usb3v1);
394 }
395}
396
397static void twl4030_phy_suspend(struct twl4030_usb *twl, int controller_off)
398{
399 if (twl->asleep)
400 return;
401
402 twl4030_phy_power(twl, 0);
403 twl->asleep = 1;
404 dev_dbg(twl->dev, "%s\n", __func__);
405}
406
407static void __twl4030_phy_resume(struct twl4030_usb *twl)
408{
409 twl4030_phy_power(twl, 1);
410 twl4030_i2c_access(twl, 1);
411 twl4030_usb_set_mode(twl, twl->usb_mode);
412 if (twl->usb_mode == T2_USB_MODE_ULPI)
413 twl4030_i2c_access(twl, 0);
414}
415
416static void twl4030_phy_resume(struct twl4030_usb *twl)
417{
418 if (!twl->asleep)
419 return;
420 __twl4030_phy_resume(twl);
421 twl->asleep = 0;
422 dev_dbg(twl->dev, "%s\n", __func__);
423}
424
425static int twl4030_usb_ldo_init(struct twl4030_usb *twl)
426{
427 /* Enable writing to power configuration registers */
428 twl_i2c_write_u8(TWL4030_MODULE_PM_MASTER,
429 TWL4030_PM_MASTER_KEY_CFG1,
430 TWL4030_PM_MASTER_PROTECT_KEY);
431
432 twl_i2c_write_u8(TWL4030_MODULE_PM_MASTER,
433 TWL4030_PM_MASTER_KEY_CFG2,
434 TWL4030_PM_MASTER_PROTECT_KEY);
435
436 /* Keep VUSB3V1 LDO in sleep state until VBUS/ID change detected*/
437 /*twl_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER, 0, VUSB_DEDICATED2);*/
438
439 /* input to VUSB3V1 LDO is from VBAT, not VBUS */
440 twl_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER, 0x14, VUSB_DEDICATED1);
441
442 /* Initialize 3.1V regulator */
443 twl_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER, 0, VUSB3V1_DEV_GRP);
444
445 twl->usb3v1 = regulator_get(twl->dev, "usb3v1");
446 if (IS_ERR(twl->usb3v1))
447 return -ENODEV;
448
449 twl_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER, 0, VUSB3V1_TYPE);
450
451 /* Initialize 1.5V regulator */
452 twl_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER, 0, VUSB1V5_DEV_GRP);
453
454 twl->usb1v5 = regulator_get(twl->dev, "usb1v5");
455 if (IS_ERR(twl->usb1v5))
456 goto fail1;
457
458 twl_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER, 0, VUSB1V5_TYPE);
459
460 /* Initialize 1.8V regulator */
461 twl_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER, 0, VUSB1V8_DEV_GRP);
462
463 twl->usb1v8 = regulator_get(twl->dev, "usb1v8");
464 if (IS_ERR(twl->usb1v8))
465 goto fail2;
466
467 twl_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER, 0, VUSB1V8_TYPE);
468
469 /* disable access to power configuration registers */
470 twl_i2c_write_u8(TWL4030_MODULE_PM_MASTER, 0,
471 TWL4030_PM_MASTER_PROTECT_KEY);
472
473 return 0;
474
475fail2:
476 regulator_put(twl->usb1v5);
477 twl->usb1v5 = NULL;
478fail1:
479 regulator_put(twl->usb3v1);
480 twl->usb3v1 = NULL;
481 return -ENODEV;
482}
483
484static ssize_t twl4030_usb_vbus_show(struct device *dev,
485 struct device_attribute *attr, char *buf)
486{
487 struct twl4030_usb *twl = dev_get_drvdata(dev);
488 unsigned long flags;
489 int ret = -EINVAL;
490
491 spin_lock_irqsave(&twl->lock, flags);
492 ret = sprintf(buf, "%s\n",
493 twl->vbus_supplied ? "on" : "off");
494 spin_unlock_irqrestore(&twl->lock, flags);
495
496 return ret;
497}
498static DEVICE_ATTR(vbus, 0444, twl4030_usb_vbus_show, NULL);
499
500static irqreturn_t twl4030_usb_irq(int irq, void *_twl)
501{
502 struct twl4030_usb *twl = _twl;
503 int status;
504
505 status = twl4030_usb_linkstat(twl);
506 if (status >= 0) {
507 /* FIXME add a set_power() method so that B-devices can
508 * configure the charger appropriately. It's not always
509 * correct to consume VBUS power, and how much current to
510 * consume is a function of the USB configuration chosen
511 * by the host.
512 *
513 * REVISIT usb_gadget_vbus_connect(...) as needed, ditto
514 * its disconnect() sibling, when changing to/from the
515 * USB_LINK_VBUS state. musb_hdrc won't care until it
516 * starts to handle softconnect right.
517 */
518 if (status == USB_EVENT_NONE)
519 twl4030_phy_suspend(twl, 0);
520 else
521 twl4030_phy_resume(twl);
522
523 atomic_notifier_call_chain(&twl->otg.notifier, status,
524 twl->otg.gadget);
525 }
526 sysfs_notify(&twl->dev->kobj, NULL, "vbus");
527
528 return IRQ_HANDLED;
529}
530
531static void twl4030_usb_phy_init(struct twl4030_usb *twl)
532{
533 int status;
534
535 status = twl4030_usb_linkstat(twl);
536 if (status >= 0) {
537 if (status == USB_EVENT_NONE) {
538 __twl4030_phy_power(twl, 0);
539 twl->asleep = 1;
540 } else {
541 __twl4030_phy_resume(twl);
542 twl->asleep = 0;
543 }
544
545 atomic_notifier_call_chain(&twl->otg.notifier, status,
546 twl->otg.gadget);
547 }
548 sysfs_notify(&twl->dev->kobj, NULL, "vbus");
549}
550
551static int twl4030_set_suspend(struct otg_transceiver *x, int suspend)
552{
553 struct twl4030_usb *twl = xceiv_to_twl(x);
554
555 if (suspend)
556 twl4030_phy_suspend(twl, 1);
557 else
558 twl4030_phy_resume(twl);
559
560 return 0;
561}
562
563static int twl4030_set_peripheral(struct otg_transceiver *x,
564 struct usb_gadget *gadget)
565{
566 struct twl4030_usb *twl;
567
568 if (!x)
569 return -ENODEV;
570
571 twl = xceiv_to_twl(x);
572 twl->otg.gadget = gadget;
573 if (!gadget)
574 twl->otg.state = OTG_STATE_UNDEFINED;
575
576 return 0;
577}
578
579static int twl4030_set_host(struct otg_transceiver *x, struct usb_bus *host)
580{
581 struct twl4030_usb *twl;
582
583 if (!x)
584 return -ENODEV;
585
586 twl = xceiv_to_twl(x);
587 twl->otg.host = host;
588 if (!host)
589 twl->otg.state = OTG_STATE_UNDEFINED;
590
591 return 0;
592}
593
594static int __devinit twl4030_usb_probe(struct platform_device *pdev)
595{
596 struct twl4030_usb_data *pdata = pdev->dev.platform_data;
597 struct twl4030_usb *twl;
598 int status, err;
599
600 if (!pdata) {
601 dev_dbg(&pdev->dev, "platform_data not available\n");
602 return -EINVAL;
603 }
604
605 twl = kzalloc(sizeof *twl, GFP_KERNEL);
606 if (!twl)
607 return -ENOMEM;
608
609 twl->dev = &pdev->dev;
610 twl->irq = platform_get_irq(pdev, 0);
611 twl->otg.dev = twl->dev;
612 twl->otg.label = "twl4030";
613 twl->otg.set_host = twl4030_set_host;
614 twl->otg.set_peripheral = twl4030_set_peripheral;
615 twl->otg.set_suspend = twl4030_set_suspend;
616 twl->usb_mode = pdata->usb_mode;
617 twl->vbus_supplied = false;
618 twl->asleep = 1;
619
620 /* init spinlock for workqueue */
621 spin_lock_init(&twl->lock);
622
623 err = twl4030_usb_ldo_init(twl);
624 if (err) {
625 dev_err(&pdev->dev, "ldo init failed\n");
626 kfree(twl);
627 return err;
628 }
629 otg_set_transceiver(&twl->otg);
630
631 platform_set_drvdata(pdev, twl);
632 if (device_create_file(&pdev->dev, &dev_attr_vbus))
633 dev_warn(&pdev->dev, "could not create sysfs file\n");
634
635 ATOMIC_INIT_NOTIFIER_HEAD(&twl->otg.notifier);
636
637 /* Our job is to use irqs and status from the power module
638 * to keep the transceiver disabled when nothing's connected.
639 *
640 * FIXME we actually shouldn't start enabling it until the
641 * USB controller drivers have said they're ready, by calling
642 * set_host() and/or set_peripheral() ... OTG_capable boards
643 * need both handles, otherwise just one suffices.
644 */
645 twl->irq_enabled = true;
646 status = request_threaded_irq(twl->irq, NULL, twl4030_usb_irq,
647 IRQF_TRIGGER_FALLING | IRQF_TRIGGER_RISING,
648 "twl4030_usb", twl);
649 if (status < 0) {
650 dev_dbg(&pdev->dev, "can't get IRQ %d, err %d\n",
651 twl->irq, status);
652 kfree(twl);
653 return status;
654 }
655
656 /* Power down phy or make it work according to
657 * current link state.
658 */
659 twl4030_usb_phy_init(twl);
660
661 dev_info(&pdev->dev, "Initialized TWL4030 USB module\n");
662 return 0;
663}
664
665static int __exit twl4030_usb_remove(struct platform_device *pdev)
666{
667 struct twl4030_usb *twl = platform_get_drvdata(pdev);
668 int val;
669
670 free_irq(twl->irq, twl);
671 device_remove_file(twl->dev, &dev_attr_vbus);
672
673 /* set transceiver mode to power on defaults */
674 twl4030_usb_set_mode(twl, -1);
675
676 /* autogate 60MHz ULPI clock,
677 * clear dpll clock request for i2c access,
678 * disable 32KHz
679 */
680 val = twl4030_usb_read(twl, PHY_CLK_CTRL);
681 if (val >= 0) {
682 val |= PHY_CLK_CTRL_CLOCKGATING_EN;
683 val &= ~(PHY_CLK_CTRL_CLK32K_EN | REQ_PHY_DPLL_CLK);
684 twl4030_usb_write(twl, PHY_CLK_CTRL, (u8)val);
685 }
686
687 /* disable complete OTG block */
688 twl4030_usb_clear_bits(twl, POWER_CTRL, POWER_CTRL_OTG_ENAB);
689
690 if (!twl->asleep)
691 twl4030_phy_power(twl, 0);
692 regulator_put(twl->usb1v5);
693 regulator_put(twl->usb1v8);
694 regulator_put(twl->usb3v1);
695
696 kfree(twl);
697
698 return 0;
699}
700
701static struct platform_driver twl4030_usb_driver = {
702 .probe = twl4030_usb_probe,
703 .remove = __exit_p(twl4030_usb_remove),
704 .driver = {
705 .name = "twl4030_usb",
706 .owner = THIS_MODULE,
707 },
708};
709
710static int __init twl4030_usb_init(void)
711{
712 return platform_driver_register(&twl4030_usb_driver);
713}
714subsys_initcall(twl4030_usb_init);
715
716static void __exit twl4030_usb_exit(void)
717{
718 platform_driver_unregister(&twl4030_usb_driver);
719}
720module_exit(twl4030_usb_exit);
721
722MODULE_ALIAS("platform:twl4030_usb");
723MODULE_AUTHOR("Texas Instruments, Inc, Nokia Corporation");
724MODULE_DESCRIPTION("TWL4030 USB transceiver driver");
725MODULE_LICENSE("GPL");