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1/*
2 * R8A66597 HCD (Host Controller Driver)
3 *
4 * Copyright (C) 2006-2007 Renesas Solutions Corp.
5 * Portions Copyright (C) 2004 Psion Teklogix (for NetBook PRO)
6 * Portions Copyright (C) 2004-2005 David Brownell
7 * Portions Copyright (C) 1999 Roman Weissgaerber
8 *
9 * Author : Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; version 2 of the License.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
23 *
24 */
25
26#ifndef __R8A66597_H__
27#define __R8A66597_H__
28
29#ifdef CONFIG_HAVE_CLK
30#include <linux/clk.h>
31#endif
32
33#include <linux/usb/r8a66597.h>
34
35#define R8A66597_MAX_NUM_PIPE 10
36#define R8A66597_BUF_BSIZE 8
37#define R8A66597_MAX_DEVICE 10
38#define R8A66597_MAX_ROOT_HUB 2
39#define R8A66597_MAX_SAMPLING 5
40#define R8A66597_RH_POLL_TIME 10
41#define R8A66597_MAX_DMA_CHANNEL 2
42#define R8A66597_PIPE_NO_DMA R8A66597_MAX_DMA_CHANNEL
43#define check_bulk_or_isoc(pipenum) ((pipenum >= 1 && pipenum <= 5))
44#define check_interrupt(pipenum) ((pipenum >= 6 && pipenum <= 9))
45#define make_devsel(addr) (addr << 12)
46
47struct r8a66597_pipe_info {
48 unsigned long timer_interval;
49 u16 pipenum;
50 u16 address; /* R8A66597 HCD usb address */
51 u16 epnum;
52 u16 maxpacket;
53 u16 type;
54 u16 bufnum;
55 u16 buf_bsize;
56 u16 interval;
57 u16 dir_in;
58};
59
60struct r8a66597_pipe {
61 struct r8a66597_pipe_info info;
62
63 unsigned long fifoaddr;
64 unsigned long fifosel;
65 unsigned long fifoctr;
66 unsigned long pipectr;
67 unsigned long pipetre;
68 unsigned long pipetrn;
69};
70
71struct r8a66597_td {
72 struct r8a66597_pipe *pipe;
73 struct urb *urb;
74 struct list_head queue;
75
76 u16 type;
77 u16 pipenum;
78 int iso_cnt;
79
80 u16 address; /* R8A66597's USB address */
81 u16 maxpacket;
82
83 unsigned zero_packet:1;
84 unsigned short_packet:1;
85 unsigned set_address:1;
86};
87
88struct r8a66597_device {
89 u16 address; /* R8A66597's USB address */
90 u16 hub_port;
91 u16 root_port;
92
93 unsigned short ep_in_toggle;
94 unsigned short ep_out_toggle;
95 unsigned char pipe_cnt[R8A66597_MAX_NUM_PIPE];
96 unsigned char dma_map;
97
98 enum usb_device_state state;
99
100 struct usb_device *udev;
101 int usb_address;
102 struct list_head device_list;
103};
104
105struct r8a66597_root_hub {
106 u32 port;
107 u16 old_syssts;
108 int scount;
109
110 struct r8a66597_device *dev;
111};
112
113struct r8a66597 {
114 spinlock_t lock;
115 void __iomem *reg;
116#ifdef CONFIG_HAVE_CLK
117 struct clk *clk;
118#endif
119 struct r8a66597_platdata *pdata;
120 struct r8a66597_device device0;
121 struct r8a66597_root_hub root_hub[R8A66597_MAX_ROOT_HUB];
122 struct list_head pipe_queue[R8A66597_MAX_NUM_PIPE];
123
124 struct timer_list rh_timer;
125 struct timer_list td_timer[R8A66597_MAX_NUM_PIPE];
126 struct timer_list interval_timer[R8A66597_MAX_NUM_PIPE];
127
128 unsigned short address_map;
129 unsigned short timeout_map;
130 unsigned short interval_map;
131 unsigned char pipe_cnt[R8A66597_MAX_NUM_PIPE];
132 unsigned char dma_map;
133 unsigned int max_root_hub;
134
135 struct list_head child_device;
136 unsigned long child_connect_map[4];
137
138 unsigned bus_suspended:1;
139 unsigned irq_sense_low:1;
140};
141
142static inline struct r8a66597 *hcd_to_r8a66597(struct usb_hcd *hcd)
143{
144 return (struct r8a66597 *)(hcd->hcd_priv);
145}
146
147static inline struct usb_hcd *r8a66597_to_hcd(struct r8a66597 *r8a66597)
148{
149 return container_of((void *)r8a66597, struct usb_hcd, hcd_priv);
150}
151
152static inline struct r8a66597_td *r8a66597_get_td(struct r8a66597 *r8a66597,
153 u16 pipenum)
154{
155 if (unlikely(list_empty(&r8a66597->pipe_queue[pipenum])))
156 return NULL;
157
158 return list_entry(r8a66597->pipe_queue[pipenum].next,
159 struct r8a66597_td, queue);
160}
161
162static inline struct urb *r8a66597_get_urb(struct r8a66597 *r8a66597,
163 u16 pipenum)
164{
165 struct r8a66597_td *td;
166
167 td = r8a66597_get_td(r8a66597, pipenum);
168 return (td ? td->urb : NULL);
169}
170
171static inline u16 r8a66597_read(struct r8a66597 *r8a66597, unsigned long offset)
172{
173 return ioread16(r8a66597->reg + offset);
174}
175
176static inline void r8a66597_read_fifo(struct r8a66597 *r8a66597,
177 unsigned long offset, u16 *buf,
178 int len)
179{
180 void __iomem *fifoaddr = r8a66597->reg + offset;
181 unsigned long count;
182
183 if (r8a66597->pdata->on_chip) {
184 count = len / 4;
185 ioread32_rep(fifoaddr, buf, count);
186
187 if (len & 0x00000003) {
188 unsigned long tmp = ioread32(fifoaddr);
189 memcpy((unsigned char *)buf + count * 4, &tmp,
190 len & 0x03);
191 }
192 } else {
193 len = (len + 1) / 2;
194 ioread16_rep(fifoaddr, buf, len);
195 }
196}
197
198static inline void r8a66597_write(struct r8a66597 *r8a66597, u16 val,
199 unsigned long offset)
200{
201 iowrite16(val, r8a66597->reg + offset);
202}
203
204static inline void r8a66597_mdfy(struct r8a66597 *r8a66597,
205 u16 val, u16 pat, unsigned long offset)
206{
207 u16 tmp;
208 tmp = r8a66597_read(r8a66597, offset);
209 tmp = tmp & (~pat);
210 tmp = tmp | val;
211 r8a66597_write(r8a66597, tmp, offset);
212}
213
214#define r8a66597_bclr(r8a66597, val, offset) \
215 r8a66597_mdfy(r8a66597, 0, val, offset)
216#define r8a66597_bset(r8a66597, val, offset) \
217 r8a66597_mdfy(r8a66597, val, 0, offset)
218
219static inline void r8a66597_write_fifo(struct r8a66597 *r8a66597,
220 struct r8a66597_pipe *pipe, u16 *buf,
221 int len)
222{
223 void __iomem *fifoaddr = r8a66597->reg + pipe->fifoaddr;
224 unsigned long count;
225 unsigned char *pb;
226 int i;
227
228 if (r8a66597->pdata->on_chip) {
229 count = len / 4;
230 iowrite32_rep(fifoaddr, buf, count);
231
232 if (len & 0x00000003) {
233 pb = (unsigned char *)buf + count * 4;
234 for (i = 0; i < (len & 0x00000003); i++) {
235 if (r8a66597_read(r8a66597, CFIFOSEL) & BIGEND)
236 iowrite8(pb[i], fifoaddr + i);
237 else
238 iowrite8(pb[i], fifoaddr + 3 - i);
239 }
240 }
241 } else {
242 int odd = len & 0x0001;
243
244 len = len / 2;
245 iowrite16_rep(fifoaddr, buf, len);
246 if (unlikely(odd)) {
247 buf = &buf[len];
248 if (r8a66597->pdata->wr0_shorted_to_wr1)
249 r8a66597_bclr(r8a66597, MBW_16, pipe->fifosel);
250 iowrite8((unsigned char)*buf, fifoaddr);
251 if (r8a66597->pdata->wr0_shorted_to_wr1)
252 r8a66597_bset(r8a66597, MBW_16, pipe->fifosel);
253 }
254 }
255}
256
257static inline unsigned long get_syscfg_reg(int port)
258{
259 return port == 0 ? SYSCFG0 : SYSCFG1;
260}
261
262static inline unsigned long get_syssts_reg(int port)
263{
264 return port == 0 ? SYSSTS0 : SYSSTS1;
265}
266
267static inline unsigned long get_dvstctr_reg(int port)
268{
269 return port == 0 ? DVSTCTR0 : DVSTCTR1;
270}
271
272static inline unsigned long get_dmacfg_reg(int port)
273{
274 return port == 0 ? DMA0CFG : DMA1CFG;
275}
276
277static inline unsigned long get_intenb_reg(int port)
278{
279 return port == 0 ? INTENB1 : INTENB2;
280}
281
282static inline unsigned long get_intsts_reg(int port)
283{
284 return port == 0 ? INTSTS1 : INTSTS2;
285}
286
287static inline u16 get_rh_usb_speed(struct r8a66597 *r8a66597, int port)
288{
289 unsigned long dvstctr_reg = get_dvstctr_reg(port);
290
291 return r8a66597_read(r8a66597, dvstctr_reg) & RHST;
292}
293
294static inline void r8a66597_port_power(struct r8a66597 *r8a66597, int port,
295 int power)
296{
297 unsigned long dvstctr_reg = get_dvstctr_reg(port);
298
299 if (r8a66597->pdata->port_power) {
300 r8a66597->pdata->port_power(port, power);
301 } else {
302 if (power)
303 r8a66597_bset(r8a66597, VBOUT, dvstctr_reg);
304 else
305 r8a66597_bclr(r8a66597, VBOUT, dvstctr_reg);
306 }
307}
308
309static inline u16 get_xtal_from_pdata(struct r8a66597_platdata *pdata)
310{
311 u16 clock = 0;
312
313 switch (pdata->xtal) {
314 case R8A66597_PLATDATA_XTAL_12MHZ:
315 clock = XTAL12;
316 break;
317 case R8A66597_PLATDATA_XTAL_24MHZ:
318 clock = XTAL24;
319 break;
320 case R8A66597_PLATDATA_XTAL_48MHZ:
321 clock = XTAL48;
322 break;
323 default:
324 printk(KERN_ERR "r8a66597: platdata clock is wrong.\n");
325 break;
326 }
327
328 return clock;
329}
330
331#define get_pipectr_addr(pipenum) (PIPE1CTR + (pipenum - 1) * 2)
332#define get_pipetre_addr(pipenum) (PIPE1TRE + (pipenum - 1) * 4)
333#define get_pipetrn_addr(pipenum) (PIPE1TRN + (pipenum - 1) * 4)
334#define get_devadd_addr(address) (DEVADD0 + address * 2)
335
336#define enable_irq_ready(r8a66597, pipenum) \
337 enable_pipe_irq(r8a66597, pipenum, BRDYENB)
338#define disable_irq_ready(r8a66597, pipenum) \
339 disable_pipe_irq(r8a66597, pipenum, BRDYENB)
340#define enable_irq_empty(r8a66597, pipenum) \
341 enable_pipe_irq(r8a66597, pipenum, BEMPENB)
342#define disable_irq_empty(r8a66597, pipenum) \
343 disable_pipe_irq(r8a66597, pipenum, BEMPENB)
344#define enable_irq_nrdy(r8a66597, pipenum) \
345 enable_pipe_irq(r8a66597, pipenum, NRDYENB)
346#define disable_irq_nrdy(r8a66597, pipenum) \
347 disable_pipe_irq(r8a66597, pipenum, NRDYENB)
348
349#endif /* __R8A66597_H__ */
350
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * R8A66597 HCD (Host Controller Driver)
4 *
5 * Copyright (C) 2006-2007 Renesas Solutions Corp.
6 * Portions Copyright (C) 2004 Psion Teklogix (for NetBook PRO)
7 * Portions Copyright (C) 2004-2005 David Brownell
8 * Portions Copyright (C) 1999 Roman Weissgaerber
9 *
10 * Author : Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
11 */
12
13#ifndef __R8A66597_H__
14#define __R8A66597_H__
15
16#include <linux/clk.h>
17#include <linux/usb/r8a66597.h>
18
19#define R8A66597_MAX_NUM_PIPE 10
20#define R8A66597_BUF_BSIZE 8
21#define R8A66597_MAX_DEVICE 10
22#define R8A66597_MAX_ROOT_HUB 2
23#define R8A66597_MAX_SAMPLING 5
24#define R8A66597_RH_POLL_TIME 10
25#define R8A66597_MAX_DMA_CHANNEL 2
26#define R8A66597_PIPE_NO_DMA R8A66597_MAX_DMA_CHANNEL
27#define check_bulk_or_isoc(pipenum) ((pipenum >= 1 && pipenum <= 5))
28#define check_interrupt(pipenum) ((pipenum >= 6 && pipenum <= 9))
29#define make_devsel(addr) (addr << 12)
30
31struct r8a66597_pipe_info {
32 unsigned long timer_interval;
33 u16 pipenum;
34 u16 address; /* R8A66597 HCD usb address */
35 u16 epnum;
36 u16 maxpacket;
37 u16 type;
38 u16 bufnum;
39 u16 buf_bsize;
40 u16 interval;
41 u16 dir_in;
42};
43
44struct r8a66597_pipe {
45 struct r8a66597_pipe_info info;
46
47 unsigned long fifoaddr;
48 unsigned long fifosel;
49 unsigned long fifoctr;
50 unsigned long pipectr;
51 unsigned long pipetre;
52 unsigned long pipetrn;
53};
54
55struct r8a66597_td {
56 struct r8a66597_pipe *pipe;
57 struct urb *urb;
58 struct list_head queue;
59
60 u16 type;
61 u16 pipenum;
62 int iso_cnt;
63
64 u16 address; /* R8A66597's USB address */
65 u16 maxpacket;
66
67 unsigned zero_packet:1;
68 unsigned short_packet:1;
69 unsigned set_address:1;
70};
71
72struct r8a66597_device {
73 u16 address; /* R8A66597's USB address */
74 u16 hub_port;
75 u16 root_port;
76
77 unsigned short ep_in_toggle;
78 unsigned short ep_out_toggle;
79 unsigned char pipe_cnt[R8A66597_MAX_NUM_PIPE];
80 unsigned char dma_map;
81
82 enum usb_device_state state;
83
84 struct usb_device *udev;
85 int usb_address;
86 struct list_head device_list;
87};
88
89struct r8a66597_root_hub {
90 u32 port;
91 u16 old_syssts;
92 int scount;
93
94 struct r8a66597_device *dev;
95};
96
97struct r8a66597;
98
99struct r8a66597_timers {
100 struct timer_list td;
101 struct timer_list interval;
102 struct r8a66597 *r8a66597;
103};
104
105struct r8a66597 {
106 spinlock_t lock;
107 void __iomem *reg;
108 struct clk *clk;
109 struct r8a66597_platdata *pdata;
110 struct r8a66597_device device0;
111 struct r8a66597_root_hub root_hub[R8A66597_MAX_ROOT_HUB];
112 struct list_head pipe_queue[R8A66597_MAX_NUM_PIPE];
113
114 struct timer_list rh_timer;
115 struct r8a66597_timers timers[R8A66597_MAX_NUM_PIPE];
116
117 unsigned short address_map;
118 unsigned short timeout_map;
119 unsigned short interval_map;
120 unsigned char pipe_cnt[R8A66597_MAX_NUM_PIPE];
121 unsigned char dma_map;
122 unsigned int max_root_hub;
123
124 struct list_head child_device;
125 unsigned long child_connect_map[4];
126
127 unsigned bus_suspended:1;
128 unsigned irq_sense_low:1;
129};
130
131static inline struct r8a66597 *hcd_to_r8a66597(struct usb_hcd *hcd)
132{
133 return (struct r8a66597 *)(hcd->hcd_priv);
134}
135
136static inline struct usb_hcd *r8a66597_to_hcd(struct r8a66597 *r8a66597)
137{
138 return container_of((void *)r8a66597, struct usb_hcd, hcd_priv);
139}
140
141static inline struct r8a66597_td *r8a66597_get_td(struct r8a66597 *r8a66597,
142 u16 pipenum)
143{
144 if (unlikely(list_empty(&r8a66597->pipe_queue[pipenum])))
145 return NULL;
146
147 return list_entry(r8a66597->pipe_queue[pipenum].next,
148 struct r8a66597_td, queue);
149}
150
151static inline struct urb *r8a66597_get_urb(struct r8a66597 *r8a66597,
152 u16 pipenum)
153{
154 struct r8a66597_td *td;
155
156 td = r8a66597_get_td(r8a66597, pipenum);
157 return (td ? td->urb : NULL);
158}
159
160static inline u16 r8a66597_read(struct r8a66597 *r8a66597, unsigned long offset)
161{
162 return ioread16(r8a66597->reg + offset);
163}
164
165static inline void r8a66597_read_fifo(struct r8a66597 *r8a66597,
166 unsigned long offset, u16 *buf,
167 int len)
168{
169 void __iomem *fifoaddr = r8a66597->reg + offset;
170 unsigned long count;
171
172 if (r8a66597->pdata->on_chip) {
173 count = len / 4;
174 ioread32_rep(fifoaddr, buf, count);
175
176 if (len & 0x00000003) {
177 unsigned long tmp = ioread32(fifoaddr);
178 memcpy((unsigned char *)buf + count * 4, &tmp,
179 len & 0x03);
180 }
181 } else {
182 len = (len + 1) / 2;
183 ioread16_rep(fifoaddr, buf, len);
184 }
185}
186
187static inline void r8a66597_write(struct r8a66597 *r8a66597, u16 val,
188 unsigned long offset)
189{
190 iowrite16(val, r8a66597->reg + offset);
191}
192
193static inline void r8a66597_mdfy(struct r8a66597 *r8a66597,
194 u16 val, u16 pat, unsigned long offset)
195{
196 u16 tmp;
197 tmp = r8a66597_read(r8a66597, offset);
198 tmp = tmp & (~pat);
199 tmp = tmp | val;
200 r8a66597_write(r8a66597, tmp, offset);
201}
202
203#define r8a66597_bclr(r8a66597, val, offset) \
204 r8a66597_mdfy(r8a66597, 0, val, offset)
205#define r8a66597_bset(r8a66597, val, offset) \
206 r8a66597_mdfy(r8a66597, val, 0, offset)
207
208static inline void r8a66597_write_fifo(struct r8a66597 *r8a66597,
209 struct r8a66597_pipe *pipe, u16 *buf,
210 int len)
211{
212 void __iomem *fifoaddr = r8a66597->reg + pipe->fifoaddr;
213 unsigned long count;
214 unsigned char *pb;
215 int i;
216
217 if (r8a66597->pdata->on_chip) {
218 count = len / 4;
219 iowrite32_rep(fifoaddr, buf, count);
220
221 if (len & 0x00000003) {
222 pb = (unsigned char *)buf + count * 4;
223 for (i = 0; i < (len & 0x00000003); i++) {
224 if (r8a66597_read(r8a66597, CFIFOSEL) & BIGEND)
225 iowrite8(pb[i], fifoaddr + i);
226 else
227 iowrite8(pb[i], fifoaddr + 3 - i);
228 }
229 }
230 } else {
231 int odd = len & 0x0001;
232
233 len = len / 2;
234 iowrite16_rep(fifoaddr, buf, len);
235 if (unlikely(odd)) {
236 buf = &buf[len];
237 if (r8a66597->pdata->wr0_shorted_to_wr1)
238 r8a66597_bclr(r8a66597, MBW_16, pipe->fifosel);
239 iowrite8((unsigned char)*buf, fifoaddr);
240 if (r8a66597->pdata->wr0_shorted_to_wr1)
241 r8a66597_bset(r8a66597, MBW_16, pipe->fifosel);
242 }
243 }
244}
245
246static inline unsigned long get_syscfg_reg(int port)
247{
248 return port == 0 ? SYSCFG0 : SYSCFG1;
249}
250
251static inline unsigned long get_syssts_reg(int port)
252{
253 return port == 0 ? SYSSTS0 : SYSSTS1;
254}
255
256static inline unsigned long get_dvstctr_reg(int port)
257{
258 return port == 0 ? DVSTCTR0 : DVSTCTR1;
259}
260
261static inline unsigned long get_dmacfg_reg(int port)
262{
263 return port == 0 ? DMA0CFG : DMA1CFG;
264}
265
266static inline unsigned long get_intenb_reg(int port)
267{
268 return port == 0 ? INTENB1 : INTENB2;
269}
270
271static inline unsigned long get_intsts_reg(int port)
272{
273 return port == 0 ? INTSTS1 : INTSTS2;
274}
275
276static inline u16 get_rh_usb_speed(struct r8a66597 *r8a66597, int port)
277{
278 unsigned long dvstctr_reg = get_dvstctr_reg(port);
279
280 return r8a66597_read(r8a66597, dvstctr_reg) & RHST;
281}
282
283static inline void r8a66597_port_power(struct r8a66597 *r8a66597, int port,
284 int power)
285{
286 unsigned long dvstctr_reg = get_dvstctr_reg(port);
287
288 if (r8a66597->pdata->port_power) {
289 r8a66597->pdata->port_power(port, power);
290 } else {
291 if (power)
292 r8a66597_bset(r8a66597, VBOUT, dvstctr_reg);
293 else
294 r8a66597_bclr(r8a66597, VBOUT, dvstctr_reg);
295 }
296}
297
298static inline u16 get_xtal_from_pdata(struct r8a66597_platdata *pdata)
299{
300 u16 clock = 0;
301
302 switch (pdata->xtal) {
303 case R8A66597_PLATDATA_XTAL_12MHZ:
304 clock = XTAL12;
305 break;
306 case R8A66597_PLATDATA_XTAL_24MHZ:
307 clock = XTAL24;
308 break;
309 case R8A66597_PLATDATA_XTAL_48MHZ:
310 clock = XTAL48;
311 break;
312 default:
313 printk(KERN_ERR "r8a66597: platdata clock is wrong.\n");
314 break;
315 }
316
317 return clock;
318}
319
320#define get_pipectr_addr(pipenum) (PIPE1CTR + (pipenum - 1) * 2)
321#define get_pipetre_addr(pipenum) (PIPE1TRE + (pipenum - 1) * 4)
322#define get_pipetrn_addr(pipenum) (PIPE1TRN + (pipenum - 1) * 4)
323#define get_devadd_addr(address) (DEVADD0 + address * 2)
324
325#define enable_irq_ready(r8a66597, pipenum) \
326 enable_pipe_irq(r8a66597, pipenum, BRDYENB)
327#define disable_irq_ready(r8a66597, pipenum) \
328 disable_pipe_irq(r8a66597, pipenum, BRDYENB)
329#define enable_irq_empty(r8a66597, pipenum) \
330 enable_pipe_irq(r8a66597, pipenum, BEMPENB)
331#define disable_irq_empty(r8a66597, pipenum) \
332 disable_pipe_irq(r8a66597, pipenum, BEMPENB)
333#define enable_irq_nrdy(r8a66597, pipenum) \
334 enable_pipe_irq(r8a66597, pipenum, NRDYENB)
335#define disable_irq_nrdy(r8a66597, pipenum) \
336 disable_pipe_irq(r8a66597, pipenum, NRDYENB)
337
338#endif /* __R8A66597_H__ */
339