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1/*
2 * Driver for CLPS711x serial ports
3 *
4 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
5 *
6 * Copyright 1999 ARM Limited
7 * Copyright (C) 2000 Deep Blue Solutions Ltd.
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22 */
23
24#if defined(CONFIG_SERIAL_CLPS711X_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
25#define SUPPORT_SYSRQ
26#endif
27
28#include <linux/module.h>
29#include <linux/ioport.h>
30#include <linux/init.h>
31#include <linux/console.h>
32#include <linux/sysrq.h>
33#include <linux/spinlock.h>
34#include <linux/device.h>
35#include <linux/tty.h>
36#include <linux/tty_flip.h>
37#include <linux/serial_core.h>
38#include <linux/serial.h>
39#include <linux/io.h>
40
41#include <mach/hardware.h>
42#include <asm/irq.h>
43#include <asm/hardware/clps7111.h>
44
45#define UART_NR 2
46
47#define SERIAL_CLPS711X_MAJOR 204
48#define SERIAL_CLPS711X_MINOR 40
49#define SERIAL_CLPS711X_NR UART_NR
50
51/*
52 * We use the relevant SYSCON register as a base address for these ports.
53 */
54#define UBRLCR(port) ((port)->iobase + UBRLCR1 - SYSCON1)
55#define UARTDR(port) ((port)->iobase + UARTDR1 - SYSCON1)
56#define SYSFLG(port) ((port)->iobase + SYSFLG1 - SYSCON1)
57#define SYSCON(port) ((port)->iobase + SYSCON1 - SYSCON1)
58
59#define TX_IRQ(port) ((port)->irq)
60#define RX_IRQ(port) ((port)->irq + 1)
61
62#define UART_ANY_ERR (UARTDR_FRMERR | UARTDR_PARERR | UARTDR_OVERR)
63
64#define tx_enabled(port) ((port)->unused[0])
65
66static void clps711xuart_stop_tx(struct uart_port *port)
67{
68 if (tx_enabled(port)) {
69 disable_irq(TX_IRQ(port));
70 tx_enabled(port) = 0;
71 }
72}
73
74static void clps711xuart_start_tx(struct uart_port *port)
75{
76 if (!tx_enabled(port)) {
77 enable_irq(TX_IRQ(port));
78 tx_enabled(port) = 1;
79 }
80}
81
82static void clps711xuart_stop_rx(struct uart_port *port)
83{
84 disable_irq(RX_IRQ(port));
85}
86
87static void clps711xuart_enable_ms(struct uart_port *port)
88{
89}
90
91static irqreturn_t clps711xuart_int_rx(int irq, void *dev_id)
92{
93 struct uart_port *port = dev_id;
94 struct tty_struct *tty = port->state->port.tty;
95 unsigned int status, ch, flg;
96
97 status = clps_readl(SYSFLG(port));
98 while (!(status & SYSFLG_URXFE)) {
99 ch = clps_readl(UARTDR(port));
100
101 port->icount.rx++;
102
103 flg = TTY_NORMAL;
104
105 /*
106 * Note that the error handling code is
107 * out of the main execution path
108 */
109 if (unlikely(ch & UART_ANY_ERR)) {
110 if (ch & UARTDR_PARERR)
111 port->icount.parity++;
112 else if (ch & UARTDR_FRMERR)
113 port->icount.frame++;
114 if (ch & UARTDR_OVERR)
115 port->icount.overrun++;
116
117 ch &= port->read_status_mask;
118
119 if (ch & UARTDR_PARERR)
120 flg = TTY_PARITY;
121 else if (ch & UARTDR_FRMERR)
122 flg = TTY_FRAME;
123
124#ifdef SUPPORT_SYSRQ
125 port->sysrq = 0;
126#endif
127 }
128
129 if (uart_handle_sysrq_char(port, ch))
130 goto ignore_char;
131
132 /*
133 * CHECK: does overrun affect the current character?
134 * ASSUMPTION: it does not.
135 */
136 uart_insert_char(port, ch, UARTDR_OVERR, ch, flg);
137
138 ignore_char:
139 status = clps_readl(SYSFLG(port));
140 }
141 tty_flip_buffer_push(tty);
142 return IRQ_HANDLED;
143}
144
145static irqreturn_t clps711xuart_int_tx(int irq, void *dev_id)
146{
147 struct uart_port *port = dev_id;
148 struct circ_buf *xmit = &port->state->xmit;
149 int count;
150
151 if (port->x_char) {
152 clps_writel(port->x_char, UARTDR(port));
153 port->icount.tx++;
154 port->x_char = 0;
155 return IRQ_HANDLED;
156 }
157 if (uart_circ_empty(xmit) || uart_tx_stopped(port)) {
158 clps711xuart_stop_tx(port);
159 return IRQ_HANDLED;
160 }
161
162 count = port->fifosize >> 1;
163 do {
164 clps_writel(xmit->buf[xmit->tail], UARTDR(port));
165 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
166 port->icount.tx++;
167 if (uart_circ_empty(xmit))
168 break;
169 } while (--count > 0);
170
171 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
172 uart_write_wakeup(port);
173
174 if (uart_circ_empty(xmit))
175 clps711xuart_stop_tx(port);
176
177 return IRQ_HANDLED;
178}
179
180static unsigned int clps711xuart_tx_empty(struct uart_port *port)
181{
182 unsigned int status = clps_readl(SYSFLG(port));
183 return status & SYSFLG_UBUSY ? 0 : TIOCSER_TEMT;
184}
185
186static unsigned int clps711xuart_get_mctrl(struct uart_port *port)
187{
188 unsigned int port_addr;
189 unsigned int result = 0;
190 unsigned int status;
191
192 port_addr = SYSFLG(port);
193 if (port_addr == SYSFLG1) {
194 status = clps_readl(SYSFLG1);
195 if (status & SYSFLG1_DCD)
196 result |= TIOCM_CAR;
197 if (status & SYSFLG1_DSR)
198 result |= TIOCM_DSR;
199 if (status & SYSFLG1_CTS)
200 result |= TIOCM_CTS;
201 }
202
203 return result;
204}
205
206static void
207clps711xuart_set_mctrl_null(struct uart_port *port, unsigned int mctrl)
208{
209}
210
211static void clps711xuart_break_ctl(struct uart_port *port, int break_state)
212{
213 unsigned long flags;
214 unsigned int ubrlcr;
215
216 spin_lock_irqsave(&port->lock, flags);
217 ubrlcr = clps_readl(UBRLCR(port));
218 if (break_state == -1)
219 ubrlcr |= UBRLCR_BREAK;
220 else
221 ubrlcr &= ~UBRLCR_BREAK;
222 clps_writel(ubrlcr, UBRLCR(port));
223 spin_unlock_irqrestore(&port->lock, flags);
224}
225
226static int clps711xuart_startup(struct uart_port *port)
227{
228 unsigned int syscon;
229 int retval;
230
231 tx_enabled(port) = 1;
232
233 /*
234 * Allocate the IRQs
235 */
236 retval = request_irq(TX_IRQ(port), clps711xuart_int_tx, 0,
237 "clps711xuart_tx", port);
238 if (retval)
239 return retval;
240
241 retval = request_irq(RX_IRQ(port), clps711xuart_int_rx, 0,
242 "clps711xuart_rx", port);
243 if (retval) {
244 free_irq(TX_IRQ(port), port);
245 return retval;
246 }
247
248 /*
249 * enable the port
250 */
251 syscon = clps_readl(SYSCON(port));
252 syscon |= SYSCON_UARTEN;
253 clps_writel(syscon, SYSCON(port));
254
255 return 0;
256}
257
258static void clps711xuart_shutdown(struct uart_port *port)
259{
260 unsigned int ubrlcr, syscon;
261
262 /*
263 * Free the interrupt
264 */
265 free_irq(TX_IRQ(port), port); /* TX interrupt */
266 free_irq(RX_IRQ(port), port); /* RX interrupt */
267
268 /*
269 * disable the port
270 */
271 syscon = clps_readl(SYSCON(port));
272 syscon &= ~SYSCON_UARTEN;
273 clps_writel(syscon, SYSCON(port));
274
275 /*
276 * disable break condition and fifos
277 */
278 ubrlcr = clps_readl(UBRLCR(port));
279 ubrlcr &= ~(UBRLCR_FIFOEN | UBRLCR_BREAK);
280 clps_writel(ubrlcr, UBRLCR(port));
281}
282
283static void
284clps711xuart_set_termios(struct uart_port *port, struct ktermios *termios,
285 struct ktermios *old)
286{
287 unsigned int ubrlcr, baud, quot;
288 unsigned long flags;
289
290 /*
291 * We don't implement CREAD.
292 */
293 termios->c_cflag |= CREAD;
294
295 /*
296 * Ask the core to calculate the divisor for us.
297 */
298 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/16);
299 quot = uart_get_divisor(port, baud);
300
301 switch (termios->c_cflag & CSIZE) {
302 case CS5:
303 ubrlcr = UBRLCR_WRDLEN5;
304 break;
305 case CS6:
306 ubrlcr = UBRLCR_WRDLEN6;
307 break;
308 case CS7:
309 ubrlcr = UBRLCR_WRDLEN7;
310 break;
311 default: // CS8
312 ubrlcr = UBRLCR_WRDLEN8;
313 break;
314 }
315 if (termios->c_cflag & CSTOPB)
316 ubrlcr |= UBRLCR_XSTOP;
317 if (termios->c_cflag & PARENB) {
318 ubrlcr |= UBRLCR_PRTEN;
319 if (!(termios->c_cflag & PARODD))
320 ubrlcr |= UBRLCR_EVENPRT;
321 }
322 if (port->fifosize > 1)
323 ubrlcr |= UBRLCR_FIFOEN;
324
325 spin_lock_irqsave(&port->lock, flags);
326
327 /*
328 * Update the per-port timeout.
329 */
330 uart_update_timeout(port, termios->c_cflag, baud);
331
332 port->read_status_mask = UARTDR_OVERR;
333 if (termios->c_iflag & INPCK)
334 port->read_status_mask |= UARTDR_PARERR | UARTDR_FRMERR;
335
336 /*
337 * Characters to ignore
338 */
339 port->ignore_status_mask = 0;
340 if (termios->c_iflag & IGNPAR)
341 port->ignore_status_mask |= UARTDR_FRMERR | UARTDR_PARERR;
342 if (termios->c_iflag & IGNBRK) {
343 /*
344 * If we're ignoring parity and break indicators,
345 * ignore overruns to (for real raw support).
346 */
347 if (termios->c_iflag & IGNPAR)
348 port->ignore_status_mask |= UARTDR_OVERR;
349 }
350
351 quot -= 1;
352
353 clps_writel(ubrlcr | quot, UBRLCR(port));
354
355 spin_unlock_irqrestore(&port->lock, flags);
356}
357
358static const char *clps711xuart_type(struct uart_port *port)
359{
360 return port->type == PORT_CLPS711X ? "CLPS711x" : NULL;
361}
362
363/*
364 * Configure/autoconfigure the port.
365 */
366static void clps711xuart_config_port(struct uart_port *port, int flags)
367{
368 if (flags & UART_CONFIG_TYPE)
369 port->type = PORT_CLPS711X;
370}
371
372static void clps711xuart_release_port(struct uart_port *port)
373{
374}
375
376static int clps711xuart_request_port(struct uart_port *port)
377{
378 return 0;
379}
380
381static struct uart_ops clps711x_pops = {
382 .tx_empty = clps711xuart_tx_empty,
383 .set_mctrl = clps711xuart_set_mctrl_null,
384 .get_mctrl = clps711xuart_get_mctrl,
385 .stop_tx = clps711xuart_stop_tx,
386 .start_tx = clps711xuart_start_tx,
387 .stop_rx = clps711xuart_stop_rx,
388 .enable_ms = clps711xuart_enable_ms,
389 .break_ctl = clps711xuart_break_ctl,
390 .startup = clps711xuart_startup,
391 .shutdown = clps711xuart_shutdown,
392 .set_termios = clps711xuart_set_termios,
393 .type = clps711xuart_type,
394 .config_port = clps711xuart_config_port,
395 .release_port = clps711xuart_release_port,
396 .request_port = clps711xuart_request_port,
397};
398
399static struct uart_port clps711x_ports[UART_NR] = {
400 {
401 .iobase = SYSCON1,
402 .irq = IRQ_UTXINT1, /* IRQ_URXINT1, IRQ_UMSINT */
403 .uartclk = 3686400,
404 .fifosize = 16,
405 .ops = &clps711x_pops,
406 .line = 0,
407 .flags = UPF_BOOT_AUTOCONF,
408 },
409 {
410 .iobase = SYSCON2,
411 .irq = IRQ_UTXINT2, /* IRQ_URXINT2 */
412 .uartclk = 3686400,
413 .fifosize = 16,
414 .ops = &clps711x_pops,
415 .line = 1,
416 .flags = UPF_BOOT_AUTOCONF,
417 }
418};
419
420#ifdef CONFIG_SERIAL_CLPS711X_CONSOLE
421static void clps711xuart_console_putchar(struct uart_port *port, int ch)
422{
423 while (clps_readl(SYSFLG(port)) & SYSFLG_UTXFF)
424 barrier();
425 clps_writel(ch, UARTDR(port));
426}
427
428/*
429 * Print a string to the serial port trying not to disturb
430 * any possible real use of the port...
431 *
432 * The console_lock must be held when we get here.
433 *
434 * Note that this is called with interrupts already disabled
435 */
436static void
437clps711xuart_console_write(struct console *co, const char *s,
438 unsigned int count)
439{
440 struct uart_port *port = clps711x_ports + co->index;
441 unsigned int status, syscon;
442
443 /*
444 * Ensure that the port is enabled.
445 */
446 syscon = clps_readl(SYSCON(port));
447 clps_writel(syscon | SYSCON_UARTEN, SYSCON(port));
448
449 uart_console_write(port, s, count, clps711xuart_console_putchar);
450
451 /*
452 * Finally, wait for transmitter to become empty
453 * and restore the uart state.
454 */
455 do {
456 status = clps_readl(SYSFLG(port));
457 } while (status & SYSFLG_UBUSY);
458
459 clps_writel(syscon, SYSCON(port));
460}
461
462static void __init
463clps711xuart_console_get_options(struct uart_port *port, int *baud,
464 int *parity, int *bits)
465{
466 if (clps_readl(SYSCON(port)) & SYSCON_UARTEN) {
467 unsigned int ubrlcr, quot;
468
469 ubrlcr = clps_readl(UBRLCR(port));
470
471 *parity = 'n';
472 if (ubrlcr & UBRLCR_PRTEN) {
473 if (ubrlcr & UBRLCR_EVENPRT)
474 *parity = 'e';
475 else
476 *parity = 'o';
477 }
478
479 if ((ubrlcr & UBRLCR_WRDLEN_MASK) == UBRLCR_WRDLEN7)
480 *bits = 7;
481 else
482 *bits = 8;
483
484 quot = ubrlcr & UBRLCR_BAUD_MASK;
485 *baud = port->uartclk / (16 * (quot + 1));
486 }
487}
488
489static int __init clps711xuart_console_setup(struct console *co, char *options)
490{
491 struct uart_port *port;
492 int baud = 38400;
493 int bits = 8;
494 int parity = 'n';
495 int flow = 'n';
496
497 /*
498 * Check whether an invalid uart number has been specified, and
499 * if so, search for the first available port that does have
500 * console support.
501 */
502 port = uart_get_console(clps711x_ports, UART_NR, co);
503
504 if (options)
505 uart_parse_options(options, &baud, &parity, &bits, &flow);
506 else
507 clps711xuart_console_get_options(port, &baud, &parity, &bits);
508
509 return uart_set_options(port, co, baud, parity, bits, flow);
510}
511
512static struct uart_driver clps711x_reg;
513static struct console clps711x_console = {
514 .name = "ttyCL",
515 .write = clps711xuart_console_write,
516 .device = uart_console_device,
517 .setup = clps711xuart_console_setup,
518 .flags = CON_PRINTBUFFER,
519 .index = -1,
520 .data = &clps711x_reg,
521};
522
523static int __init clps711xuart_console_init(void)
524{
525 register_console(&clps711x_console);
526 return 0;
527}
528console_initcall(clps711xuart_console_init);
529
530#define CLPS711X_CONSOLE &clps711x_console
531#else
532#define CLPS711X_CONSOLE NULL
533#endif
534
535static struct uart_driver clps711x_reg = {
536 .driver_name = "ttyCL",
537 .dev_name = "ttyCL",
538 .major = SERIAL_CLPS711X_MAJOR,
539 .minor = SERIAL_CLPS711X_MINOR,
540 .nr = UART_NR,
541
542 .cons = CLPS711X_CONSOLE,
543};
544
545static int __init clps711xuart_init(void)
546{
547 int ret, i;
548
549 printk(KERN_INFO "Serial: CLPS711x driver\n");
550
551 ret = uart_register_driver(&clps711x_reg);
552 if (ret)
553 return ret;
554
555 for (i = 0; i < UART_NR; i++)
556 uart_add_one_port(&clps711x_reg, &clps711x_ports[i]);
557
558 return 0;
559}
560
561static void __exit clps711xuart_exit(void)
562{
563 int i;
564
565 for (i = 0; i < UART_NR; i++)
566 uart_remove_one_port(&clps711x_reg, &clps711x_ports[i]);
567
568 uart_unregister_driver(&clps711x_reg);
569}
570
571module_init(clps711xuart_init);
572module_exit(clps711xuart_exit);
573
574MODULE_AUTHOR("Deep Blue Solutions Ltd");
575MODULE_DESCRIPTION("CLPS-711x generic serial driver");
576MODULE_LICENSE("GPL");
577MODULE_ALIAS_CHARDEV(SERIAL_CLPS711X_MAJOR, SERIAL_CLPS711X_MINOR);
1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Driver for CLPS711x serial ports
4 *
5 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
6 *
7 * Copyright 1999 ARM Limited
8 * Copyright (C) 2000 Deep Blue Solutions Ltd.
9 */
10
11#if defined(CONFIG_SERIAL_CLPS711X_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
12#define SUPPORT_SYSRQ
13#endif
14
15#include <linux/module.h>
16#include <linux/device.h>
17#include <linux/console.h>
18#include <linux/serial_core.h>
19#include <linux/serial.h>
20#include <linux/clk.h>
21#include <linux/io.h>
22#include <linux/tty.h>
23#include <linux/tty_flip.h>
24#include <linux/ioport.h>
25#include <linux/of.h>
26#include <linux/platform_device.h>
27#include <linux/regmap.h>
28
29#include <linux/mfd/syscon.h>
30#include <linux/mfd/syscon/clps711x.h>
31
32#include "serial_mctrl_gpio.h"
33
34#define UART_CLPS711X_DEVNAME "ttyCL"
35#define UART_CLPS711X_NR 2
36#define UART_CLPS711X_MAJOR 204
37#define UART_CLPS711X_MINOR 40
38
39#define UARTDR_OFFSET (0x00)
40#define UBRLCR_OFFSET (0x40)
41
42#define UARTDR_FRMERR (1 << 8)
43#define UARTDR_PARERR (1 << 9)
44#define UARTDR_OVERR (1 << 10)
45
46#define UBRLCR_BAUD_MASK ((1 << 12) - 1)
47#define UBRLCR_BREAK (1 << 12)
48#define UBRLCR_PRTEN (1 << 13)
49#define UBRLCR_EVENPRT (1 << 14)
50#define UBRLCR_XSTOP (1 << 15)
51#define UBRLCR_FIFOEN (1 << 16)
52#define UBRLCR_WRDLEN5 (0 << 17)
53#define UBRLCR_WRDLEN6 (1 << 17)
54#define UBRLCR_WRDLEN7 (2 << 17)
55#define UBRLCR_WRDLEN8 (3 << 17)
56#define UBRLCR_WRDLEN_MASK (3 << 17)
57
58struct clps711x_port {
59 struct uart_port port;
60 unsigned int tx_enabled;
61 int rx_irq;
62 struct regmap *syscon;
63 struct mctrl_gpios *gpios;
64};
65
66static struct uart_driver clps711x_uart = {
67 .owner = THIS_MODULE,
68 .driver_name = UART_CLPS711X_DEVNAME,
69 .dev_name = UART_CLPS711X_DEVNAME,
70 .major = UART_CLPS711X_MAJOR,
71 .minor = UART_CLPS711X_MINOR,
72 .nr = UART_CLPS711X_NR,
73};
74
75static void uart_clps711x_stop_tx(struct uart_port *port)
76{
77 struct clps711x_port *s = dev_get_drvdata(port->dev);
78
79 if (s->tx_enabled) {
80 disable_irq(port->irq);
81 s->tx_enabled = 0;
82 }
83}
84
85static void uart_clps711x_start_tx(struct uart_port *port)
86{
87 struct clps711x_port *s = dev_get_drvdata(port->dev);
88
89 if (!s->tx_enabled) {
90 s->tx_enabled = 1;
91 enable_irq(port->irq);
92 }
93}
94
95static irqreturn_t uart_clps711x_int_rx(int irq, void *dev_id)
96{
97 struct uart_port *port = dev_id;
98 struct clps711x_port *s = dev_get_drvdata(port->dev);
99 unsigned int status, flg;
100 u16 ch;
101
102 for (;;) {
103 u32 sysflg = 0;
104
105 regmap_read(s->syscon, SYSFLG_OFFSET, &sysflg);
106 if (sysflg & SYSFLG_URXFE)
107 break;
108
109 ch = readw(port->membase + UARTDR_OFFSET);
110 status = ch & (UARTDR_FRMERR | UARTDR_PARERR | UARTDR_OVERR);
111 ch &= 0xff;
112
113 port->icount.rx++;
114 flg = TTY_NORMAL;
115
116 if (unlikely(status)) {
117 if (status & UARTDR_PARERR)
118 port->icount.parity++;
119 else if (status & UARTDR_FRMERR)
120 port->icount.frame++;
121 else if (status & UARTDR_OVERR)
122 port->icount.overrun++;
123
124 status &= port->read_status_mask;
125
126 if (status & UARTDR_PARERR)
127 flg = TTY_PARITY;
128 else if (status & UARTDR_FRMERR)
129 flg = TTY_FRAME;
130 else if (status & UARTDR_OVERR)
131 flg = TTY_OVERRUN;
132 }
133
134 if (uart_handle_sysrq_char(port, ch))
135 continue;
136
137 if (status & port->ignore_status_mask)
138 continue;
139
140 uart_insert_char(port, status, UARTDR_OVERR, ch, flg);
141 }
142
143 tty_flip_buffer_push(&port->state->port);
144
145 return IRQ_HANDLED;
146}
147
148static irqreturn_t uart_clps711x_int_tx(int irq, void *dev_id)
149{
150 struct uart_port *port = dev_id;
151 struct clps711x_port *s = dev_get_drvdata(port->dev);
152 struct circ_buf *xmit = &port->state->xmit;
153
154 if (port->x_char) {
155 writew(port->x_char, port->membase + UARTDR_OFFSET);
156 port->icount.tx++;
157 port->x_char = 0;
158 return IRQ_HANDLED;
159 }
160
161 if (uart_circ_empty(xmit) || uart_tx_stopped(port)) {
162 if (s->tx_enabled) {
163 disable_irq_nosync(port->irq);
164 s->tx_enabled = 0;
165 }
166 return IRQ_HANDLED;
167 }
168
169 while (!uart_circ_empty(xmit)) {
170 u32 sysflg = 0;
171
172 writew(xmit->buf[xmit->tail], port->membase + UARTDR_OFFSET);
173 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
174 port->icount.tx++;
175
176 regmap_read(s->syscon, SYSFLG_OFFSET, &sysflg);
177 if (sysflg & SYSFLG_UTXFF)
178 break;
179 }
180
181 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
182 uart_write_wakeup(port);
183
184 return IRQ_HANDLED;
185}
186
187static unsigned int uart_clps711x_tx_empty(struct uart_port *port)
188{
189 struct clps711x_port *s = dev_get_drvdata(port->dev);
190 u32 sysflg = 0;
191
192 regmap_read(s->syscon, SYSFLG_OFFSET, &sysflg);
193
194 return (sysflg & SYSFLG_UBUSY) ? 0 : TIOCSER_TEMT;
195}
196
197static unsigned int uart_clps711x_get_mctrl(struct uart_port *port)
198{
199 unsigned int result = TIOCM_DSR | TIOCM_CTS | TIOCM_CAR;
200 struct clps711x_port *s = dev_get_drvdata(port->dev);
201
202 return mctrl_gpio_get(s->gpios, &result);
203}
204
205static void uart_clps711x_set_mctrl(struct uart_port *port, unsigned int mctrl)
206{
207 struct clps711x_port *s = dev_get_drvdata(port->dev);
208
209 mctrl_gpio_set(s->gpios, mctrl);
210}
211
212static void uart_clps711x_break_ctl(struct uart_port *port, int break_state)
213{
214 unsigned int ubrlcr;
215
216 ubrlcr = readl(port->membase + UBRLCR_OFFSET);
217 if (break_state)
218 ubrlcr |= UBRLCR_BREAK;
219 else
220 ubrlcr &= ~UBRLCR_BREAK;
221 writel(ubrlcr, port->membase + UBRLCR_OFFSET);
222}
223
224static void uart_clps711x_set_ldisc(struct uart_port *port,
225 struct ktermios *termios)
226{
227 if (!port->line) {
228 struct clps711x_port *s = dev_get_drvdata(port->dev);
229
230 regmap_update_bits(s->syscon, SYSCON_OFFSET, SYSCON1_SIREN,
231 (termios->c_line == N_IRDA) ? SYSCON1_SIREN : 0);
232 }
233}
234
235static int uart_clps711x_startup(struct uart_port *port)
236{
237 struct clps711x_port *s = dev_get_drvdata(port->dev);
238
239 /* Disable break */
240 writel(readl(port->membase + UBRLCR_OFFSET) & ~UBRLCR_BREAK,
241 port->membase + UBRLCR_OFFSET);
242
243 /* Enable the port */
244 return regmap_update_bits(s->syscon, SYSCON_OFFSET,
245 SYSCON_UARTEN, SYSCON_UARTEN);
246}
247
248static void uart_clps711x_shutdown(struct uart_port *port)
249{
250 struct clps711x_port *s = dev_get_drvdata(port->dev);
251
252 /* Disable the port */
253 regmap_update_bits(s->syscon, SYSCON_OFFSET, SYSCON_UARTEN, 0);
254}
255
256static void uart_clps711x_set_termios(struct uart_port *port,
257 struct ktermios *termios,
258 struct ktermios *old)
259{
260 u32 ubrlcr;
261 unsigned int baud, quot;
262
263 /* Mask termios capabilities we don't support */
264 termios->c_cflag &= ~CMSPAR;
265 termios->c_iflag &= ~(BRKINT | IGNBRK);
266
267 /* Ask the core to calculate the divisor for us */
268 baud = uart_get_baud_rate(port, termios, old, port->uartclk / 4096,
269 port->uartclk / 16);
270 quot = uart_get_divisor(port, baud);
271
272 switch (termios->c_cflag & CSIZE) {
273 case CS5:
274 ubrlcr = UBRLCR_WRDLEN5;
275 break;
276 case CS6:
277 ubrlcr = UBRLCR_WRDLEN6;
278 break;
279 case CS7:
280 ubrlcr = UBRLCR_WRDLEN7;
281 break;
282 case CS8:
283 default:
284 ubrlcr = UBRLCR_WRDLEN8;
285 break;
286 }
287
288 if (termios->c_cflag & CSTOPB)
289 ubrlcr |= UBRLCR_XSTOP;
290
291 if (termios->c_cflag & PARENB) {
292 ubrlcr |= UBRLCR_PRTEN;
293 if (!(termios->c_cflag & PARODD))
294 ubrlcr |= UBRLCR_EVENPRT;
295 }
296
297 /* Enable FIFO */
298 ubrlcr |= UBRLCR_FIFOEN;
299
300 /* Set read status mask */
301 port->read_status_mask = UARTDR_OVERR;
302 if (termios->c_iflag & INPCK)
303 port->read_status_mask |= UARTDR_PARERR | UARTDR_FRMERR;
304
305 /* Set status ignore mask */
306 port->ignore_status_mask = 0;
307 if (!(termios->c_cflag & CREAD))
308 port->ignore_status_mask |= UARTDR_OVERR | UARTDR_PARERR |
309 UARTDR_FRMERR;
310
311 uart_update_timeout(port, termios->c_cflag, baud);
312
313 writel(ubrlcr | (quot - 1), port->membase + UBRLCR_OFFSET);
314}
315
316static const char *uart_clps711x_type(struct uart_port *port)
317{
318 return (port->type == PORT_CLPS711X) ? "CLPS711X" : NULL;
319}
320
321static void uart_clps711x_config_port(struct uart_port *port, int flags)
322{
323 if (flags & UART_CONFIG_TYPE)
324 port->type = PORT_CLPS711X;
325}
326
327static void uart_clps711x_nop_void(struct uart_port *port)
328{
329}
330
331static int uart_clps711x_nop_int(struct uart_port *port)
332{
333 return 0;
334}
335
336static const struct uart_ops uart_clps711x_ops = {
337 .tx_empty = uart_clps711x_tx_empty,
338 .set_mctrl = uart_clps711x_set_mctrl,
339 .get_mctrl = uart_clps711x_get_mctrl,
340 .stop_tx = uart_clps711x_stop_tx,
341 .start_tx = uart_clps711x_start_tx,
342 .stop_rx = uart_clps711x_nop_void,
343 .break_ctl = uart_clps711x_break_ctl,
344 .set_ldisc = uart_clps711x_set_ldisc,
345 .startup = uart_clps711x_startup,
346 .shutdown = uart_clps711x_shutdown,
347 .set_termios = uart_clps711x_set_termios,
348 .type = uart_clps711x_type,
349 .config_port = uart_clps711x_config_port,
350 .release_port = uart_clps711x_nop_void,
351 .request_port = uart_clps711x_nop_int,
352};
353
354#ifdef CONFIG_SERIAL_CLPS711X_CONSOLE
355static void uart_clps711x_console_putchar(struct uart_port *port, int ch)
356{
357 struct clps711x_port *s = dev_get_drvdata(port->dev);
358 u32 sysflg = 0;
359
360 /* Wait for FIFO is not full */
361 do {
362 regmap_read(s->syscon, SYSFLG_OFFSET, &sysflg);
363 } while (sysflg & SYSFLG_UTXFF);
364
365 writew(ch, port->membase + UARTDR_OFFSET);
366}
367
368static void uart_clps711x_console_write(struct console *co, const char *c,
369 unsigned n)
370{
371 struct uart_port *port = clps711x_uart.state[co->index].uart_port;
372 struct clps711x_port *s = dev_get_drvdata(port->dev);
373 u32 sysflg = 0;
374
375 uart_console_write(port, c, n, uart_clps711x_console_putchar);
376
377 /* Wait for transmitter to become empty */
378 do {
379 regmap_read(s->syscon, SYSFLG_OFFSET, &sysflg);
380 } while (sysflg & SYSFLG_UBUSY);
381}
382
383static int uart_clps711x_console_setup(struct console *co, char *options)
384{
385 int baud = 38400, bits = 8, parity = 'n', flow = 'n';
386 int ret, index = co->index;
387 struct clps711x_port *s;
388 struct uart_port *port;
389 unsigned int quot;
390 u32 ubrlcr;
391
392 if (index < 0 || index >= UART_CLPS711X_NR)
393 return -EINVAL;
394
395 port = clps711x_uart.state[index].uart_port;
396 if (!port)
397 return -ENODEV;
398
399 s = dev_get_drvdata(port->dev);
400
401 if (!options) {
402 u32 syscon = 0;
403
404 regmap_read(s->syscon, SYSCON_OFFSET, &syscon);
405 if (syscon & SYSCON_UARTEN) {
406 ubrlcr = readl(port->membase + UBRLCR_OFFSET);
407
408 if (ubrlcr & UBRLCR_PRTEN) {
409 if (ubrlcr & UBRLCR_EVENPRT)
410 parity = 'e';
411 else
412 parity = 'o';
413 }
414
415 if ((ubrlcr & UBRLCR_WRDLEN_MASK) == UBRLCR_WRDLEN7)
416 bits = 7;
417
418 quot = ubrlcr & UBRLCR_BAUD_MASK;
419 baud = port->uartclk / (16 * (quot + 1));
420 }
421 } else
422 uart_parse_options(options, &baud, &parity, &bits, &flow);
423
424 ret = uart_set_options(port, co, baud, parity, bits, flow);
425 if (ret)
426 return ret;
427
428 return regmap_update_bits(s->syscon, SYSCON_OFFSET,
429 SYSCON_UARTEN, SYSCON_UARTEN);
430}
431
432static struct console clps711x_console = {
433 .name = UART_CLPS711X_DEVNAME,
434 .device = uart_console_device,
435 .write = uart_clps711x_console_write,
436 .setup = uart_clps711x_console_setup,
437 .flags = CON_PRINTBUFFER,
438 .index = -1,
439};
440#endif
441
442static int uart_clps711x_probe(struct platform_device *pdev)
443{
444 struct device_node *np = pdev->dev.of_node;
445 struct clps711x_port *s;
446 struct resource *res;
447 struct clk *uart_clk;
448 int irq, ret;
449
450 s = devm_kzalloc(&pdev->dev, sizeof(*s), GFP_KERNEL);
451 if (!s)
452 return -ENOMEM;
453
454 uart_clk = devm_clk_get(&pdev->dev, NULL);
455 if (IS_ERR(uart_clk))
456 return PTR_ERR(uart_clk);
457
458 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
459 s->port.membase = devm_ioremap_resource(&pdev->dev, res);
460 if (IS_ERR(s->port.membase))
461 return PTR_ERR(s->port.membase);
462
463 irq = platform_get_irq(pdev, 0);
464 if (irq < 0)
465 return irq;
466 s->port.irq = irq;
467
468 s->rx_irq = platform_get_irq(pdev, 1);
469 if (s->rx_irq < 0)
470 return s->rx_irq;
471
472 s->syscon = syscon_regmap_lookup_by_phandle(np, "syscon");
473 if (IS_ERR(s->syscon))
474 return PTR_ERR(s->syscon);
475
476 s->port.line = of_alias_get_id(np, "serial");
477 s->port.dev = &pdev->dev;
478 s->port.iotype = UPIO_MEM32;
479 s->port.mapbase = res->start;
480 s->port.type = PORT_CLPS711X;
481 s->port.fifosize = 16;
482 s->port.flags = UPF_SKIP_TEST | UPF_FIXED_TYPE;
483 s->port.uartclk = clk_get_rate(uart_clk);
484 s->port.ops = &uart_clps711x_ops;
485
486 platform_set_drvdata(pdev, s);
487
488 s->gpios = mctrl_gpio_init_noauto(&pdev->dev, 0);
489 if (IS_ERR(s->gpios))
490 return PTR_ERR(s->gpios);
491
492 ret = uart_add_one_port(&clps711x_uart, &s->port);
493 if (ret)
494 return ret;
495
496 /* Disable port */
497 if (!uart_console(&s->port))
498 regmap_update_bits(s->syscon, SYSCON_OFFSET, SYSCON_UARTEN, 0);
499
500 s->tx_enabled = 1;
501
502 ret = devm_request_irq(&pdev->dev, s->port.irq, uart_clps711x_int_tx, 0,
503 dev_name(&pdev->dev), &s->port);
504 if (ret) {
505 uart_remove_one_port(&clps711x_uart, &s->port);
506 return ret;
507 }
508
509 ret = devm_request_irq(&pdev->dev, s->rx_irq, uart_clps711x_int_rx, 0,
510 dev_name(&pdev->dev), &s->port);
511 if (ret)
512 uart_remove_one_port(&clps711x_uart, &s->port);
513
514 return ret;
515}
516
517static int uart_clps711x_remove(struct platform_device *pdev)
518{
519 struct clps711x_port *s = platform_get_drvdata(pdev);
520
521 return uart_remove_one_port(&clps711x_uart, &s->port);
522}
523
524static const struct of_device_id __maybe_unused clps711x_uart_dt_ids[] = {
525 { .compatible = "cirrus,ep7209-uart", },
526 { }
527};
528MODULE_DEVICE_TABLE(of, clps711x_uart_dt_ids);
529
530static struct platform_driver clps711x_uart_platform = {
531 .driver = {
532 .name = "clps711x-uart",
533 .of_match_table = of_match_ptr(clps711x_uart_dt_ids),
534 },
535 .probe = uart_clps711x_probe,
536 .remove = uart_clps711x_remove,
537};
538
539static int __init uart_clps711x_init(void)
540{
541 int ret;
542
543#ifdef CONFIG_SERIAL_CLPS711X_CONSOLE
544 clps711x_uart.cons = &clps711x_console;
545 clps711x_console.data = &clps711x_uart;
546#endif
547
548 ret = uart_register_driver(&clps711x_uart);
549 if (ret)
550 return ret;
551
552 return platform_driver_register(&clps711x_uart_platform);
553}
554module_init(uart_clps711x_init);
555
556static void __exit uart_clps711x_exit(void)
557{
558 platform_driver_unregister(&clps711x_uart_platform);
559 uart_unregister_driver(&clps711x_uart);
560}
561module_exit(uart_clps711x_exit);
562
563MODULE_AUTHOR("Deep Blue Solutions Ltd");
564MODULE_DESCRIPTION("CLPS711X serial driver");
565MODULE_LICENSE("GPL");