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1// SPDX-License-Identifier: GPL-2.0+
2
3/*
4 * Freescale QuadSPI driver.
5 *
6 * Copyright (C) 2013 Freescale Semiconductor, Inc.
7 * Copyright (C) 2018 Bootlin
8 * Copyright (C) 2018 exceet electronics GmbH
9 * Copyright (C) 2018 Kontron Electronics GmbH
10 *
11 * Transition to SPI MEM interface:
12 * Authors:
13 * Boris Brezillon <bbrezillon@kernel.org>
14 * Frieder Schrempf <frieder.schrempf@kontron.de>
15 * Yogesh Gaur <yogeshnarayan.gaur@nxp.com>
16 * Suresh Gupta <suresh.gupta@nxp.com>
17 *
18 * Based on the original fsl-quadspi.c spi-nor driver:
19 * Author: Freescale Semiconductor, Inc.
20 *
21 */
22
23#include <linux/bitops.h>
24#include <linux/clk.h>
25#include <linux/completion.h>
26#include <linux/delay.h>
27#include <linux/err.h>
28#include <linux/errno.h>
29#include <linux/interrupt.h>
30#include <linux/io.h>
31#include <linux/iopoll.h>
32#include <linux/jiffies.h>
33#include <linux/kernel.h>
34#include <linux/module.h>
35#include <linux/mutex.h>
36#include <linux/of.h>
37#include <linux/of_device.h>
38#include <linux/platform_device.h>
39#include <linux/pm_qos.h>
40#include <linux/sizes.h>
41
42#include <linux/spi/spi.h>
43#include <linux/spi/spi-mem.h>
44
45/*
46 * The driver only uses one single LUT entry, that is updated on
47 * each call of exec_op(). Index 0 is preset at boot with a basic
48 * read operation, so let's use the last entry (15).
49 */
50#define SEQID_LUT 15
51
52/* Registers used by the driver */
53#define QUADSPI_MCR 0x00
54#define QUADSPI_MCR_RESERVED_MASK GENMASK(19, 16)
55#define QUADSPI_MCR_MDIS_MASK BIT(14)
56#define QUADSPI_MCR_CLR_TXF_MASK BIT(11)
57#define QUADSPI_MCR_CLR_RXF_MASK BIT(10)
58#define QUADSPI_MCR_DDR_EN_MASK BIT(7)
59#define QUADSPI_MCR_END_CFG_MASK GENMASK(3, 2)
60#define QUADSPI_MCR_SWRSTHD_MASK BIT(1)
61#define QUADSPI_MCR_SWRSTSD_MASK BIT(0)
62
63#define QUADSPI_IPCR 0x08
64#define QUADSPI_IPCR_SEQID(x) ((x) << 24)
65
66#define QUADSPI_BUF3CR 0x1c
67#define QUADSPI_BUF3CR_ALLMST_MASK BIT(31)
68#define QUADSPI_BUF3CR_ADATSZ(x) ((x) << 8)
69#define QUADSPI_BUF3CR_ADATSZ_MASK GENMASK(15, 8)
70
71#define QUADSPI_BFGENCR 0x20
72#define QUADSPI_BFGENCR_SEQID(x) ((x) << 12)
73
74#define QUADSPI_BUF0IND 0x30
75#define QUADSPI_BUF1IND 0x34
76#define QUADSPI_BUF2IND 0x38
77#define QUADSPI_SFAR 0x100
78
79#define QUADSPI_SMPR 0x108
80#define QUADSPI_SMPR_DDRSMP_MASK GENMASK(18, 16)
81#define QUADSPI_SMPR_FSDLY_MASK BIT(6)
82#define QUADSPI_SMPR_FSPHS_MASK BIT(5)
83#define QUADSPI_SMPR_HSENA_MASK BIT(0)
84
85#define QUADSPI_RBCT 0x110
86#define QUADSPI_RBCT_WMRK_MASK GENMASK(4, 0)
87#define QUADSPI_RBCT_RXBRD_USEIPS BIT(8)
88
89#define QUADSPI_TBDR 0x154
90
91#define QUADSPI_SR 0x15c
92#define QUADSPI_SR_IP_ACC_MASK BIT(1)
93#define QUADSPI_SR_AHB_ACC_MASK BIT(2)
94
95#define QUADSPI_FR 0x160
96#define QUADSPI_FR_TFF_MASK BIT(0)
97
98#define QUADSPI_SPTRCLR 0x16c
99#define QUADSPI_SPTRCLR_IPPTRC BIT(8)
100#define QUADSPI_SPTRCLR_BFPTRC BIT(0)
101
102#define QUADSPI_SFA1AD 0x180
103#define QUADSPI_SFA2AD 0x184
104#define QUADSPI_SFB1AD 0x188
105#define QUADSPI_SFB2AD 0x18c
106#define QUADSPI_RBDR(x) (0x200 + ((x) * 4))
107
108#define QUADSPI_LUTKEY 0x300
109#define QUADSPI_LUTKEY_VALUE 0x5AF05AF0
110
111#define QUADSPI_LCKCR 0x304
112#define QUADSPI_LCKER_LOCK BIT(0)
113#define QUADSPI_LCKER_UNLOCK BIT(1)
114
115#define QUADSPI_RSER 0x164
116#define QUADSPI_RSER_TFIE BIT(0)
117
118#define QUADSPI_LUT_BASE 0x310
119#define QUADSPI_LUT_OFFSET (SEQID_LUT * 4 * 4)
120#define QUADSPI_LUT_REG(idx) \
121 (QUADSPI_LUT_BASE + QUADSPI_LUT_OFFSET + (idx) * 4)
122
123/* Instruction set for the LUT register */
124#define LUT_STOP 0
125#define LUT_CMD 1
126#define LUT_ADDR 2
127#define LUT_DUMMY 3
128#define LUT_MODE 4
129#define LUT_MODE2 5
130#define LUT_MODE4 6
131#define LUT_FSL_READ 7
132#define LUT_FSL_WRITE 8
133#define LUT_JMP_ON_CS 9
134#define LUT_ADDR_DDR 10
135#define LUT_MODE_DDR 11
136#define LUT_MODE2_DDR 12
137#define LUT_MODE4_DDR 13
138#define LUT_FSL_READ_DDR 14
139#define LUT_FSL_WRITE_DDR 15
140#define LUT_DATA_LEARN 16
141
142/*
143 * The PAD definitions for LUT register.
144 *
145 * The pad stands for the number of IO lines [0:3].
146 * For example, the quad read needs four IO lines,
147 * so you should use LUT_PAD(4).
148 */
149#define LUT_PAD(x) (fls(x) - 1)
150
151/*
152 * Macro for constructing the LUT entries with the following
153 * register layout:
154 *
155 * ---------------------------------------------------
156 * | INSTR1 | PAD1 | OPRND1 | INSTR0 | PAD0 | OPRND0 |
157 * ---------------------------------------------------
158 */
159#define LUT_DEF(idx, ins, pad, opr) \
160 ((((ins) << 10) | ((pad) << 8) | (opr)) << (((idx) % 2) * 16))
161
162/* Controller needs driver to swap endianness */
163#define QUADSPI_QUIRK_SWAP_ENDIAN BIT(0)
164
165/* Controller needs 4x internal clock */
166#define QUADSPI_QUIRK_4X_INT_CLK BIT(1)
167
168/*
169 * TKT253890, the controller needs the driver to fill the txfifo with
170 * 16 bytes at least to trigger a data transfer, even though the extra
171 * data won't be transferred.
172 */
173#define QUADSPI_QUIRK_TKT253890 BIT(2)
174
175/* TKT245618, the controller cannot wake up from wait mode */
176#define QUADSPI_QUIRK_TKT245618 BIT(3)
177
178/*
179 * Controller adds QSPI_AMBA_BASE (base address of the mapped memory)
180 * internally. No need to add it when setting SFXXAD and SFAR registers
181 */
182#define QUADSPI_QUIRK_BASE_INTERNAL BIT(4)
183
184struct fsl_qspi_devtype_data {
185 unsigned int rxfifo;
186 unsigned int txfifo;
187 unsigned int ahb_buf_size;
188 unsigned int quirks;
189 bool little_endian;
190};
191
192static const struct fsl_qspi_devtype_data vybrid_data = {
193 .rxfifo = SZ_128,
194 .txfifo = SZ_64,
195 .ahb_buf_size = SZ_1K,
196 .quirks = QUADSPI_QUIRK_SWAP_ENDIAN,
197 .little_endian = true,
198};
199
200static const struct fsl_qspi_devtype_data imx6sx_data = {
201 .rxfifo = SZ_128,
202 .txfifo = SZ_512,
203 .ahb_buf_size = SZ_1K,
204 .quirks = QUADSPI_QUIRK_4X_INT_CLK | QUADSPI_QUIRK_TKT245618,
205 .little_endian = true,
206};
207
208static const struct fsl_qspi_devtype_data imx7d_data = {
209 .rxfifo = SZ_128,
210 .txfifo = SZ_512,
211 .ahb_buf_size = SZ_1K,
212 .quirks = QUADSPI_QUIRK_TKT253890 | QUADSPI_QUIRK_4X_INT_CLK,
213 .little_endian = true,
214};
215
216static const struct fsl_qspi_devtype_data imx6ul_data = {
217 .rxfifo = SZ_128,
218 .txfifo = SZ_512,
219 .ahb_buf_size = SZ_1K,
220 .quirks = QUADSPI_QUIRK_TKT253890 | QUADSPI_QUIRK_4X_INT_CLK,
221 .little_endian = true,
222};
223
224static const struct fsl_qspi_devtype_data ls1021a_data = {
225 .rxfifo = SZ_128,
226 .txfifo = SZ_64,
227 .ahb_buf_size = SZ_1K,
228 .quirks = 0,
229 .little_endian = false,
230};
231
232static const struct fsl_qspi_devtype_data ls2080a_data = {
233 .rxfifo = SZ_128,
234 .txfifo = SZ_64,
235 .ahb_buf_size = SZ_1K,
236 .quirks = QUADSPI_QUIRK_TKT253890 | QUADSPI_QUIRK_BASE_INTERNAL,
237 .little_endian = true,
238};
239
240struct fsl_qspi {
241 void __iomem *iobase;
242 void __iomem *ahb_addr;
243 u32 memmap_phy;
244 struct clk *clk, *clk_en;
245 struct device *dev;
246 struct completion c;
247 const struct fsl_qspi_devtype_data *devtype_data;
248 struct mutex lock;
249 struct pm_qos_request pm_qos_req;
250 int selected;
251};
252
253static inline int needs_swap_endian(struct fsl_qspi *q)
254{
255 return q->devtype_data->quirks & QUADSPI_QUIRK_SWAP_ENDIAN;
256}
257
258static inline int needs_4x_clock(struct fsl_qspi *q)
259{
260 return q->devtype_data->quirks & QUADSPI_QUIRK_4X_INT_CLK;
261}
262
263static inline int needs_fill_txfifo(struct fsl_qspi *q)
264{
265 return q->devtype_data->quirks & QUADSPI_QUIRK_TKT253890;
266}
267
268static inline int needs_wakeup_wait_mode(struct fsl_qspi *q)
269{
270 return q->devtype_data->quirks & QUADSPI_QUIRK_TKT245618;
271}
272
273static inline int needs_amba_base_offset(struct fsl_qspi *q)
274{
275 return !(q->devtype_data->quirks & QUADSPI_QUIRK_BASE_INTERNAL);
276}
277
278/*
279 * An IC bug makes it necessary to rearrange the 32-bit data.
280 * Later chips, such as IMX6SLX, have fixed this bug.
281 */
282static inline u32 fsl_qspi_endian_xchg(struct fsl_qspi *q, u32 a)
283{
284 return needs_swap_endian(q) ? __swab32(a) : a;
285}
286
287/*
288 * R/W functions for big- or little-endian registers:
289 * The QSPI controller's endianness is independent of
290 * the CPU core's endianness. So far, although the CPU
291 * core is little-endian the QSPI controller can use
292 * big-endian or little-endian.
293 */
294static void qspi_writel(struct fsl_qspi *q, u32 val, void __iomem *addr)
295{
296 if (q->devtype_data->little_endian)
297 iowrite32(val, addr);
298 else
299 iowrite32be(val, addr);
300}
301
302static u32 qspi_readl(struct fsl_qspi *q, void __iomem *addr)
303{
304 if (q->devtype_data->little_endian)
305 return ioread32(addr);
306
307 return ioread32be(addr);
308}
309
310static irqreturn_t fsl_qspi_irq_handler(int irq, void *dev_id)
311{
312 struct fsl_qspi *q = dev_id;
313 u32 reg;
314
315 /* clear interrupt */
316 reg = qspi_readl(q, q->iobase + QUADSPI_FR);
317 qspi_writel(q, reg, q->iobase + QUADSPI_FR);
318
319 if (reg & QUADSPI_FR_TFF_MASK)
320 complete(&q->c);
321
322 dev_dbg(q->dev, "QUADSPI_FR : 0x%.8x:0x%.8x\n", 0, reg);
323 return IRQ_HANDLED;
324}
325
326static int fsl_qspi_check_buswidth(struct fsl_qspi *q, u8 width)
327{
328 switch (width) {
329 case 1:
330 case 2:
331 case 4:
332 return 0;
333 }
334
335 return -ENOTSUPP;
336}
337
338static bool fsl_qspi_supports_op(struct spi_mem *mem,
339 const struct spi_mem_op *op)
340{
341 struct fsl_qspi *q = spi_controller_get_devdata(mem->spi->master);
342 int ret;
343
344 ret = fsl_qspi_check_buswidth(q, op->cmd.buswidth);
345
346 if (op->addr.nbytes)
347 ret |= fsl_qspi_check_buswidth(q, op->addr.buswidth);
348
349 if (op->dummy.nbytes)
350 ret |= fsl_qspi_check_buswidth(q, op->dummy.buswidth);
351
352 if (op->data.nbytes)
353 ret |= fsl_qspi_check_buswidth(q, op->data.buswidth);
354
355 if (ret)
356 return false;
357
358 /*
359 * The number of instructions needed for the op, needs
360 * to fit into a single LUT entry.
361 */
362 if (op->addr.nbytes +
363 (op->dummy.nbytes ? 1:0) +
364 (op->data.nbytes ? 1:0) > 6)
365 return false;
366
367 /* Max 64 dummy clock cycles supported */
368 if (op->dummy.nbytes &&
369 (op->dummy.nbytes * 8 / op->dummy.buswidth > 64))
370 return false;
371
372 /* Max data length, check controller limits and alignment */
373 if (op->data.dir == SPI_MEM_DATA_IN &&
374 (op->data.nbytes > q->devtype_data->ahb_buf_size ||
375 (op->data.nbytes > q->devtype_data->rxfifo - 4 &&
376 !IS_ALIGNED(op->data.nbytes, 8))))
377 return false;
378
379 if (op->data.dir == SPI_MEM_DATA_OUT &&
380 op->data.nbytes > q->devtype_data->txfifo)
381 return false;
382
383 return true;
384}
385
386static void fsl_qspi_prepare_lut(struct fsl_qspi *q,
387 const struct spi_mem_op *op)
388{
389 void __iomem *base = q->iobase;
390 u32 lutval[4] = {};
391 int lutidx = 1, i;
392
393 lutval[0] |= LUT_DEF(0, LUT_CMD, LUT_PAD(op->cmd.buswidth),
394 op->cmd.opcode);
395
396 /*
397 * For some unknown reason, using LUT_ADDR doesn't work in some
398 * cases (at least with only one byte long addresses), so
399 * let's use LUT_MODE to write the address bytes one by one
400 */
401 for (i = 0; i < op->addr.nbytes; i++) {
402 u8 addrbyte = op->addr.val >> (8 * (op->addr.nbytes - i - 1));
403
404 lutval[lutidx / 2] |= LUT_DEF(lutidx, LUT_MODE,
405 LUT_PAD(op->addr.buswidth),
406 addrbyte);
407 lutidx++;
408 }
409
410 if (op->dummy.nbytes) {
411 lutval[lutidx / 2] |= LUT_DEF(lutidx, LUT_DUMMY,
412 LUT_PAD(op->dummy.buswidth),
413 op->dummy.nbytes * 8 /
414 op->dummy.buswidth);
415 lutidx++;
416 }
417
418 if (op->data.nbytes) {
419 lutval[lutidx / 2] |= LUT_DEF(lutidx,
420 op->data.dir == SPI_MEM_DATA_IN ?
421 LUT_FSL_READ : LUT_FSL_WRITE,
422 LUT_PAD(op->data.buswidth),
423 0);
424 lutidx++;
425 }
426
427 lutval[lutidx / 2] |= LUT_DEF(lutidx, LUT_STOP, 0, 0);
428
429 /* unlock LUT */
430 qspi_writel(q, QUADSPI_LUTKEY_VALUE, q->iobase + QUADSPI_LUTKEY);
431 qspi_writel(q, QUADSPI_LCKER_UNLOCK, q->iobase + QUADSPI_LCKCR);
432
433 /* fill LUT */
434 for (i = 0; i < ARRAY_SIZE(lutval); i++)
435 qspi_writel(q, lutval[i], base + QUADSPI_LUT_REG(i));
436
437 /* lock LUT */
438 qspi_writel(q, QUADSPI_LUTKEY_VALUE, q->iobase + QUADSPI_LUTKEY);
439 qspi_writel(q, QUADSPI_LCKER_LOCK, q->iobase + QUADSPI_LCKCR);
440}
441
442static int fsl_qspi_clk_prep_enable(struct fsl_qspi *q)
443{
444 int ret;
445
446 ret = clk_prepare_enable(q->clk_en);
447 if (ret)
448 return ret;
449
450 ret = clk_prepare_enable(q->clk);
451 if (ret) {
452 clk_disable_unprepare(q->clk_en);
453 return ret;
454 }
455
456 if (needs_wakeup_wait_mode(q))
457 pm_qos_add_request(&q->pm_qos_req, PM_QOS_CPU_DMA_LATENCY, 0);
458
459 return 0;
460}
461
462static void fsl_qspi_clk_disable_unprep(struct fsl_qspi *q)
463{
464 if (needs_wakeup_wait_mode(q))
465 pm_qos_remove_request(&q->pm_qos_req);
466
467 clk_disable_unprepare(q->clk);
468 clk_disable_unprepare(q->clk_en);
469}
470
471/*
472 * If we have changed the content of the flash by writing or erasing, or if we
473 * read from flash with a different offset into the page buffer, we need to
474 * invalidate the AHB buffer. If we do not do so, we may read out the wrong
475 * data. The spec tells us reset the AHB domain and Serial Flash domain at
476 * the same time.
477 */
478static void fsl_qspi_invalidate(struct fsl_qspi *q)
479{
480 u32 reg;
481
482 reg = qspi_readl(q, q->iobase + QUADSPI_MCR);
483 reg |= QUADSPI_MCR_SWRSTHD_MASK | QUADSPI_MCR_SWRSTSD_MASK;
484 qspi_writel(q, reg, q->iobase + QUADSPI_MCR);
485
486 /*
487 * The minimum delay : 1 AHB + 2 SFCK clocks.
488 * Delay 1 us is enough.
489 */
490 udelay(1);
491
492 reg &= ~(QUADSPI_MCR_SWRSTHD_MASK | QUADSPI_MCR_SWRSTSD_MASK);
493 qspi_writel(q, reg, q->iobase + QUADSPI_MCR);
494}
495
496static void fsl_qspi_select_mem(struct fsl_qspi *q, struct spi_device *spi)
497{
498 unsigned long rate = spi->max_speed_hz;
499 int ret;
500
501 if (q->selected == spi->chip_select)
502 return;
503
504 if (needs_4x_clock(q))
505 rate *= 4;
506
507 fsl_qspi_clk_disable_unprep(q);
508
509 ret = clk_set_rate(q->clk, rate);
510 if (ret)
511 return;
512
513 ret = fsl_qspi_clk_prep_enable(q);
514 if (ret)
515 return;
516
517 q->selected = spi->chip_select;
518
519 fsl_qspi_invalidate(q);
520}
521
522static void fsl_qspi_read_ahb(struct fsl_qspi *q, const struct spi_mem_op *op)
523{
524 memcpy_fromio(op->data.buf.in,
525 q->ahb_addr + q->selected * q->devtype_data->ahb_buf_size,
526 op->data.nbytes);
527}
528
529static void fsl_qspi_fill_txfifo(struct fsl_qspi *q,
530 const struct spi_mem_op *op)
531{
532 void __iomem *base = q->iobase;
533 int i;
534 u32 val;
535
536 for (i = 0; i < ALIGN_DOWN(op->data.nbytes, 4); i += 4) {
537 memcpy(&val, op->data.buf.out + i, 4);
538 val = fsl_qspi_endian_xchg(q, val);
539 qspi_writel(q, val, base + QUADSPI_TBDR);
540 }
541
542 if (i < op->data.nbytes) {
543 memcpy(&val, op->data.buf.out + i, op->data.nbytes - i);
544 val = fsl_qspi_endian_xchg(q, val);
545 qspi_writel(q, val, base + QUADSPI_TBDR);
546 }
547
548 if (needs_fill_txfifo(q)) {
549 for (i = op->data.nbytes; i < 16; i += 4)
550 qspi_writel(q, 0, base + QUADSPI_TBDR);
551 }
552}
553
554static void fsl_qspi_read_rxfifo(struct fsl_qspi *q,
555 const struct spi_mem_op *op)
556{
557 void __iomem *base = q->iobase;
558 int i;
559 u8 *buf = op->data.buf.in;
560 u32 val;
561
562 for (i = 0; i < ALIGN_DOWN(op->data.nbytes, 4); i += 4) {
563 val = qspi_readl(q, base + QUADSPI_RBDR(i / 4));
564 val = fsl_qspi_endian_xchg(q, val);
565 memcpy(buf + i, &val, 4);
566 }
567
568 if (i < op->data.nbytes) {
569 val = qspi_readl(q, base + QUADSPI_RBDR(i / 4));
570 val = fsl_qspi_endian_xchg(q, val);
571 memcpy(buf + i, &val, op->data.nbytes - i);
572 }
573}
574
575static int fsl_qspi_do_op(struct fsl_qspi *q, const struct spi_mem_op *op)
576{
577 void __iomem *base = q->iobase;
578 int err = 0;
579
580 init_completion(&q->c);
581
582 /*
583 * Always start the sequence at the same index since we update
584 * the LUT at each exec_op() call. And also specify the DATA
585 * length, since it's has not been specified in the LUT.
586 */
587 qspi_writel(q, op->data.nbytes | QUADSPI_IPCR_SEQID(SEQID_LUT),
588 base + QUADSPI_IPCR);
589
590 /* Wait for the interrupt. */
591 if (!wait_for_completion_timeout(&q->c, msecs_to_jiffies(1000)))
592 err = -ETIMEDOUT;
593
594 if (!err && op->data.nbytes && op->data.dir == SPI_MEM_DATA_IN)
595 fsl_qspi_read_rxfifo(q, op);
596
597 return err;
598}
599
600static int fsl_qspi_readl_poll_tout(struct fsl_qspi *q, void __iomem *base,
601 u32 mask, u32 delay_us, u32 timeout_us)
602{
603 u32 reg;
604
605 if (!q->devtype_data->little_endian)
606 mask = (u32)cpu_to_be32(mask);
607
608 return readl_poll_timeout(base, reg, !(reg & mask), delay_us,
609 timeout_us);
610}
611
612static int fsl_qspi_exec_op(struct spi_mem *mem, const struct spi_mem_op *op)
613{
614 struct fsl_qspi *q = spi_controller_get_devdata(mem->spi->master);
615 void __iomem *base = q->iobase;
616 u32 addr_offset = 0;
617 int err = 0;
618
619 mutex_lock(&q->lock);
620
621 /* wait for the controller being ready */
622 fsl_qspi_readl_poll_tout(q, base + QUADSPI_SR, (QUADSPI_SR_IP_ACC_MASK |
623 QUADSPI_SR_AHB_ACC_MASK), 10, 1000);
624
625 fsl_qspi_select_mem(q, mem->spi);
626
627 if (needs_amba_base_offset(q))
628 addr_offset = q->memmap_phy;
629
630 qspi_writel(q,
631 q->selected * q->devtype_data->ahb_buf_size + addr_offset,
632 base + QUADSPI_SFAR);
633
634 qspi_writel(q, qspi_readl(q, base + QUADSPI_MCR) |
635 QUADSPI_MCR_CLR_RXF_MASK | QUADSPI_MCR_CLR_TXF_MASK,
636 base + QUADSPI_MCR);
637
638 qspi_writel(q, QUADSPI_SPTRCLR_BFPTRC | QUADSPI_SPTRCLR_IPPTRC,
639 base + QUADSPI_SPTRCLR);
640
641 fsl_qspi_prepare_lut(q, op);
642
643 /*
644 * If we have large chunks of data, we read them through the AHB bus
645 * by accessing the mapped memory. In all other cases we use
646 * IP commands to access the flash.
647 */
648 if (op->data.nbytes > (q->devtype_data->rxfifo - 4) &&
649 op->data.dir == SPI_MEM_DATA_IN) {
650 fsl_qspi_read_ahb(q, op);
651 } else {
652 qspi_writel(q, QUADSPI_RBCT_WMRK_MASK |
653 QUADSPI_RBCT_RXBRD_USEIPS, base + QUADSPI_RBCT);
654
655 if (op->data.nbytes && op->data.dir == SPI_MEM_DATA_OUT)
656 fsl_qspi_fill_txfifo(q, op);
657
658 err = fsl_qspi_do_op(q, op);
659 }
660
661 /* Invalidate the data in the AHB buffer. */
662 fsl_qspi_invalidate(q);
663
664 mutex_unlock(&q->lock);
665
666 return err;
667}
668
669static int fsl_qspi_adjust_op_size(struct spi_mem *mem, struct spi_mem_op *op)
670{
671 struct fsl_qspi *q = spi_controller_get_devdata(mem->spi->master);
672
673 if (op->data.dir == SPI_MEM_DATA_OUT) {
674 if (op->data.nbytes > q->devtype_data->txfifo)
675 op->data.nbytes = q->devtype_data->txfifo;
676 } else {
677 if (op->data.nbytes > q->devtype_data->ahb_buf_size)
678 op->data.nbytes = q->devtype_data->ahb_buf_size;
679 else if (op->data.nbytes > (q->devtype_data->rxfifo - 4))
680 op->data.nbytes = ALIGN_DOWN(op->data.nbytes, 8);
681 }
682
683 return 0;
684}
685
686static int fsl_qspi_default_setup(struct fsl_qspi *q)
687{
688 void __iomem *base = q->iobase;
689 u32 reg, addr_offset = 0;
690 int ret;
691
692 /* disable and unprepare clock to avoid glitch pass to controller */
693 fsl_qspi_clk_disable_unprep(q);
694
695 /* the default frequency, we will change it later if necessary. */
696 ret = clk_set_rate(q->clk, 66000000);
697 if (ret)
698 return ret;
699
700 ret = fsl_qspi_clk_prep_enable(q);
701 if (ret)
702 return ret;
703
704 /* Reset the module */
705 qspi_writel(q, QUADSPI_MCR_SWRSTSD_MASK | QUADSPI_MCR_SWRSTHD_MASK,
706 base + QUADSPI_MCR);
707 udelay(1);
708
709 /* Disable the module */
710 qspi_writel(q, QUADSPI_MCR_MDIS_MASK | QUADSPI_MCR_RESERVED_MASK,
711 base + QUADSPI_MCR);
712
713 reg = qspi_readl(q, base + QUADSPI_SMPR);
714 qspi_writel(q, reg & ~(QUADSPI_SMPR_FSDLY_MASK
715 | QUADSPI_SMPR_FSPHS_MASK
716 | QUADSPI_SMPR_HSENA_MASK
717 | QUADSPI_SMPR_DDRSMP_MASK), base + QUADSPI_SMPR);
718
719 /* We only use the buffer3 for AHB read */
720 qspi_writel(q, 0, base + QUADSPI_BUF0IND);
721 qspi_writel(q, 0, base + QUADSPI_BUF1IND);
722 qspi_writel(q, 0, base + QUADSPI_BUF2IND);
723
724 qspi_writel(q, QUADSPI_BFGENCR_SEQID(SEQID_LUT),
725 q->iobase + QUADSPI_BFGENCR);
726 qspi_writel(q, QUADSPI_RBCT_WMRK_MASK, base + QUADSPI_RBCT);
727 qspi_writel(q, QUADSPI_BUF3CR_ALLMST_MASK |
728 QUADSPI_BUF3CR_ADATSZ(q->devtype_data->ahb_buf_size / 8),
729 base + QUADSPI_BUF3CR);
730
731 if (needs_amba_base_offset(q))
732 addr_offset = q->memmap_phy;
733
734 /*
735 * In HW there can be a maximum of four chips on two buses with
736 * two chip selects on each bus. We use four chip selects in SW
737 * to differentiate between the four chips.
738 * We use ahb_buf_size for each chip and set SFA1AD, SFA2AD, SFB1AD,
739 * SFB2AD accordingly.
740 */
741 qspi_writel(q, q->devtype_data->ahb_buf_size + addr_offset,
742 base + QUADSPI_SFA1AD);
743 qspi_writel(q, q->devtype_data->ahb_buf_size * 2 + addr_offset,
744 base + QUADSPI_SFA2AD);
745 qspi_writel(q, q->devtype_data->ahb_buf_size * 3 + addr_offset,
746 base + QUADSPI_SFB1AD);
747 qspi_writel(q, q->devtype_data->ahb_buf_size * 4 + addr_offset,
748 base + QUADSPI_SFB2AD);
749
750 q->selected = -1;
751
752 /* Enable the module */
753 qspi_writel(q, QUADSPI_MCR_RESERVED_MASK | QUADSPI_MCR_END_CFG_MASK,
754 base + QUADSPI_MCR);
755
756 /* clear all interrupt status */
757 qspi_writel(q, 0xffffffff, q->iobase + QUADSPI_FR);
758
759 /* enable the interrupt */
760 qspi_writel(q, QUADSPI_RSER_TFIE, q->iobase + QUADSPI_RSER);
761
762 return 0;
763}
764
765static const char *fsl_qspi_get_name(struct spi_mem *mem)
766{
767 struct fsl_qspi *q = spi_controller_get_devdata(mem->spi->master);
768 struct device *dev = &mem->spi->dev;
769 const char *name;
770
771 /*
772 * In order to keep mtdparts compatible with the old MTD driver at
773 * mtd/spi-nor/fsl-quadspi.c, we set a custom name derived from the
774 * platform_device of the controller.
775 */
776 if (of_get_available_child_count(q->dev->of_node) == 1)
777 return dev_name(q->dev);
778
779 name = devm_kasprintf(dev, GFP_KERNEL,
780 "%s-%d", dev_name(q->dev),
781 mem->spi->chip_select);
782
783 if (!name) {
784 dev_err(dev, "failed to get memory for custom flash name\n");
785 return ERR_PTR(-ENOMEM);
786 }
787
788 return name;
789}
790
791static const struct spi_controller_mem_ops fsl_qspi_mem_ops = {
792 .adjust_op_size = fsl_qspi_adjust_op_size,
793 .supports_op = fsl_qspi_supports_op,
794 .exec_op = fsl_qspi_exec_op,
795 .get_name = fsl_qspi_get_name,
796};
797
798static int fsl_qspi_probe(struct platform_device *pdev)
799{
800 struct spi_controller *ctlr;
801 struct device *dev = &pdev->dev;
802 struct device_node *np = dev->of_node;
803 struct resource *res;
804 struct fsl_qspi *q;
805 int ret;
806
807 ctlr = spi_alloc_master(&pdev->dev, sizeof(*q));
808 if (!ctlr)
809 return -ENOMEM;
810
811 ctlr->mode_bits = SPI_RX_DUAL | SPI_RX_QUAD |
812 SPI_TX_DUAL | SPI_TX_QUAD;
813
814 q = spi_controller_get_devdata(ctlr);
815 q->dev = dev;
816 q->devtype_data = of_device_get_match_data(dev);
817 if (!q->devtype_data) {
818 ret = -ENODEV;
819 goto err_put_ctrl;
820 }
821
822 platform_set_drvdata(pdev, q);
823
824 /* find the resources */
825 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "QuadSPI");
826 q->iobase = devm_ioremap_resource(dev, res);
827 if (IS_ERR(q->iobase)) {
828 ret = PTR_ERR(q->iobase);
829 goto err_put_ctrl;
830 }
831
832 res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
833 "QuadSPI-memory");
834 q->ahb_addr = devm_ioremap_resource(dev, res);
835 if (IS_ERR(q->ahb_addr)) {
836 ret = PTR_ERR(q->ahb_addr);
837 goto err_put_ctrl;
838 }
839
840 q->memmap_phy = res->start;
841
842 /* find the clocks */
843 q->clk_en = devm_clk_get(dev, "qspi_en");
844 if (IS_ERR(q->clk_en)) {
845 ret = PTR_ERR(q->clk_en);
846 goto err_put_ctrl;
847 }
848
849 q->clk = devm_clk_get(dev, "qspi");
850 if (IS_ERR(q->clk)) {
851 ret = PTR_ERR(q->clk);
852 goto err_put_ctrl;
853 }
854
855 ret = fsl_qspi_clk_prep_enable(q);
856 if (ret) {
857 dev_err(dev, "can not enable the clock\n");
858 goto err_put_ctrl;
859 }
860
861 /* find the irq */
862 ret = platform_get_irq(pdev, 0);
863 if (ret < 0)
864 goto err_disable_clk;
865
866 ret = devm_request_irq(dev, ret,
867 fsl_qspi_irq_handler, 0, pdev->name, q);
868 if (ret) {
869 dev_err(dev, "failed to request irq: %d\n", ret);
870 goto err_disable_clk;
871 }
872
873 mutex_init(&q->lock);
874
875 ctlr->bus_num = -1;
876 ctlr->num_chipselect = 4;
877 ctlr->mem_ops = &fsl_qspi_mem_ops;
878
879 fsl_qspi_default_setup(q);
880
881 ctlr->dev.of_node = np;
882
883 ret = devm_spi_register_controller(dev, ctlr);
884 if (ret)
885 goto err_destroy_mutex;
886
887 return 0;
888
889err_destroy_mutex:
890 mutex_destroy(&q->lock);
891
892err_disable_clk:
893 fsl_qspi_clk_disable_unprep(q);
894
895err_put_ctrl:
896 spi_controller_put(ctlr);
897
898 dev_err(dev, "Freescale QuadSPI probe failed\n");
899 return ret;
900}
901
902static int fsl_qspi_remove(struct platform_device *pdev)
903{
904 struct fsl_qspi *q = platform_get_drvdata(pdev);
905
906 /* disable the hardware */
907 qspi_writel(q, QUADSPI_MCR_MDIS_MASK, q->iobase + QUADSPI_MCR);
908 qspi_writel(q, 0x0, q->iobase + QUADSPI_RSER);
909
910 fsl_qspi_clk_disable_unprep(q);
911
912 mutex_destroy(&q->lock);
913
914 return 0;
915}
916
917static int fsl_qspi_suspend(struct device *dev)
918{
919 return 0;
920}
921
922static int fsl_qspi_resume(struct device *dev)
923{
924 struct fsl_qspi *q = dev_get_drvdata(dev);
925
926 fsl_qspi_default_setup(q);
927
928 return 0;
929}
930
931static const struct of_device_id fsl_qspi_dt_ids[] = {
932 { .compatible = "fsl,vf610-qspi", .data = &vybrid_data, },
933 { .compatible = "fsl,imx6sx-qspi", .data = &imx6sx_data, },
934 { .compatible = "fsl,imx7d-qspi", .data = &imx7d_data, },
935 { .compatible = "fsl,imx6ul-qspi", .data = &imx6ul_data, },
936 { .compatible = "fsl,ls1021a-qspi", .data = &ls1021a_data, },
937 { .compatible = "fsl,ls2080a-qspi", .data = &ls2080a_data, },
938 { /* sentinel */ }
939};
940MODULE_DEVICE_TABLE(of, fsl_qspi_dt_ids);
941
942static const struct dev_pm_ops fsl_qspi_pm_ops = {
943 .suspend = fsl_qspi_suspend,
944 .resume = fsl_qspi_resume,
945};
946
947static struct platform_driver fsl_qspi_driver = {
948 .driver = {
949 .name = "fsl-quadspi",
950 .of_match_table = fsl_qspi_dt_ids,
951 .pm = &fsl_qspi_pm_ops,
952 },
953 .probe = fsl_qspi_probe,
954 .remove = fsl_qspi_remove,
955};
956module_platform_driver(fsl_qspi_driver);
957
958MODULE_DESCRIPTION("Freescale QuadSPI Controller Driver");
959MODULE_AUTHOR("Freescale Semiconductor Inc.");
960MODULE_AUTHOR("Boris Brezillon <bbrezillon@kernel.org>");
961MODULE_AUTHOR("Frieder Schrempf <frieder.schrempf@kontron.de>");
962MODULE_AUTHOR("Yogesh Gaur <yogeshnarayan.gaur@nxp.com>");
963MODULE_AUTHOR("Suresh Gupta <suresh.gupta@nxp.com>");
964MODULE_LICENSE("GPL v2");