Loading...
Note: File does not exist in v3.1.
1/*
2 * This file is part of the Chelsio FCoE driver for Linux.
3 *
4 * Copyright (c) 2008-2013 Chelsio Communications, Inc. All rights reserved.
5 *
6 * This software is available to you under a choice of one of two
7 * licenses. You may choose to be licensed under the terms of the GNU
8 * General Public License (GPL) Version 2, available from the file
9 * OpenIB.org BSD license below:
10 *
11 * Redistribution and use in source and binary forms, with or
12 * without modification, are permitted provided that the following
13 * conditions are met:
14 *
15 * - Redistributions of source code must retain the above
16 * copyright notice, this list of conditions and the following
17 * disclaimer.
18 *
19 * - Redistributions in binary form must reproduce the above
20 * copyright notice, this list of conditions and the following
21 * disclaimer in the documentation and/or other materials
22 * provided with the distribution.
23 *
24 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
25 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
26 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
27 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
28 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
29 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
30 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
31 * SOFTWARE.
32 */
33
34#include "csio_hw.h"
35#include "csio_init.h"
36
37static int
38csio_t5_set_mem_win(struct csio_hw *hw, uint32_t win)
39{
40 u32 mem_win_base;
41 /*
42 * Truncation intentional: we only read the bottom 32-bits of the
43 * 64-bit BAR0/BAR1 ... We use the hardware backdoor mechanism to
44 * read BAR0 instead of using pci_resource_start() because we could be
45 * operating from within a Virtual Machine which is trapping our
46 * accesses to our Configuration Space and we need to set up the PCI-E
47 * Memory Window decoders with the actual addresses which will be
48 * coming across the PCI-E link.
49 */
50
51 /* For T5, only relative offset inside the PCIe BAR is passed */
52 mem_win_base = MEMWIN_BASE;
53
54 /*
55 * Set up memory window for accessing adapter memory ranges. (Read
56 * back MA register to ensure that changes propagate before we attempt
57 * to use the new values.)
58 */
59 csio_wr_reg32(hw, mem_win_base | BIR_V(0) |
60 WINDOW_V(ilog2(MEMWIN_APERTURE) - 10),
61 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN_A, win));
62 csio_rd_reg32(hw,
63 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN_A, win));
64
65 return 0;
66}
67
68/*
69 * Interrupt handler for the PCIE module.
70 */
71static void
72csio_t5_pcie_intr_handler(struct csio_hw *hw)
73{
74 static struct intr_info pcie_intr_info[] = {
75 { MSTGRPPERR_F, "Master Response Read Queue parity error",
76 -1, 1 },
77 { MSTTIMEOUTPERR_F, "Master Timeout FIFO parity error", -1, 1 },
78 { MSIXSTIPERR_F, "MSI-X STI SRAM parity error", -1, 1 },
79 { MSIXADDRLPERR_F, "MSI-X AddrL parity error", -1, 1 },
80 { MSIXADDRHPERR_F, "MSI-X AddrH parity error", -1, 1 },
81 { MSIXDATAPERR_F, "MSI-X data parity error", -1, 1 },
82 { MSIXDIPERR_F, "MSI-X DI parity error", -1, 1 },
83 { PIOCPLGRPPERR_F, "PCI PIO completion Group FIFO parity error",
84 -1, 1 },
85 { PIOREQGRPPERR_F, "PCI PIO request Group FIFO parity error",
86 -1, 1 },
87 { TARTAGPERR_F, "PCI PCI target tag FIFO parity error", -1, 1 },
88 { MSTTAGQPERR_F, "PCI master tag queue parity error", -1, 1 },
89 { CREQPERR_F, "PCI CMD channel request parity error", -1, 1 },
90 { CRSPPERR_F, "PCI CMD channel response parity error", -1, 1 },
91 { DREQWRPERR_F, "PCI DMA channel write request parity error",
92 -1, 1 },
93 { DREQPERR_F, "PCI DMA channel request parity error", -1, 1 },
94 { DRSPPERR_F, "PCI DMA channel response parity error", -1, 1 },
95 { HREQWRPERR_F, "PCI HMA channel count parity error", -1, 1 },
96 { HREQPERR_F, "PCI HMA channel request parity error", -1, 1 },
97 { HRSPPERR_F, "PCI HMA channel response parity error", -1, 1 },
98 { CFGSNPPERR_F, "PCI config snoop FIFO parity error", -1, 1 },
99 { FIDPERR_F, "PCI FID parity error", -1, 1 },
100 { VFIDPERR_F, "PCI INTx clear parity error", -1, 1 },
101 { MAGRPPERR_F, "PCI MA group FIFO parity error", -1, 1 },
102 { PIOTAGPERR_F, "PCI PIO tag parity error", -1, 1 },
103 { IPRXHDRGRPPERR_F, "PCI IP Rx header group parity error",
104 -1, 1 },
105 { IPRXDATAGRPPERR_F, "PCI IP Rx data group parity error",
106 -1, 1 },
107 { RPLPERR_F, "PCI IP replay buffer parity error", -1, 1 },
108 { IPSOTPERR_F, "PCI IP SOT buffer parity error", -1, 1 },
109 { TRGT1GRPPERR_F, "PCI TRGT1 group FIFOs parity error", -1, 1 },
110 { READRSPERR_F, "Outbound read error", -1, 0 },
111 { 0, NULL, 0, 0 }
112 };
113
114 int fat;
115 fat = csio_handle_intr_status(hw, PCIE_INT_CAUSE_A, pcie_intr_info);
116 if (fat)
117 csio_hw_fatal_err(hw);
118}
119
120/*
121 * csio_t5_flash_cfg_addr - return the address of the flash configuration file
122 * @hw: the HW module
123 *
124 * Return the address within the flash where the Firmware Configuration
125 * File is stored.
126 */
127static unsigned int
128csio_t5_flash_cfg_addr(struct csio_hw *hw)
129{
130 return FLASH_CFG_START;
131}
132
133/*
134 * csio_t5_mc_read - read from MC through backdoor accesses
135 * @hw: the hw module
136 * @idx: index to the register
137 * @addr: address of first byte requested
138 * @data: 64 bytes of data containing the requested address
139 * @ecc: where to store the corresponding 64-bit ECC word
140 *
141 * Read 64 bytes of data from MC starting at a 64-byte-aligned address
142 * that covers the requested address @addr. If @parity is not %NULL it
143 * is assigned the 64-bit ECC word for the read data.
144 */
145static int
146csio_t5_mc_read(struct csio_hw *hw, int idx, uint32_t addr, __be32 *data,
147 uint64_t *ecc)
148{
149 int i;
150 uint32_t mc_bist_cmd_reg, mc_bist_cmd_addr_reg, mc_bist_cmd_len_reg;
151 uint32_t mc_bist_status_rdata_reg, mc_bist_data_pattern_reg;
152
153 mc_bist_cmd_reg = MC_REG(MC_P_BIST_CMD_A, idx);
154 mc_bist_cmd_addr_reg = MC_REG(MC_P_BIST_CMD_ADDR_A, idx);
155 mc_bist_cmd_len_reg = MC_REG(MC_P_BIST_CMD_LEN_A, idx);
156 mc_bist_status_rdata_reg = MC_REG(MC_P_BIST_STATUS_RDATA_A, idx);
157 mc_bist_data_pattern_reg = MC_REG(MC_P_BIST_DATA_PATTERN_A, idx);
158
159 if (csio_rd_reg32(hw, mc_bist_cmd_reg) & START_BIST_F)
160 return -EBUSY;
161 csio_wr_reg32(hw, addr & ~0x3fU, mc_bist_cmd_addr_reg);
162 csio_wr_reg32(hw, 64, mc_bist_cmd_len_reg);
163 csio_wr_reg32(hw, 0xc, mc_bist_data_pattern_reg);
164 csio_wr_reg32(hw, BIST_OPCODE_V(1) | START_BIST_F | BIST_CMD_GAP_V(1),
165 mc_bist_cmd_reg);
166 i = csio_hw_wait_op_done_val(hw, mc_bist_cmd_reg, START_BIST_F,
167 0, 10, 1, NULL);
168 if (i)
169 return i;
170
171#define MC_DATA(i) MC_BIST_STATUS_REG(MC_BIST_STATUS_RDATA_A, i)
172
173 for (i = 15; i >= 0; i--)
174 *data++ = htonl(csio_rd_reg32(hw, MC_DATA(i)));
175 if (ecc)
176 *ecc = csio_rd_reg64(hw, MC_DATA(16));
177#undef MC_DATA
178 return 0;
179}
180
181/*
182 * csio_t5_edc_read - read from EDC through backdoor accesses
183 * @hw: the hw module
184 * @idx: which EDC to access
185 * @addr: address of first byte requested
186 * @data: 64 bytes of data containing the requested address
187 * @ecc: where to store the corresponding 64-bit ECC word
188 *
189 * Read 64 bytes of data from EDC starting at a 64-byte-aligned address
190 * that covers the requested address @addr. If @parity is not %NULL it
191 * is assigned the 64-bit ECC word for the read data.
192 */
193static int
194csio_t5_edc_read(struct csio_hw *hw, int idx, uint32_t addr, __be32 *data,
195 uint64_t *ecc)
196{
197 int i;
198 uint32_t edc_bist_cmd_reg, edc_bist_cmd_addr_reg, edc_bist_cmd_len_reg;
199 uint32_t edc_bist_cmd_data_pattern, edc_bist_status_rdata_reg;
200
201/*
202 * These macro are missing in t4_regs.h file.
203 */
204#define EDC_STRIDE_T5 (EDC_T51_BASE_ADDR - EDC_T50_BASE_ADDR)
205#define EDC_REG_T5(reg, idx) (reg + EDC_STRIDE_T5 * idx)
206
207 edc_bist_cmd_reg = EDC_REG_T5(EDC_H_BIST_CMD_A, idx);
208 edc_bist_cmd_addr_reg = EDC_REG_T5(EDC_H_BIST_CMD_ADDR_A, idx);
209 edc_bist_cmd_len_reg = EDC_REG_T5(EDC_H_BIST_CMD_LEN_A, idx);
210 edc_bist_cmd_data_pattern = EDC_REG_T5(EDC_H_BIST_DATA_PATTERN_A, idx);
211 edc_bist_status_rdata_reg = EDC_REG_T5(EDC_H_BIST_STATUS_RDATA_A, idx);
212#undef EDC_REG_T5
213#undef EDC_STRIDE_T5
214
215 if (csio_rd_reg32(hw, edc_bist_cmd_reg) & START_BIST_F)
216 return -EBUSY;
217 csio_wr_reg32(hw, addr & ~0x3fU, edc_bist_cmd_addr_reg);
218 csio_wr_reg32(hw, 64, edc_bist_cmd_len_reg);
219 csio_wr_reg32(hw, 0xc, edc_bist_cmd_data_pattern);
220 csio_wr_reg32(hw, BIST_OPCODE_V(1) | START_BIST_F | BIST_CMD_GAP_V(1),
221 edc_bist_cmd_reg);
222 i = csio_hw_wait_op_done_val(hw, edc_bist_cmd_reg, START_BIST_F,
223 0, 10, 1, NULL);
224 if (i)
225 return i;
226
227#define EDC_DATA(i) (EDC_BIST_STATUS_REG(EDC_BIST_STATUS_RDATA_A, i) + idx)
228
229 for (i = 15; i >= 0; i--)
230 *data++ = htonl(csio_rd_reg32(hw, EDC_DATA(i)));
231 if (ecc)
232 *ecc = csio_rd_reg64(hw, EDC_DATA(16));
233#undef EDC_DATA
234 return 0;
235}
236
237/*
238 * csio_t5_memory_rw - read/write EDC 0, EDC 1 or MC via PCIE memory window
239 * @hw: the csio_hw
240 * @win: PCI-E memory Window to use
241 * @mtype: memory type: MEM_EDC0, MEM_EDC1, MEM_MC0 (or MEM_MC) or MEM_MC1
242 * @addr: address within indicated memory type
243 * @len: amount of memory to transfer
244 * @buf: host memory buffer
245 * @dir: direction of transfer 1 => read, 0 => write
246 *
247 * Reads/writes an [almost] arbitrary memory region in the firmware: the
248 * firmware memory address, length and host buffer must be aligned on
249 * 32-bit boudaries. The memory is transferred as a raw byte sequence
250 * from/to the firmware's memory. If this memory contains data
251 * structures which contain multi-byte integers, it's the callers
252 * responsibility to perform appropriate byte order conversions.
253 */
254static int
255csio_t5_memory_rw(struct csio_hw *hw, u32 win, int mtype, u32 addr,
256 u32 len, uint32_t *buf, int dir)
257{
258 u32 pos, start, offset, memoffset;
259 u32 edc_size, mc_size, win_pf, mem_reg, mem_aperture, mem_base;
260
261 /*
262 * Argument sanity checks ...
263 */
264 if ((addr & 0x3) || (len & 0x3))
265 return -EINVAL;
266
267 /* Offset into the region of memory which is being accessed
268 * MEM_EDC0 = 0
269 * MEM_EDC1 = 1
270 * MEM_MC = 2 -- T4
271 * MEM_MC0 = 2 -- For T5
272 * MEM_MC1 = 3 -- For T5
273 */
274 edc_size = EDRAM0_SIZE_G(csio_rd_reg32(hw, MA_EDRAM0_BAR_A));
275 if (mtype != MEM_MC1)
276 memoffset = (mtype * (edc_size * 1024 * 1024));
277 else {
278 mc_size = EXT_MEM_SIZE_G(csio_rd_reg32(hw,
279 MA_EXT_MEMORY_BAR_A));
280 memoffset = (MEM_MC0 * edc_size + mc_size) * 1024 * 1024;
281 }
282
283 /* Determine the PCIE_MEM_ACCESS_OFFSET */
284 addr = addr + memoffset;
285
286 /*
287 * Each PCI-E Memory Window is programmed with a window size -- or
288 * "aperture" -- which controls the granularity of its mapping onto
289 * adapter memory. We need to grab that aperture in order to know
290 * how to use the specified window. The window is also programmed
291 * with the base address of the Memory Window in BAR0's address
292 * space. For T4 this is an absolute PCI-E Bus Address. For T5
293 * the address is relative to BAR0.
294 */
295 mem_reg = csio_rd_reg32(hw,
296 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN_A, win));
297 mem_aperture = 1 << (WINDOW_V(mem_reg) + 10);
298 mem_base = PCIEOFST_G(mem_reg) << 10;
299
300 start = addr & ~(mem_aperture-1);
301 offset = addr - start;
302 win_pf = PFNUM_V(hw->pfn);
303
304 csio_dbg(hw, "csio_t5_memory_rw: mem_reg: 0x%x, mem_aperture: 0x%x\n",
305 mem_reg, mem_aperture);
306 csio_dbg(hw, "csio_t5_memory_rw: mem_base: 0x%x, mem_offset: 0x%x\n",
307 mem_base, memoffset);
308 csio_dbg(hw, "csio_t5_memory_rw: start:0x%x, offset:0x%x, win_pf:%d\n",
309 start, offset, win_pf);
310 csio_dbg(hw, "csio_t5_memory_rw: mtype: %d, addr: 0x%x, len: %d\n",
311 mtype, addr, len);
312
313 for (pos = start; len > 0; pos += mem_aperture, offset = 0) {
314 /*
315 * Move PCI-E Memory Window to our current transfer
316 * position. Read it back to ensure that changes propagate
317 * before we attempt to use the new value.
318 */
319 csio_wr_reg32(hw, pos | win_pf,
320 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET_A, win));
321 csio_rd_reg32(hw,
322 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET_A, win));
323
324 while (offset < mem_aperture && len > 0) {
325 if (dir)
326 *buf++ = csio_rd_reg32(hw, mem_base + offset);
327 else
328 csio_wr_reg32(hw, *buf++, mem_base + offset);
329
330 offset += sizeof(__be32);
331 len -= sizeof(__be32);
332 }
333 }
334 return 0;
335}
336
337/*
338 * csio_t5_dfs_create_ext_mem - setup debugfs for MC0 or MC1 to read the values
339 * @hw: the csio_hw
340 *
341 * This function creates files in the debugfs with external memory region
342 * MC0 & MC1.
343 */
344static void
345csio_t5_dfs_create_ext_mem(struct csio_hw *hw)
346{
347 u32 size;
348 int i = csio_rd_reg32(hw, MA_TARGET_MEM_ENABLE_A);
349
350 if (i & EXT_MEM_ENABLE_F) {
351 size = csio_rd_reg32(hw, MA_EXT_MEMORY_BAR_A);
352 csio_add_debugfs_mem(hw, "mc0", MEM_MC0,
353 EXT_MEM_SIZE_G(size));
354 }
355 if (i & EXT_MEM1_ENABLE_F) {
356 size = csio_rd_reg32(hw, MA_EXT_MEMORY1_BAR_A);
357 csio_add_debugfs_mem(hw, "mc1", MEM_MC1,
358 EXT_MEM_SIZE_G(size));
359 }
360}
361
362/* T5 adapter specific function */
363struct csio_hw_chip_ops t5_ops = {
364 .chip_set_mem_win = csio_t5_set_mem_win,
365 .chip_pcie_intr_handler = csio_t5_pcie_intr_handler,
366 .chip_flash_cfg_addr = csio_t5_flash_cfg_addr,
367 .chip_mc_read = csio_t5_mc_read,
368 .chip_edc_read = csio_t5_edc_read,
369 .chip_memory_rw = csio_t5_memory_rw,
370 .chip_dfs_create_ext_mem = csio_t5_dfs_create_ext_mem,
371};