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1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (c) 2017, The Linux Foundation. All rights reserved.
4 */
5
6#ifndef QCOM_PHY_QMP_H_
7#define QCOM_PHY_QMP_H_
8
9/* Only for QMP V2 PHY - QSERDES COM registers */
10#define QSERDES_COM_BG_TIMER 0x00c
11#define QSERDES_COM_SSC_EN_CENTER 0x010
12#define QSERDES_COM_SSC_ADJ_PER1 0x014
13#define QSERDES_COM_SSC_ADJ_PER2 0x018
14#define QSERDES_COM_SSC_PER1 0x01c
15#define QSERDES_COM_SSC_PER2 0x020
16#define QSERDES_COM_SSC_STEP_SIZE1 0x024
17#define QSERDES_COM_SSC_STEP_SIZE2 0x028
18#define QSERDES_COM_BIAS_EN_CLKBUFLR_EN 0x034
19#define QSERDES_COM_CLK_ENABLE1 0x038
20#define QSERDES_COM_SYS_CLK_CTRL 0x03c
21#define QSERDES_COM_SYSCLK_BUF_ENABLE 0x040
22#define QSERDES_COM_PLL_IVCO 0x048
23#define QSERDES_COM_LOCK_CMP1_MODE0 0x04c
24#define QSERDES_COM_LOCK_CMP2_MODE0 0x050
25#define QSERDES_COM_LOCK_CMP3_MODE0 0x054
26#define QSERDES_COM_LOCK_CMP1_MODE1 0x058
27#define QSERDES_COM_LOCK_CMP2_MODE1 0x05c
28#define QSERDES_COM_LOCK_CMP3_MODE1 0x060
29#define QSERDES_COM_BG_TRIM 0x070
30#define QSERDES_COM_CLK_EP_DIV 0x074
31#define QSERDES_COM_CP_CTRL_MODE0 0x078
32#define QSERDES_COM_CP_CTRL_MODE1 0x07c
33#define QSERDES_COM_PLL_RCTRL_MODE0 0x084
34#define QSERDES_COM_PLL_RCTRL_MODE1 0x088
35#define QSERDES_COM_PLL_CCTRL_MODE0 0x090
36#define QSERDES_COM_PLL_CCTRL_MODE1 0x094
37#define QSERDES_COM_BIAS_EN_CTRL_BY_PSM 0x0a8
38#define QSERDES_COM_SYSCLK_EN_SEL 0x0ac
39#define QSERDES_COM_RESETSM_CNTRL 0x0b4
40#define QSERDES_COM_RESTRIM_CTRL 0x0bc
41#define QSERDES_COM_RESCODE_DIV_NUM 0x0c4
42#define QSERDES_COM_LOCK_CMP_EN 0x0c8
43#define QSERDES_COM_LOCK_CMP_CFG 0x0cc
44#define QSERDES_COM_DEC_START_MODE0 0x0d0
45#define QSERDES_COM_DEC_START_MODE1 0x0d4
46#define QSERDES_COM_DIV_FRAC_START1_MODE0 0x0dc
47#define QSERDES_COM_DIV_FRAC_START2_MODE0 0x0e0
48#define QSERDES_COM_DIV_FRAC_START3_MODE0 0x0e4
49#define QSERDES_COM_DIV_FRAC_START1_MODE1 0x0e8
50#define QSERDES_COM_DIV_FRAC_START2_MODE1 0x0ec
51#define QSERDES_COM_DIV_FRAC_START3_MODE1 0x0f0
52#define QSERDES_COM_INTEGLOOP_GAIN0_MODE0 0x108
53#define QSERDES_COM_INTEGLOOP_GAIN1_MODE0 0x10c
54#define QSERDES_COM_INTEGLOOP_GAIN0_MODE1 0x110
55#define QSERDES_COM_INTEGLOOP_GAIN1_MODE1 0x114
56#define QSERDES_COM_VCO_TUNE_CTRL 0x124
57#define QSERDES_COM_VCO_TUNE_MAP 0x128
58#define QSERDES_COM_VCO_TUNE1_MODE0 0x12c
59#define QSERDES_COM_VCO_TUNE2_MODE0 0x130
60#define QSERDES_COM_VCO_TUNE1_MODE1 0x134
61#define QSERDES_COM_VCO_TUNE2_MODE1 0x138
62#define QSERDES_COM_VCO_TUNE_TIMER1 0x144
63#define QSERDES_COM_VCO_TUNE_TIMER2 0x148
64#define QSERDES_COM_BG_CTRL 0x170
65#define QSERDES_COM_CLK_SELECT 0x174
66#define QSERDES_COM_HSCLK_SEL 0x178
67#define QSERDES_COM_CORECLK_DIV 0x184
68#define QSERDES_COM_CORE_CLK_EN 0x18c
69#define QSERDES_COM_C_READY_STATUS 0x190
70#define QSERDES_COM_CMN_CONFIG 0x194
71#define QSERDES_COM_SVS_MODE_CLK_SEL 0x19c
72#define QSERDES_COM_DEBUG_BUS0 0x1a0
73#define QSERDES_COM_DEBUG_BUS1 0x1a4
74#define QSERDES_COM_DEBUG_BUS2 0x1a8
75#define QSERDES_COM_DEBUG_BUS3 0x1ac
76#define QSERDES_COM_DEBUG_BUS_SEL 0x1b0
77#define QSERDES_COM_CORECLK_DIV_MODE1 0x1bc
78
79/* Only for QMP V2 PHY - TX registers */
80#define QSERDES_TX_RES_CODE_LANE_OFFSET 0x054
81#define QSERDES_TX_DEBUG_BUS_SEL 0x064
82#define QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN 0x068
83#define QSERDES_TX_LANE_MODE 0x094
84#define QSERDES_TX_RCV_DETECT_LVL_2 0x0ac
85
86/* Only for QMP V2 PHY - RX registers */
87#define QSERDES_RX_UCDR_SO_GAIN_HALF 0x010
88#define QSERDES_RX_UCDR_SO_GAIN 0x01c
89#define QSERDES_RX_UCDR_FASTLOCK_FO_GAIN 0x040
90#define QSERDES_RX_UCDR_SO_SATURATION_AND_ENABLE 0x048
91#define QSERDES_RX_RX_TERM_BW 0x090
92#define QSERDES_RX_RX_EQ_GAIN1_LSB 0x0c4
93#define QSERDES_RX_RX_EQ_GAIN1_MSB 0x0c8
94#define QSERDES_RX_RX_EQ_GAIN2_LSB 0x0cc
95#define QSERDES_RX_RX_EQ_GAIN2_MSB 0x0d0
96#define QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2 0x0d8
97#define QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3 0x0dc
98#define QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4 0x0e0
99#define QSERDES_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x108
100#define QSERDES_RX_RX_OFFSET_ADAPTOR_CNTRL2 0x10c
101#define QSERDES_RX_SIGDET_ENABLES 0x110
102#define QSERDES_RX_SIGDET_CNTRL 0x114
103#define QSERDES_RX_SIGDET_LVL 0x118
104#define QSERDES_RX_SIGDET_DEGLITCH_CNTRL 0x11c
105#define QSERDES_RX_RX_BAND 0x120
106#define QSERDES_RX_RX_INTERFACE_MODE 0x12c
107
108/* Only for QMP V2 PHY - PCS registers */
109#define QPHY_POWER_DOWN_CONTROL 0x04
110#define QPHY_TXDEEMPH_M6DB_V0 0x24
111#define QPHY_TXDEEMPH_M3P5DB_V0 0x28
112#define QPHY_ENDPOINT_REFCLK_DRIVE 0x54
113#define QPHY_RX_IDLE_DTCT_CNTRL 0x58
114#define QPHY_POWER_STATE_CONFIG1 0x60
115#define QPHY_POWER_STATE_CONFIG2 0x64
116#define QPHY_POWER_STATE_CONFIG4 0x6c
117#define QPHY_LOCK_DETECT_CONFIG1 0x80
118#define QPHY_LOCK_DETECT_CONFIG2 0x84
119#define QPHY_LOCK_DETECT_CONFIG3 0x88
120#define QPHY_PWRUP_RESET_DLY_TIME_AUXCLK 0xa0
121#define QPHY_LP_WAKEUP_DLY_TIME_AUXCLK 0xa4
122#define QPHY_PLL_LOCK_CHK_DLY_TIME_AUXCLK_LSB 0x1A8
123#define QPHY_OSC_DTCT_ACTIONS 0x1AC
124#define QPHY_RX_SIGDET_LVL 0x1D8
125#define QPHY_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB 0x1DC
126#define QPHY_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB 0x1E0
127
128/* Only for QMP V3 PHY - DP COM registers */
129#define QPHY_V3_DP_COM_PHY_MODE_CTRL 0x00
130#define QPHY_V3_DP_COM_SW_RESET 0x04
131#define QPHY_V3_DP_COM_POWER_DOWN_CTRL 0x08
132#define QPHY_V3_DP_COM_SWI_CTRL 0x0c
133#define QPHY_V3_DP_COM_TYPEC_CTRL 0x10
134#define QPHY_V3_DP_COM_TYPEC_PWRDN_CTRL 0x14
135#define QPHY_V3_DP_COM_RESET_OVRD_CTRL 0x1c
136
137/* Only for QMP V3 PHY - QSERDES COM registers */
138#define QSERDES_V3_COM_BG_TIMER 0x00c
139#define QSERDES_V3_COM_SSC_EN_CENTER 0x010
140#define QSERDES_V3_COM_SSC_ADJ_PER1 0x014
141#define QSERDES_V3_COM_SSC_ADJ_PER2 0x018
142#define QSERDES_V3_COM_SSC_PER1 0x01c
143#define QSERDES_V3_COM_SSC_PER2 0x020
144#define QSERDES_V3_COM_SSC_STEP_SIZE1 0x024
145#define QSERDES_V3_COM_SSC_STEP_SIZE2 0x028
146#define QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN 0x034
147#define QSERDES_V3_COM_CLK_ENABLE1 0x038
148#define QSERDES_V3_COM_SYS_CLK_CTRL 0x03c
149#define QSERDES_V3_COM_SYSCLK_BUF_ENABLE 0x040
150#define QSERDES_V3_COM_PLL_IVCO 0x048
151#define QSERDES_V3_COM_LOCK_CMP1_MODE0 0x098
152#define QSERDES_V3_COM_LOCK_CMP2_MODE0 0x09c
153#define QSERDES_V3_COM_LOCK_CMP3_MODE0 0x0a0
154#define QSERDES_V3_COM_LOCK_CMP1_MODE1 0x0a4
155#define QSERDES_V3_COM_LOCK_CMP2_MODE1 0x0a8
156#define QSERDES_V3_COM_LOCK_CMP3_MODE1 0x0ac
157#define QSERDES_V3_COM_CLK_EP_DIV 0x05c
158#define QSERDES_V3_COM_CP_CTRL_MODE0 0x060
159#define QSERDES_V3_COM_CP_CTRL_MODE1 0x064
160#define QSERDES_V3_COM_PLL_RCTRL_MODE0 0x068
161#define QSERDES_V3_COM_PLL_RCTRL_MODE1 0x06c
162#define QSERDES_V3_COM_PLL_CCTRL_MODE0 0x070
163#define QSERDES_V3_COM_PLL_CCTRL_MODE1 0x074
164#define QSERDES_V3_COM_SYSCLK_EN_SEL 0x080
165#define QSERDES_V3_COM_RESETSM_CNTRL 0x088
166#define QSERDES_V3_COM_RESETSM_CNTRL2 0x08c
167#define QSERDES_V3_COM_LOCK_CMP_EN 0x090
168#define QSERDES_V3_COM_LOCK_CMP_CFG 0x094
169#define QSERDES_V3_COM_DEC_START_MODE0 0x0b0
170#define QSERDES_V3_COM_DEC_START_MODE1 0x0b4
171#define QSERDES_V3_COM_DIV_FRAC_START1_MODE0 0x0b8
172#define QSERDES_V3_COM_DIV_FRAC_START2_MODE0 0x0bc
173#define QSERDES_V3_COM_DIV_FRAC_START3_MODE0 0x0c0
174#define QSERDES_V3_COM_DIV_FRAC_START1_MODE1 0x0c4
175#define QSERDES_V3_COM_DIV_FRAC_START2_MODE1 0x0c8
176#define QSERDES_V3_COM_DIV_FRAC_START3_MODE1 0x0cc
177#define QSERDES_V3_COM_INTEGLOOP_INITVAL 0x0d0
178#define QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0 0x0d8
179#define QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0 0x0dc
180#define QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE1 0x0e0
181#define QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE1 0x0e4
182#define QSERDES_V3_COM_VCO_TUNE_CTRL 0x0ec
183#define QSERDES_V3_COM_VCO_TUNE_MAP 0x0f0
184#define QSERDES_V3_COM_VCO_TUNE1_MODE0 0x0f4
185#define QSERDES_V3_COM_VCO_TUNE2_MODE0 0x0f8
186#define QSERDES_V3_COM_VCO_TUNE1_MODE1 0x0fc
187#define QSERDES_V3_COM_VCO_TUNE2_MODE1 0x100
188#define QSERDES_V3_COM_VCO_TUNE_INITVAL1 0x104
189#define QSERDES_V3_COM_VCO_TUNE_INITVAL2 0x108
190#define QSERDES_V3_COM_VCO_TUNE_TIMER1 0x11c
191#define QSERDES_V3_COM_VCO_TUNE_TIMER2 0x120
192#define QSERDES_V3_COM_CLK_SELECT 0x138
193#define QSERDES_V3_COM_HSCLK_SEL 0x13c
194#define QSERDES_V3_COM_CORECLK_DIV_MODE0 0x148
195#define QSERDES_V3_COM_CORECLK_DIV_MODE1 0x14c
196#define QSERDES_V3_COM_CORE_CLK_EN 0x154
197#define QSERDES_V3_COM_C_READY_STATUS 0x158
198#define QSERDES_V3_COM_CMN_CONFIG 0x15c
199#define QSERDES_V3_COM_SVS_MODE_CLK_SEL 0x164
200#define QSERDES_V3_COM_DEBUG_BUS0 0x168
201#define QSERDES_V3_COM_DEBUG_BUS1 0x16c
202#define QSERDES_V3_COM_DEBUG_BUS2 0x170
203#define QSERDES_V3_COM_DEBUG_BUS3 0x174
204#define QSERDES_V3_COM_DEBUG_BUS_SEL 0x178
205#define QSERDES_V3_COM_CMN_MODE 0x184
206
207/* Only for QMP V3 PHY - TX registers */
208#define QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX 0x044
209#define QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX 0x048
210#define QSERDES_V3_TX_DEBUG_BUS_SEL 0x058
211#define QSERDES_V3_TX_HIGHZ_DRVR_EN 0x060
212#define QSERDES_V3_TX_LANE_MODE_1 0x08c
213#define QSERDES_V3_TX_RCV_DETECT_LVL_2 0x0a4
214
215/* Only for QMP V3 PHY - RX registers */
216#define QSERDES_V3_RX_UCDR_FO_GAIN 0x008
217#define QSERDES_V3_RX_UCDR_SO_GAIN_HALF 0x00c
218#define QSERDES_V3_RX_UCDR_SO_GAIN 0x014
219#define QSERDES_V3_RX_UCDR_SVS_SO_GAIN_HALF 0x024
220#define QSERDES_V3_RX_UCDR_SVS_SO_GAIN_QUARTER 0x028
221#define QSERDES_V3_RX_UCDR_SVS_SO_GAIN 0x02c
222#define QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN 0x030
223#define QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE 0x034
224#define QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW 0x03c
225#define QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_HIGH 0x040
226#define QSERDES_V3_RX_UCDR_PI_CONTROLS 0x044
227#define QSERDES_V3_RX_RX_TERM_BW 0x07c
228#define QSERDES_V3_RX_VGA_CAL_CNTRL1 0x0bc
229#define QSERDES_V3_RX_VGA_CAL_CNTRL2 0x0c0
230#define QSERDES_V3_RX_RX_EQ_GAIN2_LSB 0x0c8
231#define QSERDES_V3_RX_RX_EQ_GAIN2_MSB 0x0cc
232#define QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2 0x0d4
233#define QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3 0x0d8
234#define QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4 0x0dc
235#define QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x0f8
236#define QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2 0x0fc
237#define QSERDES_V3_RX_SIGDET_ENABLES 0x100
238#define QSERDES_V3_RX_SIGDET_CNTRL 0x104
239#define QSERDES_V3_RX_SIGDET_LVL 0x108
240#define QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL 0x10c
241#define QSERDES_V3_RX_RX_BAND 0x110
242#define QSERDES_V3_RX_RX_INTERFACE_MODE 0x11c
243#define QSERDES_V3_RX_RX_MODE_00 0x164
244#define QSERDES_V3_RX_RX_MODE_01 0x168
245
246/* Only for QMP V3 PHY - PCS registers */
247#define QPHY_V3_PCS_POWER_DOWN_CONTROL 0x004
248#define QPHY_V3_PCS_TXMGN_V0 0x00c
249#define QPHY_V3_PCS_TXMGN_V1 0x010
250#define QPHY_V3_PCS_TXMGN_V2 0x014
251#define QPHY_V3_PCS_TXMGN_V3 0x018
252#define QPHY_V3_PCS_TXMGN_V4 0x01c
253#define QPHY_V3_PCS_TXMGN_LS 0x020
254#define QPHY_V3_PCS_TX_LARGE_AMP_DRV_LVL 0x02c
255#define QPHY_V3_PCS_TX_SMALL_AMP_DRV_LVL 0x034
256#define QPHY_V3_PCS_TXDEEMPH_M6DB_V0 0x024
257#define QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0 0x028
258#define QPHY_V3_PCS_TXDEEMPH_M6DB_V1 0x02c
259#define QPHY_V3_PCS_TXDEEMPH_M3P5DB_V1 0x030
260#define QPHY_V3_PCS_TXDEEMPH_M6DB_V2 0x034
261#define QPHY_V3_PCS_TXDEEMPH_M3P5DB_V2 0x038
262#define QPHY_V3_PCS_TXDEEMPH_M6DB_V3 0x03c
263#define QPHY_V3_PCS_TXDEEMPH_M3P5DB_V3 0x040
264#define QPHY_V3_PCS_TXDEEMPH_M6DB_V4 0x044
265#define QPHY_V3_PCS_TXDEEMPH_M3P5DB_V4 0x048
266#define QPHY_V3_PCS_TXDEEMPH_M6DB_LS 0x04c
267#define QPHY_V3_PCS_TXDEEMPH_M3P5DB_LS 0x050
268#define QPHY_V3_PCS_ENDPOINT_REFCLK_DRIVE 0x054
269#define QPHY_V3_PCS_RX_IDLE_DTCT_CNTRL 0x058
270#define QPHY_V3_PCS_RATE_SLEW_CNTRL 0x05c
271#define QPHY_V3_PCS_POWER_STATE_CONFIG1 0x060
272#define QPHY_V3_PCS_POWER_STATE_CONFIG2 0x064
273#define QPHY_V3_PCS_POWER_STATE_CONFIG4 0x06c
274#define QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L 0x070
275#define QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H 0x074
276#define QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L 0x078
277#define QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H 0x07c
278#define QPHY_V3_PCS_LOCK_DETECT_CONFIG1 0x080
279#define QPHY_V3_PCS_LOCK_DETECT_CONFIG2 0x084
280#define QPHY_V3_PCS_LOCK_DETECT_CONFIG3 0x088
281#define QPHY_V3_PCS_TSYNC_RSYNC_TIME 0x08c
282#define QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK 0x0a0
283#define QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK 0x0a4
284#define QPHY_V3_PCS_PLL_LOCK_CHK_DLY_TIME 0x0a8
285#define QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK 0x0b0
286#define QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME 0x0b8
287#define QPHY_V3_PCS_RXEQTRAINING_RUN_TIME 0x0bc
288#define QPHY_V3_PCS_FLL_CNTRL1 0x0c4
289#define QPHY_V3_PCS_FLL_CNTRL2 0x0c8
290#define QPHY_V3_PCS_FLL_CNT_VAL_L 0x0cc
291#define QPHY_V3_PCS_FLL_CNT_VAL_H_TOL 0x0d0
292#define QPHY_V3_PCS_FLL_MAN_CODE 0x0d4
293#define QPHY_V3_PCS_RX_SYM_RESYNC_CTRL 0x134
294#define QPHY_V3_PCS_RX_MIN_HIBERN8_TIME 0x138
295#define QPHY_V3_PCS_RX_SIGDET_CTRL1 0x13c
296#define QPHY_V3_PCS_RX_SIGDET_CTRL2 0x140
297#define QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK_MSB 0x1a8
298#define QPHY_V3_PCS_OSC_DTCT_ACTIONS 0x1ac
299#define QPHY_V3_PCS_SIGDET_CNTRL 0x1b0
300#define QPHY_V3_PCS_TX_MID_TERM_CTRL1 0x1bc
301#define QPHY_V3_PCS_MULTI_LANE_CTRL1 0x1c4
302#define QPHY_V3_PCS_RX_SIGDET_LVL 0x1d8
303#define QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB 0x1dc
304#define QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB 0x1e0
305#define QPHY_V3_PCS_REFGEN_REQ_CONFIG1 0x20c
306#define QPHY_V3_PCS_REFGEN_REQ_CONFIG2 0x210
307
308/* Only for QMP V3 PHY - PCS_MISC registers */
309#define QPHY_V3_PCS_MISC_CLAMP_ENABLE 0x0c
310#define QPHY_V3_PCS_MISC_OSC_DTCT_CONFIG2 0x2c
311#define QPHY_V3_PCS_MISC_PCIE_INT_AUX_CLK_CONFIG1 0x44
312#define QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG2 0x54
313#define QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG4 0x5c
314#define QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG5 0x60
315
316#endif