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1/*
2 * PCI Express PCI Hot Plug Driver
3 *
4 * Copyright (C) 1995,2001 Compaq Computer Corporation
5 * Copyright (C) 2001 Greg Kroah-Hartman (greg@kroah.com)
6 * Copyright (C) 2001 IBM Corp.
7 * Copyright (C) 2003-2004 Intel Corporation
8 *
9 * All rights reserved.
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or (at
14 * your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful, but
17 * WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
19 * NON INFRINGEMENT. See the GNU General Public License for more
20 * details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
25 *
26 * Send feedback to <greg@kroah.com>,<kristen.c.accardi@intel.com>
27 *
28 */
29
30#include <linux/kernel.h>
31#include <linux/module.h>
32#include <linux/types.h>
33#include <linux/signal.h>
34#include <linux/jiffies.h>
35#include <linux/timer.h>
36#include <linux/pci.h>
37#include <linux/interrupt.h>
38#include <linux/time.h>
39#include <linux/slab.h>
40
41#include "../pci.h"
42#include "pciehp.h"
43
44static inline int pciehp_readw(struct controller *ctrl, int reg, u16 *value)
45{
46 struct pci_dev *dev = ctrl->pcie->port;
47 return pci_read_config_word(dev, pci_pcie_cap(dev) + reg, value);
48}
49
50static inline int pciehp_readl(struct controller *ctrl, int reg, u32 *value)
51{
52 struct pci_dev *dev = ctrl->pcie->port;
53 return pci_read_config_dword(dev, pci_pcie_cap(dev) + reg, value);
54}
55
56static inline int pciehp_writew(struct controller *ctrl, int reg, u16 value)
57{
58 struct pci_dev *dev = ctrl->pcie->port;
59 return pci_write_config_word(dev, pci_pcie_cap(dev) + reg, value);
60}
61
62static inline int pciehp_writel(struct controller *ctrl, int reg, u32 value)
63{
64 struct pci_dev *dev = ctrl->pcie->port;
65 return pci_write_config_dword(dev, pci_pcie_cap(dev) + reg, value);
66}
67
68/* Power Control Command */
69#define POWER_ON 0
70#define POWER_OFF PCI_EXP_SLTCTL_PCC
71
72static irqreturn_t pcie_isr(int irq, void *dev_id);
73static void start_int_poll_timer(struct controller *ctrl, int sec);
74
75/* This is the interrupt polling timeout function. */
76static void int_poll_timeout(unsigned long data)
77{
78 struct controller *ctrl = (struct controller *)data;
79
80 /* Poll for interrupt events. regs == NULL => polling */
81 pcie_isr(0, ctrl);
82
83 init_timer(&ctrl->poll_timer);
84 if (!pciehp_poll_time)
85 pciehp_poll_time = 2; /* default polling interval is 2 sec */
86
87 start_int_poll_timer(ctrl, pciehp_poll_time);
88}
89
90/* This function starts the interrupt polling timer. */
91static void start_int_poll_timer(struct controller *ctrl, int sec)
92{
93 /* Clamp to sane value */
94 if ((sec <= 0) || (sec > 60))
95 sec = 2;
96
97 ctrl->poll_timer.function = &int_poll_timeout;
98 ctrl->poll_timer.data = (unsigned long)ctrl;
99 ctrl->poll_timer.expires = jiffies + sec * HZ;
100 add_timer(&ctrl->poll_timer);
101}
102
103static inline int pciehp_request_irq(struct controller *ctrl)
104{
105 int retval, irq = ctrl->pcie->irq;
106
107 /* Install interrupt polling timer. Start with 10 sec delay */
108 if (pciehp_poll_mode) {
109 init_timer(&ctrl->poll_timer);
110 start_int_poll_timer(ctrl, 10);
111 return 0;
112 }
113
114 /* Installs the interrupt handler */
115 retval = request_irq(irq, pcie_isr, IRQF_SHARED, MY_NAME, ctrl);
116 if (retval)
117 ctrl_err(ctrl, "Cannot get irq %d for the hotplug controller\n",
118 irq);
119 return retval;
120}
121
122static inline void pciehp_free_irq(struct controller *ctrl)
123{
124 if (pciehp_poll_mode)
125 del_timer_sync(&ctrl->poll_timer);
126 else
127 free_irq(ctrl->pcie->irq, ctrl);
128}
129
130static int pcie_poll_cmd(struct controller *ctrl)
131{
132 u16 slot_status;
133 int err, timeout = 1000;
134
135 err = pciehp_readw(ctrl, PCI_EXP_SLTSTA, &slot_status);
136 if (!err && (slot_status & PCI_EXP_SLTSTA_CC)) {
137 pciehp_writew(ctrl, PCI_EXP_SLTSTA, PCI_EXP_SLTSTA_CC);
138 return 1;
139 }
140 while (timeout > 0) {
141 msleep(10);
142 timeout -= 10;
143 err = pciehp_readw(ctrl, PCI_EXP_SLTSTA, &slot_status);
144 if (!err && (slot_status & PCI_EXP_SLTSTA_CC)) {
145 pciehp_writew(ctrl, PCI_EXP_SLTSTA, PCI_EXP_SLTSTA_CC);
146 return 1;
147 }
148 }
149 return 0; /* timeout */
150}
151
152static void pcie_wait_cmd(struct controller *ctrl, int poll)
153{
154 unsigned int msecs = pciehp_poll_mode ? 2500 : 1000;
155 unsigned long timeout = msecs_to_jiffies(msecs);
156 int rc;
157
158 if (poll)
159 rc = pcie_poll_cmd(ctrl);
160 else
161 rc = wait_event_timeout(ctrl->queue, !ctrl->cmd_busy, timeout);
162 if (!rc)
163 ctrl_dbg(ctrl, "Command not completed in 1000 msec\n");
164}
165
166/**
167 * pcie_write_cmd - Issue controller command
168 * @ctrl: controller to which the command is issued
169 * @cmd: command value written to slot control register
170 * @mask: bitmask of slot control register to be modified
171 */
172static int pcie_write_cmd(struct controller *ctrl, u16 cmd, u16 mask)
173{
174 int retval = 0;
175 u16 slot_status;
176 u16 slot_ctrl;
177
178 mutex_lock(&ctrl->ctrl_lock);
179
180 retval = pciehp_readw(ctrl, PCI_EXP_SLTSTA, &slot_status);
181 if (retval) {
182 ctrl_err(ctrl, "%s: Cannot read SLOTSTATUS register\n",
183 __func__);
184 goto out;
185 }
186
187 if (slot_status & PCI_EXP_SLTSTA_CC) {
188 if (!ctrl->no_cmd_complete) {
189 /*
190 * After 1 sec and CMD_COMPLETED still not set, just
191 * proceed forward to issue the next command according
192 * to spec. Just print out the error message.
193 */
194 ctrl_dbg(ctrl, "CMD_COMPLETED not clear after 1 sec\n");
195 } else if (!NO_CMD_CMPL(ctrl)) {
196 /*
197 * This controller semms to notify of command completed
198 * event even though it supports none of power
199 * controller, attention led, power led and EMI.
200 */
201 ctrl_dbg(ctrl, "Unexpected CMD_COMPLETED. Need to "
202 "wait for command completed event.\n");
203 ctrl->no_cmd_complete = 0;
204 } else {
205 ctrl_dbg(ctrl, "Unexpected CMD_COMPLETED. Maybe "
206 "the controller is broken.\n");
207 }
208 }
209
210 retval = pciehp_readw(ctrl, PCI_EXP_SLTCTL, &slot_ctrl);
211 if (retval) {
212 ctrl_err(ctrl, "%s: Cannot read SLOTCTRL register\n", __func__);
213 goto out;
214 }
215
216 slot_ctrl &= ~mask;
217 slot_ctrl |= (cmd & mask);
218 ctrl->cmd_busy = 1;
219 smp_mb();
220 retval = pciehp_writew(ctrl, PCI_EXP_SLTCTL, slot_ctrl);
221 if (retval)
222 ctrl_err(ctrl, "Cannot write to SLOTCTRL register\n");
223
224 /*
225 * Wait for command completion.
226 */
227 if (!retval && !ctrl->no_cmd_complete) {
228 int poll = 0;
229 /*
230 * if hotplug interrupt is not enabled or command
231 * completed interrupt is not enabled, we need to poll
232 * command completed event.
233 */
234 if (!(slot_ctrl & PCI_EXP_SLTCTL_HPIE) ||
235 !(slot_ctrl & PCI_EXP_SLTCTL_CCIE))
236 poll = 1;
237 pcie_wait_cmd(ctrl, poll);
238 }
239 out:
240 mutex_unlock(&ctrl->ctrl_lock);
241 return retval;
242}
243
244static inline int check_link_active(struct controller *ctrl)
245{
246 u16 link_status;
247
248 if (pciehp_readw(ctrl, PCI_EXP_LNKSTA, &link_status))
249 return 0;
250 return !!(link_status & PCI_EXP_LNKSTA_DLLLA);
251}
252
253static void pcie_wait_link_active(struct controller *ctrl)
254{
255 int timeout = 1000;
256
257 if (check_link_active(ctrl))
258 return;
259 while (timeout > 0) {
260 msleep(10);
261 timeout -= 10;
262 if (check_link_active(ctrl))
263 return;
264 }
265 ctrl_dbg(ctrl, "Data Link Layer Link Active not set in 1000 msec\n");
266}
267
268int pciehp_check_link_status(struct controller *ctrl)
269{
270 u16 lnk_status;
271 int retval = 0;
272
273 /*
274 * Data Link Layer Link Active Reporting must be capable for
275 * hot-plug capable downstream port. But old controller might
276 * not implement it. In this case, we wait for 1000 ms.
277 */
278 if (ctrl->link_active_reporting)
279 pcie_wait_link_active(ctrl);
280 else
281 msleep(1000);
282
283 retval = pciehp_readw(ctrl, PCI_EXP_LNKSTA, &lnk_status);
284 if (retval) {
285 ctrl_err(ctrl, "Cannot read LNKSTATUS register\n");
286 return retval;
287 }
288
289 ctrl_dbg(ctrl, "%s: lnk_status = %x\n", __func__, lnk_status);
290 if ((lnk_status & PCI_EXP_LNKSTA_LT) ||
291 !(lnk_status & PCI_EXP_LNKSTA_NLW)) {
292 ctrl_err(ctrl, "Link Training Error occurs \n");
293 retval = -1;
294 return retval;
295 }
296
297 return retval;
298}
299
300int pciehp_get_attention_status(struct slot *slot, u8 *status)
301{
302 struct controller *ctrl = slot->ctrl;
303 u16 slot_ctrl;
304 u8 atten_led_state;
305 int retval = 0;
306
307 retval = pciehp_readw(ctrl, PCI_EXP_SLTCTL, &slot_ctrl);
308 if (retval) {
309 ctrl_err(ctrl, "%s: Cannot read SLOTCTRL register\n", __func__);
310 return retval;
311 }
312
313 ctrl_dbg(ctrl, "%s: SLOTCTRL %x, value read %x\n", __func__,
314 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_ctrl);
315
316 atten_led_state = (slot_ctrl & PCI_EXP_SLTCTL_AIC) >> 6;
317
318 switch (atten_led_state) {
319 case 0:
320 *status = 0xFF; /* Reserved */
321 break;
322 case 1:
323 *status = 1; /* On */
324 break;
325 case 2:
326 *status = 2; /* Blink */
327 break;
328 case 3:
329 *status = 0; /* Off */
330 break;
331 default:
332 *status = 0xFF;
333 break;
334 }
335
336 return 0;
337}
338
339int pciehp_get_power_status(struct slot *slot, u8 *status)
340{
341 struct controller *ctrl = slot->ctrl;
342 u16 slot_ctrl;
343 u8 pwr_state;
344 int retval = 0;
345
346 retval = pciehp_readw(ctrl, PCI_EXP_SLTCTL, &slot_ctrl);
347 if (retval) {
348 ctrl_err(ctrl, "%s: Cannot read SLOTCTRL register\n", __func__);
349 return retval;
350 }
351 ctrl_dbg(ctrl, "%s: SLOTCTRL %x value read %x\n", __func__,
352 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_ctrl);
353
354 pwr_state = (slot_ctrl & PCI_EXP_SLTCTL_PCC) >> 10;
355
356 switch (pwr_state) {
357 case 0:
358 *status = 1;
359 break;
360 case 1:
361 *status = 0;
362 break;
363 default:
364 *status = 0xFF;
365 break;
366 }
367
368 return retval;
369}
370
371int pciehp_get_latch_status(struct slot *slot, u8 *status)
372{
373 struct controller *ctrl = slot->ctrl;
374 u16 slot_status;
375 int retval;
376
377 retval = pciehp_readw(ctrl, PCI_EXP_SLTSTA, &slot_status);
378 if (retval) {
379 ctrl_err(ctrl, "%s: Cannot read SLOTSTATUS register\n",
380 __func__);
381 return retval;
382 }
383 *status = !!(slot_status & PCI_EXP_SLTSTA_MRLSS);
384 return 0;
385}
386
387int pciehp_get_adapter_status(struct slot *slot, u8 *status)
388{
389 struct controller *ctrl = slot->ctrl;
390 u16 slot_status;
391 int retval;
392
393 retval = pciehp_readw(ctrl, PCI_EXP_SLTSTA, &slot_status);
394 if (retval) {
395 ctrl_err(ctrl, "%s: Cannot read SLOTSTATUS register\n",
396 __func__);
397 return retval;
398 }
399 *status = !!(slot_status & PCI_EXP_SLTSTA_PDS);
400 return 0;
401}
402
403int pciehp_query_power_fault(struct slot *slot)
404{
405 struct controller *ctrl = slot->ctrl;
406 u16 slot_status;
407 int retval;
408
409 retval = pciehp_readw(ctrl, PCI_EXP_SLTSTA, &slot_status);
410 if (retval) {
411 ctrl_err(ctrl, "Cannot check for power fault\n");
412 return retval;
413 }
414 return !!(slot_status & PCI_EXP_SLTSTA_PFD);
415}
416
417int pciehp_set_attention_status(struct slot *slot, u8 value)
418{
419 struct controller *ctrl = slot->ctrl;
420 u16 slot_cmd;
421 u16 cmd_mask;
422
423 cmd_mask = PCI_EXP_SLTCTL_AIC;
424 switch (value) {
425 case 0 : /* turn off */
426 slot_cmd = 0x00C0;
427 break;
428 case 1: /* turn on */
429 slot_cmd = 0x0040;
430 break;
431 case 2: /* turn blink */
432 slot_cmd = 0x0080;
433 break;
434 default:
435 return -EINVAL;
436 }
437 ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
438 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_cmd);
439 return pcie_write_cmd(ctrl, slot_cmd, cmd_mask);
440}
441
442void pciehp_green_led_on(struct slot *slot)
443{
444 struct controller *ctrl = slot->ctrl;
445 u16 slot_cmd;
446 u16 cmd_mask;
447
448 slot_cmd = 0x0100;
449 cmd_mask = PCI_EXP_SLTCTL_PIC;
450 pcie_write_cmd(ctrl, slot_cmd, cmd_mask);
451 ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
452 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_cmd);
453}
454
455void pciehp_green_led_off(struct slot *slot)
456{
457 struct controller *ctrl = slot->ctrl;
458 u16 slot_cmd;
459 u16 cmd_mask;
460
461 slot_cmd = 0x0300;
462 cmd_mask = PCI_EXP_SLTCTL_PIC;
463 pcie_write_cmd(ctrl, slot_cmd, cmd_mask);
464 ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
465 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_cmd);
466}
467
468void pciehp_green_led_blink(struct slot *slot)
469{
470 struct controller *ctrl = slot->ctrl;
471 u16 slot_cmd;
472 u16 cmd_mask;
473
474 slot_cmd = 0x0200;
475 cmd_mask = PCI_EXP_SLTCTL_PIC;
476 pcie_write_cmd(ctrl, slot_cmd, cmd_mask);
477 ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
478 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_cmd);
479}
480
481int pciehp_power_on_slot(struct slot * slot)
482{
483 struct controller *ctrl = slot->ctrl;
484 u16 slot_cmd;
485 u16 cmd_mask;
486 u16 slot_status;
487 u16 lnk_status;
488 int retval = 0;
489
490 /* Clear sticky power-fault bit from previous power failures */
491 retval = pciehp_readw(ctrl, PCI_EXP_SLTSTA, &slot_status);
492 if (retval) {
493 ctrl_err(ctrl, "%s: Cannot read SLOTSTATUS register\n",
494 __func__);
495 return retval;
496 }
497 slot_status &= PCI_EXP_SLTSTA_PFD;
498 if (slot_status) {
499 retval = pciehp_writew(ctrl, PCI_EXP_SLTSTA, slot_status);
500 if (retval) {
501 ctrl_err(ctrl,
502 "%s: Cannot write to SLOTSTATUS register\n",
503 __func__);
504 return retval;
505 }
506 }
507 ctrl->power_fault_detected = 0;
508
509 slot_cmd = POWER_ON;
510 cmd_mask = PCI_EXP_SLTCTL_PCC;
511 retval = pcie_write_cmd(ctrl, slot_cmd, cmd_mask);
512 if (retval) {
513 ctrl_err(ctrl, "Write %x command failed!\n", slot_cmd);
514 return retval;
515 }
516 ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
517 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_cmd);
518
519 retval = pciehp_readw(ctrl, PCI_EXP_LNKSTA, &lnk_status);
520 if (retval) {
521 ctrl_err(ctrl, "%s: Cannot read LNKSTA register\n",
522 __func__);
523 return retval;
524 }
525 pcie_update_link_speed(ctrl->pcie->port->subordinate, lnk_status);
526
527 return retval;
528}
529
530int pciehp_power_off_slot(struct slot * slot)
531{
532 struct controller *ctrl = slot->ctrl;
533 u16 slot_cmd;
534 u16 cmd_mask;
535 int retval;
536
537 slot_cmd = POWER_OFF;
538 cmd_mask = PCI_EXP_SLTCTL_PCC;
539 retval = pcie_write_cmd(ctrl, slot_cmd, cmd_mask);
540 if (retval) {
541 ctrl_err(ctrl, "Write command failed!\n");
542 return retval;
543 }
544 ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
545 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_cmd);
546 return 0;
547}
548
549static irqreturn_t pcie_isr(int irq, void *dev_id)
550{
551 struct controller *ctrl = (struct controller *)dev_id;
552 struct slot *slot = ctrl->slot;
553 u16 detected, intr_loc;
554
555 /*
556 * In order to guarantee that all interrupt events are
557 * serviced, we need to re-inspect Slot Status register after
558 * clearing what is presumed to be the last pending interrupt.
559 */
560 intr_loc = 0;
561 do {
562 if (pciehp_readw(ctrl, PCI_EXP_SLTSTA, &detected)) {
563 ctrl_err(ctrl, "%s: Cannot read SLOTSTATUS\n",
564 __func__);
565 return IRQ_NONE;
566 }
567
568 detected &= (PCI_EXP_SLTSTA_ABP | PCI_EXP_SLTSTA_PFD |
569 PCI_EXP_SLTSTA_MRLSC | PCI_EXP_SLTSTA_PDC |
570 PCI_EXP_SLTSTA_CC);
571 detected &= ~intr_loc;
572 intr_loc |= detected;
573 if (!intr_loc)
574 return IRQ_NONE;
575 if (detected && pciehp_writew(ctrl, PCI_EXP_SLTSTA, intr_loc)) {
576 ctrl_err(ctrl, "%s: Cannot write to SLOTSTATUS\n",
577 __func__);
578 return IRQ_NONE;
579 }
580 } while (detected);
581
582 ctrl_dbg(ctrl, "%s: intr_loc %x\n", __func__, intr_loc);
583
584 /* Check Command Complete Interrupt Pending */
585 if (intr_loc & PCI_EXP_SLTSTA_CC) {
586 ctrl->cmd_busy = 0;
587 smp_mb();
588 wake_up(&ctrl->queue);
589 }
590
591 if (!(intr_loc & ~PCI_EXP_SLTSTA_CC))
592 return IRQ_HANDLED;
593
594 /* Check MRL Sensor Changed */
595 if (intr_loc & PCI_EXP_SLTSTA_MRLSC)
596 pciehp_handle_switch_change(slot);
597
598 /* Check Attention Button Pressed */
599 if (intr_loc & PCI_EXP_SLTSTA_ABP)
600 pciehp_handle_attention_button(slot);
601
602 /* Check Presence Detect Changed */
603 if (intr_loc & PCI_EXP_SLTSTA_PDC)
604 pciehp_handle_presence_change(slot);
605
606 /* Check Power Fault Detected */
607 if ((intr_loc & PCI_EXP_SLTSTA_PFD) && !ctrl->power_fault_detected) {
608 ctrl->power_fault_detected = 1;
609 pciehp_handle_power_fault(slot);
610 }
611 return IRQ_HANDLED;
612}
613
614int pciehp_get_max_lnk_width(struct slot *slot,
615 enum pcie_link_width *value)
616{
617 struct controller *ctrl = slot->ctrl;
618 enum pcie_link_width lnk_wdth;
619 u32 lnk_cap;
620 int retval = 0;
621
622 retval = pciehp_readl(ctrl, PCI_EXP_LNKCAP, &lnk_cap);
623 if (retval) {
624 ctrl_err(ctrl, "%s: Cannot read LNKCAP register\n", __func__);
625 return retval;
626 }
627
628 switch ((lnk_cap & PCI_EXP_LNKSTA_NLW) >> 4){
629 case 0:
630 lnk_wdth = PCIE_LNK_WIDTH_RESRV;
631 break;
632 case 1:
633 lnk_wdth = PCIE_LNK_X1;
634 break;
635 case 2:
636 lnk_wdth = PCIE_LNK_X2;
637 break;
638 case 4:
639 lnk_wdth = PCIE_LNK_X4;
640 break;
641 case 8:
642 lnk_wdth = PCIE_LNK_X8;
643 break;
644 case 12:
645 lnk_wdth = PCIE_LNK_X12;
646 break;
647 case 16:
648 lnk_wdth = PCIE_LNK_X16;
649 break;
650 case 32:
651 lnk_wdth = PCIE_LNK_X32;
652 break;
653 default:
654 lnk_wdth = PCIE_LNK_WIDTH_UNKNOWN;
655 break;
656 }
657
658 *value = lnk_wdth;
659 ctrl_dbg(ctrl, "Max link width = %d\n", lnk_wdth);
660
661 return retval;
662}
663
664int pciehp_get_cur_lnk_width(struct slot *slot,
665 enum pcie_link_width *value)
666{
667 struct controller *ctrl = slot->ctrl;
668 enum pcie_link_width lnk_wdth = PCIE_LNK_WIDTH_UNKNOWN;
669 int retval = 0;
670 u16 lnk_status;
671
672 retval = pciehp_readw(ctrl, PCI_EXP_LNKSTA, &lnk_status);
673 if (retval) {
674 ctrl_err(ctrl, "%s: Cannot read LNKSTATUS register\n",
675 __func__);
676 return retval;
677 }
678
679 switch ((lnk_status & PCI_EXP_LNKSTA_NLW) >> 4){
680 case 0:
681 lnk_wdth = PCIE_LNK_WIDTH_RESRV;
682 break;
683 case 1:
684 lnk_wdth = PCIE_LNK_X1;
685 break;
686 case 2:
687 lnk_wdth = PCIE_LNK_X2;
688 break;
689 case 4:
690 lnk_wdth = PCIE_LNK_X4;
691 break;
692 case 8:
693 lnk_wdth = PCIE_LNK_X8;
694 break;
695 case 12:
696 lnk_wdth = PCIE_LNK_X12;
697 break;
698 case 16:
699 lnk_wdth = PCIE_LNK_X16;
700 break;
701 case 32:
702 lnk_wdth = PCIE_LNK_X32;
703 break;
704 default:
705 lnk_wdth = PCIE_LNK_WIDTH_UNKNOWN;
706 break;
707 }
708
709 *value = lnk_wdth;
710 ctrl_dbg(ctrl, "Current link width = %d\n", lnk_wdth);
711
712 return retval;
713}
714
715int pcie_enable_notification(struct controller *ctrl)
716{
717 u16 cmd, mask;
718
719 /*
720 * TBD: Power fault detected software notification support.
721 *
722 * Power fault detected software notification is not enabled
723 * now, because it caused power fault detected interrupt storm
724 * on some machines. On those machines, power fault detected
725 * bit in the slot status register was set again immediately
726 * when it is cleared in the interrupt service routine, and
727 * next power fault detected interrupt was notified again.
728 */
729 cmd = PCI_EXP_SLTCTL_PDCE;
730 if (ATTN_BUTTN(ctrl))
731 cmd |= PCI_EXP_SLTCTL_ABPE;
732 if (MRL_SENS(ctrl))
733 cmd |= PCI_EXP_SLTCTL_MRLSCE;
734 if (!pciehp_poll_mode)
735 cmd |= PCI_EXP_SLTCTL_HPIE | PCI_EXP_SLTCTL_CCIE;
736
737 mask = (PCI_EXP_SLTCTL_PDCE | PCI_EXP_SLTCTL_ABPE |
738 PCI_EXP_SLTCTL_MRLSCE | PCI_EXP_SLTCTL_PFDE |
739 PCI_EXP_SLTCTL_HPIE | PCI_EXP_SLTCTL_CCIE);
740
741 if (pcie_write_cmd(ctrl, cmd, mask)) {
742 ctrl_err(ctrl, "Cannot enable software notification\n");
743 return -1;
744 }
745 return 0;
746}
747
748static void pcie_disable_notification(struct controller *ctrl)
749{
750 u16 mask;
751 mask = (PCI_EXP_SLTCTL_PDCE | PCI_EXP_SLTCTL_ABPE |
752 PCI_EXP_SLTCTL_MRLSCE | PCI_EXP_SLTCTL_PFDE |
753 PCI_EXP_SLTCTL_HPIE | PCI_EXP_SLTCTL_CCIE |
754 PCI_EXP_SLTCTL_DLLSCE);
755 if (pcie_write_cmd(ctrl, 0, mask))
756 ctrl_warn(ctrl, "Cannot disable software notification\n");
757}
758
759int pcie_init_notification(struct controller *ctrl)
760{
761 if (pciehp_request_irq(ctrl))
762 return -1;
763 if (pcie_enable_notification(ctrl)) {
764 pciehp_free_irq(ctrl);
765 return -1;
766 }
767 ctrl->notification_enabled = 1;
768 return 0;
769}
770
771static void pcie_shutdown_notification(struct controller *ctrl)
772{
773 if (ctrl->notification_enabled) {
774 pcie_disable_notification(ctrl);
775 pciehp_free_irq(ctrl);
776 ctrl->notification_enabled = 0;
777 }
778}
779
780static int pcie_init_slot(struct controller *ctrl)
781{
782 struct slot *slot;
783
784 slot = kzalloc(sizeof(*slot), GFP_KERNEL);
785 if (!slot)
786 return -ENOMEM;
787
788 slot->ctrl = ctrl;
789 mutex_init(&slot->lock);
790 INIT_DELAYED_WORK(&slot->work, pciehp_queue_pushbutton_work);
791 ctrl->slot = slot;
792 return 0;
793}
794
795static void pcie_cleanup_slot(struct controller *ctrl)
796{
797 struct slot *slot = ctrl->slot;
798 cancel_delayed_work(&slot->work);
799 flush_workqueue(pciehp_wq);
800 flush_workqueue(pciehp_ordered_wq);
801 kfree(slot);
802}
803
804static inline void dbg_ctrl(struct controller *ctrl)
805{
806 int i;
807 u16 reg16;
808 struct pci_dev *pdev = ctrl->pcie->port;
809
810 if (!pciehp_debug)
811 return;
812
813 ctrl_info(ctrl, "Hotplug Controller:\n");
814 ctrl_info(ctrl, " Seg/Bus/Dev/Func/IRQ : %s IRQ %d\n",
815 pci_name(pdev), pdev->irq);
816 ctrl_info(ctrl, " Vendor ID : 0x%04x\n", pdev->vendor);
817 ctrl_info(ctrl, " Device ID : 0x%04x\n", pdev->device);
818 ctrl_info(ctrl, " Subsystem ID : 0x%04x\n",
819 pdev->subsystem_device);
820 ctrl_info(ctrl, " Subsystem Vendor ID : 0x%04x\n",
821 pdev->subsystem_vendor);
822 ctrl_info(ctrl, " PCIe Cap offset : 0x%02x\n",
823 pci_pcie_cap(pdev));
824 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
825 if (!pci_resource_len(pdev, i))
826 continue;
827 ctrl_info(ctrl, " PCI resource [%d] : %pR\n",
828 i, &pdev->resource[i]);
829 }
830 ctrl_info(ctrl, "Slot Capabilities : 0x%08x\n", ctrl->slot_cap);
831 ctrl_info(ctrl, " Physical Slot Number : %d\n", PSN(ctrl));
832 ctrl_info(ctrl, " Attention Button : %3s\n",
833 ATTN_BUTTN(ctrl) ? "yes" : "no");
834 ctrl_info(ctrl, " Power Controller : %3s\n",
835 POWER_CTRL(ctrl) ? "yes" : "no");
836 ctrl_info(ctrl, " MRL Sensor : %3s\n",
837 MRL_SENS(ctrl) ? "yes" : "no");
838 ctrl_info(ctrl, " Attention Indicator : %3s\n",
839 ATTN_LED(ctrl) ? "yes" : "no");
840 ctrl_info(ctrl, " Power Indicator : %3s\n",
841 PWR_LED(ctrl) ? "yes" : "no");
842 ctrl_info(ctrl, " Hot-Plug Surprise : %3s\n",
843 HP_SUPR_RM(ctrl) ? "yes" : "no");
844 ctrl_info(ctrl, " EMI Present : %3s\n",
845 EMI(ctrl) ? "yes" : "no");
846 ctrl_info(ctrl, " Command Completed : %3s\n",
847 NO_CMD_CMPL(ctrl) ? "no" : "yes");
848 pciehp_readw(ctrl, PCI_EXP_SLTSTA, ®16);
849 ctrl_info(ctrl, "Slot Status : 0x%04x\n", reg16);
850 pciehp_readw(ctrl, PCI_EXP_SLTCTL, ®16);
851 ctrl_info(ctrl, "Slot Control : 0x%04x\n", reg16);
852}
853
854struct controller *pcie_init(struct pcie_device *dev)
855{
856 struct controller *ctrl;
857 u32 slot_cap, link_cap;
858 struct pci_dev *pdev = dev->port;
859
860 ctrl = kzalloc(sizeof(*ctrl), GFP_KERNEL);
861 if (!ctrl) {
862 dev_err(&dev->device, "%s: Out of memory\n", __func__);
863 goto abort;
864 }
865 ctrl->pcie = dev;
866 if (!pci_pcie_cap(pdev)) {
867 ctrl_err(ctrl, "Cannot find PCI Express capability\n");
868 goto abort_ctrl;
869 }
870 if (pciehp_readl(ctrl, PCI_EXP_SLTCAP, &slot_cap)) {
871 ctrl_err(ctrl, "Cannot read SLOTCAP register\n");
872 goto abort_ctrl;
873 }
874
875 ctrl->slot_cap = slot_cap;
876 mutex_init(&ctrl->ctrl_lock);
877 init_waitqueue_head(&ctrl->queue);
878 dbg_ctrl(ctrl);
879 /*
880 * Controller doesn't notify of command completion if the "No
881 * Command Completed Support" bit is set in Slot Capability
882 * register or the controller supports none of power
883 * controller, attention led, power led and EMI.
884 */
885 if (NO_CMD_CMPL(ctrl) ||
886 !(POWER_CTRL(ctrl) | ATTN_LED(ctrl) | PWR_LED(ctrl) | EMI(ctrl)))
887 ctrl->no_cmd_complete = 1;
888
889 /* Check if Data Link Layer Link Active Reporting is implemented */
890 if (pciehp_readl(ctrl, PCI_EXP_LNKCAP, &link_cap)) {
891 ctrl_err(ctrl, "%s: Cannot read LNKCAP register\n", __func__);
892 goto abort_ctrl;
893 }
894 if (link_cap & PCI_EXP_LNKCAP_DLLLARC) {
895 ctrl_dbg(ctrl, "Link Active Reporting supported\n");
896 ctrl->link_active_reporting = 1;
897 }
898
899 /* Clear all remaining event bits in Slot Status register */
900 if (pciehp_writew(ctrl, PCI_EXP_SLTSTA, 0x1f))
901 goto abort_ctrl;
902
903 /* Disable sotfware notification */
904 pcie_disable_notification(ctrl);
905
906 ctrl_info(ctrl, "HPC vendor_id %x device_id %x ss_vid %x ss_did %x\n",
907 pdev->vendor, pdev->device, pdev->subsystem_vendor,
908 pdev->subsystem_device);
909
910 if (pcie_init_slot(ctrl))
911 goto abort_ctrl;
912
913 return ctrl;
914
915abort_ctrl:
916 kfree(ctrl);
917abort:
918 return NULL;
919}
920
921void pciehp_release_ctrl(struct controller *ctrl)
922{
923 pcie_shutdown_notification(ctrl);
924 pcie_cleanup_slot(ctrl);
925 kfree(ctrl);
926}
1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * PCI Express PCI Hot Plug Driver
4 *
5 * Copyright (C) 1995,2001 Compaq Computer Corporation
6 * Copyright (C) 2001 Greg Kroah-Hartman (greg@kroah.com)
7 * Copyright (C) 2001 IBM Corp.
8 * Copyright (C) 2003-2004 Intel Corporation
9 *
10 * All rights reserved.
11 *
12 * Send feedback to <greg@kroah.com>,<kristen.c.accardi@intel.com>
13 */
14
15#define dev_fmt(fmt) "pciehp: " fmt
16
17#include <linux/kernel.h>
18#include <linux/types.h>
19#include <linux/jiffies.h>
20#include <linux/kthread.h>
21#include <linux/pci.h>
22#include <linux/pm_runtime.h>
23#include <linux/interrupt.h>
24#include <linux/slab.h>
25
26#include "../pci.h"
27#include "pciehp.h"
28
29static inline struct pci_dev *ctrl_dev(struct controller *ctrl)
30{
31 return ctrl->pcie->port;
32}
33
34static irqreturn_t pciehp_isr(int irq, void *dev_id);
35static irqreturn_t pciehp_ist(int irq, void *dev_id);
36static int pciehp_poll(void *data);
37
38static inline int pciehp_request_irq(struct controller *ctrl)
39{
40 int retval, irq = ctrl->pcie->irq;
41
42 if (pciehp_poll_mode) {
43 ctrl->poll_thread = kthread_run(&pciehp_poll, ctrl,
44 "pciehp_poll-%s",
45 slot_name(ctrl));
46 return PTR_ERR_OR_ZERO(ctrl->poll_thread);
47 }
48
49 /* Installs the interrupt handler */
50 retval = request_threaded_irq(irq, pciehp_isr, pciehp_ist,
51 IRQF_SHARED, "pciehp", ctrl);
52 if (retval)
53 ctrl_err(ctrl, "Cannot get irq %d for the hotplug controller\n",
54 irq);
55 return retval;
56}
57
58static inline void pciehp_free_irq(struct controller *ctrl)
59{
60 if (pciehp_poll_mode)
61 kthread_stop(ctrl->poll_thread);
62 else
63 free_irq(ctrl->pcie->irq, ctrl);
64}
65
66static int pcie_poll_cmd(struct controller *ctrl, int timeout)
67{
68 struct pci_dev *pdev = ctrl_dev(ctrl);
69 u16 slot_status;
70
71 while (true) {
72 pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &slot_status);
73 if (slot_status == (u16) ~0) {
74 ctrl_info(ctrl, "%s: no response from device\n",
75 __func__);
76 return 0;
77 }
78
79 if (slot_status & PCI_EXP_SLTSTA_CC) {
80 pcie_capability_write_word(pdev, PCI_EXP_SLTSTA,
81 PCI_EXP_SLTSTA_CC);
82 return 1;
83 }
84 if (timeout < 0)
85 break;
86 msleep(10);
87 timeout -= 10;
88 }
89 return 0; /* timeout */
90}
91
92static void pcie_wait_cmd(struct controller *ctrl)
93{
94 unsigned int msecs = pciehp_poll_mode ? 2500 : 1000;
95 unsigned long duration = msecs_to_jiffies(msecs);
96 unsigned long cmd_timeout = ctrl->cmd_started + duration;
97 unsigned long now, timeout;
98 int rc;
99
100 /*
101 * If the controller does not generate notifications for command
102 * completions, we never need to wait between writes.
103 */
104 if (NO_CMD_CMPL(ctrl))
105 return;
106
107 if (!ctrl->cmd_busy)
108 return;
109
110 /*
111 * Even if the command has already timed out, we want to call
112 * pcie_poll_cmd() so it can clear PCI_EXP_SLTSTA_CC.
113 */
114 now = jiffies;
115 if (time_before_eq(cmd_timeout, now))
116 timeout = 1;
117 else
118 timeout = cmd_timeout - now;
119
120 if (ctrl->slot_ctrl & PCI_EXP_SLTCTL_HPIE &&
121 ctrl->slot_ctrl & PCI_EXP_SLTCTL_CCIE)
122 rc = wait_event_timeout(ctrl->queue, !ctrl->cmd_busy, timeout);
123 else
124 rc = pcie_poll_cmd(ctrl, jiffies_to_msecs(timeout));
125
126 if (!rc)
127 ctrl_info(ctrl, "Timeout on hotplug command %#06x (issued %u msec ago)\n",
128 ctrl->slot_ctrl,
129 jiffies_to_msecs(jiffies - ctrl->cmd_started));
130}
131
132#define CC_ERRATUM_MASK (PCI_EXP_SLTCTL_PCC | \
133 PCI_EXP_SLTCTL_PIC | \
134 PCI_EXP_SLTCTL_AIC | \
135 PCI_EXP_SLTCTL_EIC)
136
137static void pcie_do_write_cmd(struct controller *ctrl, u16 cmd,
138 u16 mask, bool wait)
139{
140 struct pci_dev *pdev = ctrl_dev(ctrl);
141 u16 slot_ctrl_orig, slot_ctrl;
142
143 mutex_lock(&ctrl->ctrl_lock);
144
145 /*
146 * Always wait for any previous command that might still be in progress
147 */
148 pcie_wait_cmd(ctrl);
149
150 pcie_capability_read_word(pdev, PCI_EXP_SLTCTL, &slot_ctrl);
151 if (slot_ctrl == (u16) ~0) {
152 ctrl_info(ctrl, "%s: no response from device\n", __func__);
153 goto out;
154 }
155
156 slot_ctrl_orig = slot_ctrl;
157 slot_ctrl &= ~mask;
158 slot_ctrl |= (cmd & mask);
159 ctrl->cmd_busy = 1;
160 smp_mb();
161 ctrl->slot_ctrl = slot_ctrl;
162 pcie_capability_write_word(pdev, PCI_EXP_SLTCTL, slot_ctrl);
163 ctrl->cmd_started = jiffies;
164
165 /*
166 * Controllers with the Intel CF118 and similar errata advertise
167 * Command Completed support, but they only set Command Completed
168 * if we change the "Control" bits for power, power indicator,
169 * attention indicator, or interlock. If we only change the
170 * "Enable" bits, they never set the Command Completed bit.
171 */
172 if (pdev->broken_cmd_compl &&
173 (slot_ctrl_orig & CC_ERRATUM_MASK) == (slot_ctrl & CC_ERRATUM_MASK))
174 ctrl->cmd_busy = 0;
175
176 /*
177 * Optionally wait for the hardware to be ready for a new command,
178 * indicating completion of the above issued command.
179 */
180 if (wait)
181 pcie_wait_cmd(ctrl);
182
183out:
184 mutex_unlock(&ctrl->ctrl_lock);
185}
186
187/**
188 * pcie_write_cmd - Issue controller command
189 * @ctrl: controller to which the command is issued
190 * @cmd: command value written to slot control register
191 * @mask: bitmask of slot control register to be modified
192 */
193static void pcie_write_cmd(struct controller *ctrl, u16 cmd, u16 mask)
194{
195 pcie_do_write_cmd(ctrl, cmd, mask, true);
196}
197
198/* Same as above without waiting for the hardware to latch */
199static void pcie_write_cmd_nowait(struct controller *ctrl, u16 cmd, u16 mask)
200{
201 pcie_do_write_cmd(ctrl, cmd, mask, false);
202}
203
204bool pciehp_check_link_active(struct controller *ctrl)
205{
206 struct pci_dev *pdev = ctrl_dev(ctrl);
207 u16 lnk_status;
208 bool ret;
209
210 pcie_capability_read_word(pdev, PCI_EXP_LNKSTA, &lnk_status);
211 ret = !!(lnk_status & PCI_EXP_LNKSTA_DLLLA);
212
213 if (ret)
214 ctrl_dbg(ctrl, "%s: lnk_status = %x\n", __func__, lnk_status);
215
216 return ret;
217}
218
219static bool pci_bus_check_dev(struct pci_bus *bus, int devfn)
220{
221 u32 l;
222 int count = 0;
223 int delay = 1000, step = 20;
224 bool found = false;
225
226 do {
227 found = pci_bus_read_dev_vendor_id(bus, devfn, &l, 0);
228 count++;
229
230 if (found)
231 break;
232
233 msleep(step);
234 delay -= step;
235 } while (delay > 0);
236
237 if (count > 1)
238 pr_debug("pci %04x:%02x:%02x.%d id reading try %d times with interval %d ms to get %08x\n",
239 pci_domain_nr(bus), bus->number, PCI_SLOT(devfn),
240 PCI_FUNC(devfn), count, step, l);
241
242 return found;
243}
244
245int pciehp_check_link_status(struct controller *ctrl)
246{
247 struct pci_dev *pdev = ctrl_dev(ctrl);
248 bool found;
249 u16 lnk_status;
250
251 if (!pcie_wait_for_link(pdev, true))
252 return -1;
253
254 found = pci_bus_check_dev(ctrl->pcie->port->subordinate,
255 PCI_DEVFN(0, 0));
256
257 /* ignore link or presence changes up to this point */
258 if (found)
259 atomic_and(~(PCI_EXP_SLTSTA_DLLSC | PCI_EXP_SLTSTA_PDC),
260 &ctrl->pending_events);
261
262 pcie_capability_read_word(pdev, PCI_EXP_LNKSTA, &lnk_status);
263 ctrl_dbg(ctrl, "%s: lnk_status = %x\n", __func__, lnk_status);
264 if ((lnk_status & PCI_EXP_LNKSTA_LT) ||
265 !(lnk_status & PCI_EXP_LNKSTA_NLW)) {
266 ctrl_err(ctrl, "link training error: status %#06x\n",
267 lnk_status);
268 return -1;
269 }
270
271 pcie_update_link_speed(ctrl->pcie->port->subordinate, lnk_status);
272
273 if (!found)
274 return -1;
275
276 return 0;
277}
278
279static int __pciehp_link_set(struct controller *ctrl, bool enable)
280{
281 struct pci_dev *pdev = ctrl_dev(ctrl);
282 u16 lnk_ctrl;
283
284 pcie_capability_read_word(pdev, PCI_EXP_LNKCTL, &lnk_ctrl);
285
286 if (enable)
287 lnk_ctrl &= ~PCI_EXP_LNKCTL_LD;
288 else
289 lnk_ctrl |= PCI_EXP_LNKCTL_LD;
290
291 pcie_capability_write_word(pdev, PCI_EXP_LNKCTL, lnk_ctrl);
292 ctrl_dbg(ctrl, "%s: lnk_ctrl = %x\n", __func__, lnk_ctrl);
293 return 0;
294}
295
296static int pciehp_link_enable(struct controller *ctrl)
297{
298 return __pciehp_link_set(ctrl, true);
299}
300
301int pciehp_get_raw_indicator_status(struct hotplug_slot *hotplug_slot,
302 u8 *status)
303{
304 struct controller *ctrl = to_ctrl(hotplug_slot);
305 struct pci_dev *pdev = ctrl_dev(ctrl);
306 u16 slot_ctrl;
307
308 pci_config_pm_runtime_get(pdev);
309 pcie_capability_read_word(pdev, PCI_EXP_SLTCTL, &slot_ctrl);
310 pci_config_pm_runtime_put(pdev);
311 *status = (slot_ctrl & (PCI_EXP_SLTCTL_AIC | PCI_EXP_SLTCTL_PIC)) >> 6;
312 return 0;
313}
314
315int pciehp_get_attention_status(struct hotplug_slot *hotplug_slot, u8 *status)
316{
317 struct controller *ctrl = to_ctrl(hotplug_slot);
318 struct pci_dev *pdev = ctrl_dev(ctrl);
319 u16 slot_ctrl;
320
321 pci_config_pm_runtime_get(pdev);
322 pcie_capability_read_word(pdev, PCI_EXP_SLTCTL, &slot_ctrl);
323 pci_config_pm_runtime_put(pdev);
324 ctrl_dbg(ctrl, "%s: SLOTCTRL %x, value read %x\n", __func__,
325 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_ctrl);
326
327 switch (slot_ctrl & PCI_EXP_SLTCTL_AIC) {
328 case PCI_EXP_SLTCTL_ATTN_IND_ON:
329 *status = 1; /* On */
330 break;
331 case PCI_EXP_SLTCTL_ATTN_IND_BLINK:
332 *status = 2; /* Blink */
333 break;
334 case PCI_EXP_SLTCTL_ATTN_IND_OFF:
335 *status = 0; /* Off */
336 break;
337 default:
338 *status = 0xFF;
339 break;
340 }
341
342 return 0;
343}
344
345void pciehp_get_power_status(struct controller *ctrl, u8 *status)
346{
347 struct pci_dev *pdev = ctrl_dev(ctrl);
348 u16 slot_ctrl;
349
350 pcie_capability_read_word(pdev, PCI_EXP_SLTCTL, &slot_ctrl);
351 ctrl_dbg(ctrl, "%s: SLOTCTRL %x value read %x\n", __func__,
352 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_ctrl);
353
354 switch (slot_ctrl & PCI_EXP_SLTCTL_PCC) {
355 case PCI_EXP_SLTCTL_PWR_ON:
356 *status = 1; /* On */
357 break;
358 case PCI_EXP_SLTCTL_PWR_OFF:
359 *status = 0; /* Off */
360 break;
361 default:
362 *status = 0xFF;
363 break;
364 }
365}
366
367void pciehp_get_latch_status(struct controller *ctrl, u8 *status)
368{
369 struct pci_dev *pdev = ctrl_dev(ctrl);
370 u16 slot_status;
371
372 pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &slot_status);
373 *status = !!(slot_status & PCI_EXP_SLTSTA_MRLSS);
374}
375
376bool pciehp_card_present(struct controller *ctrl)
377{
378 struct pci_dev *pdev = ctrl_dev(ctrl);
379 u16 slot_status;
380
381 pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &slot_status);
382 return slot_status & PCI_EXP_SLTSTA_PDS;
383}
384
385/**
386 * pciehp_card_present_or_link_active() - whether given slot is occupied
387 * @ctrl: PCIe hotplug controller
388 *
389 * Unlike pciehp_card_present(), which determines presence solely from the
390 * Presence Detect State bit, this helper also returns true if the Link Active
391 * bit is set. This is a concession to broken hotplug ports which hardwire
392 * Presence Detect State to zero, such as Wilocity's [1ae9:0200].
393 */
394bool pciehp_card_present_or_link_active(struct controller *ctrl)
395{
396 return pciehp_card_present(ctrl) || pciehp_check_link_active(ctrl);
397}
398
399int pciehp_query_power_fault(struct controller *ctrl)
400{
401 struct pci_dev *pdev = ctrl_dev(ctrl);
402 u16 slot_status;
403
404 pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &slot_status);
405 return !!(slot_status & PCI_EXP_SLTSTA_PFD);
406}
407
408int pciehp_set_raw_indicator_status(struct hotplug_slot *hotplug_slot,
409 u8 status)
410{
411 struct controller *ctrl = to_ctrl(hotplug_slot);
412 struct pci_dev *pdev = ctrl_dev(ctrl);
413
414 pci_config_pm_runtime_get(pdev);
415 pcie_write_cmd_nowait(ctrl, status << 6,
416 PCI_EXP_SLTCTL_AIC | PCI_EXP_SLTCTL_PIC);
417 pci_config_pm_runtime_put(pdev);
418 return 0;
419}
420
421/**
422 * pciehp_set_indicators() - set attention indicator, power indicator, or both
423 * @ctrl: PCIe hotplug controller
424 * @pwr: one of:
425 * PCI_EXP_SLTCTL_PWR_IND_ON
426 * PCI_EXP_SLTCTL_PWR_IND_BLINK
427 * PCI_EXP_SLTCTL_PWR_IND_OFF
428 * @attn: one of:
429 * PCI_EXP_SLTCTL_ATTN_IND_ON
430 * PCI_EXP_SLTCTL_ATTN_IND_BLINK
431 * PCI_EXP_SLTCTL_ATTN_IND_OFF
432 *
433 * Either @pwr or @attn can also be INDICATOR_NOOP to leave that indicator
434 * unchanged.
435 */
436void pciehp_set_indicators(struct controller *ctrl, int pwr, int attn)
437{
438 u16 cmd = 0, mask = 0;
439
440 if (PWR_LED(ctrl) && pwr != INDICATOR_NOOP) {
441 cmd |= (pwr & PCI_EXP_SLTCTL_PIC);
442 mask |= PCI_EXP_SLTCTL_PIC;
443 }
444
445 if (ATTN_LED(ctrl) && attn != INDICATOR_NOOP) {
446 cmd |= (attn & PCI_EXP_SLTCTL_AIC);
447 mask |= PCI_EXP_SLTCTL_AIC;
448 }
449
450 if (cmd) {
451 pcie_write_cmd_nowait(ctrl, cmd, mask);
452 ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
453 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, cmd);
454 }
455}
456
457int pciehp_power_on_slot(struct controller *ctrl)
458{
459 struct pci_dev *pdev = ctrl_dev(ctrl);
460 u16 slot_status;
461 int retval;
462
463 /* Clear power-fault bit from previous power failures */
464 pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &slot_status);
465 if (slot_status & PCI_EXP_SLTSTA_PFD)
466 pcie_capability_write_word(pdev, PCI_EXP_SLTSTA,
467 PCI_EXP_SLTSTA_PFD);
468 ctrl->power_fault_detected = 0;
469
470 pcie_write_cmd(ctrl, PCI_EXP_SLTCTL_PWR_ON, PCI_EXP_SLTCTL_PCC);
471 ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
472 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL,
473 PCI_EXP_SLTCTL_PWR_ON);
474
475 retval = pciehp_link_enable(ctrl);
476 if (retval)
477 ctrl_err(ctrl, "%s: Can not enable the link!\n", __func__);
478
479 return retval;
480}
481
482void pciehp_power_off_slot(struct controller *ctrl)
483{
484 pcie_write_cmd(ctrl, PCI_EXP_SLTCTL_PWR_OFF, PCI_EXP_SLTCTL_PCC);
485 ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
486 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL,
487 PCI_EXP_SLTCTL_PWR_OFF);
488}
489
490static irqreturn_t pciehp_isr(int irq, void *dev_id)
491{
492 struct controller *ctrl = (struct controller *)dev_id;
493 struct pci_dev *pdev = ctrl_dev(ctrl);
494 struct device *parent = pdev->dev.parent;
495 u16 status, events;
496
497 /*
498 * Interrupts only occur in D3hot or shallower and only if enabled
499 * in the Slot Control register (PCIe r4.0, sec 6.7.3.4).
500 */
501 if (pdev->current_state == PCI_D3cold ||
502 (!(ctrl->slot_ctrl & PCI_EXP_SLTCTL_HPIE) && !pciehp_poll_mode))
503 return IRQ_NONE;
504
505 /*
506 * Keep the port accessible by holding a runtime PM ref on its parent.
507 * Defer resume of the parent to the IRQ thread if it's suspended.
508 * Mask the interrupt until then.
509 */
510 if (parent) {
511 pm_runtime_get_noresume(parent);
512 if (!pm_runtime_active(parent)) {
513 pm_runtime_put(parent);
514 disable_irq_nosync(irq);
515 atomic_or(RERUN_ISR, &ctrl->pending_events);
516 return IRQ_WAKE_THREAD;
517 }
518 }
519
520 pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &status);
521 if (status == (u16) ~0) {
522 ctrl_info(ctrl, "%s: no response from device\n", __func__);
523 if (parent)
524 pm_runtime_put(parent);
525 return IRQ_NONE;
526 }
527
528 /*
529 * Slot Status contains plain status bits as well as event
530 * notification bits; right now we only want the event bits.
531 */
532 events = status & (PCI_EXP_SLTSTA_ABP | PCI_EXP_SLTSTA_PFD |
533 PCI_EXP_SLTSTA_PDC | PCI_EXP_SLTSTA_CC |
534 PCI_EXP_SLTSTA_DLLSC);
535
536 /*
537 * If we've already reported a power fault, don't report it again
538 * until we've done something to handle it.
539 */
540 if (ctrl->power_fault_detected)
541 events &= ~PCI_EXP_SLTSTA_PFD;
542
543 if (!events) {
544 if (parent)
545 pm_runtime_put(parent);
546 return IRQ_NONE;
547 }
548
549 pcie_capability_write_word(pdev, PCI_EXP_SLTSTA, events);
550 ctrl_dbg(ctrl, "pending interrupts %#06x from Slot Status\n", events);
551 if (parent)
552 pm_runtime_put(parent);
553
554 /*
555 * Command Completed notifications are not deferred to the
556 * IRQ thread because it may be waiting for their arrival.
557 */
558 if (events & PCI_EXP_SLTSTA_CC) {
559 ctrl->cmd_busy = 0;
560 smp_mb();
561 wake_up(&ctrl->queue);
562
563 if (events == PCI_EXP_SLTSTA_CC)
564 return IRQ_HANDLED;
565
566 events &= ~PCI_EXP_SLTSTA_CC;
567 }
568
569 if (pdev->ignore_hotplug) {
570 ctrl_dbg(ctrl, "ignoring hotplug event %#06x\n", events);
571 return IRQ_HANDLED;
572 }
573
574 /* Save pending events for consumption by IRQ thread. */
575 atomic_or(events, &ctrl->pending_events);
576 return IRQ_WAKE_THREAD;
577}
578
579static irqreturn_t pciehp_ist(int irq, void *dev_id)
580{
581 struct controller *ctrl = (struct controller *)dev_id;
582 struct pci_dev *pdev = ctrl_dev(ctrl);
583 irqreturn_t ret;
584 u32 events;
585
586 pci_config_pm_runtime_get(pdev);
587
588 /* rerun pciehp_isr() if the port was inaccessible on interrupt */
589 if (atomic_fetch_and(~RERUN_ISR, &ctrl->pending_events) & RERUN_ISR) {
590 ret = pciehp_isr(irq, dev_id);
591 enable_irq(irq);
592 if (ret != IRQ_WAKE_THREAD) {
593 pci_config_pm_runtime_put(pdev);
594 return ret;
595 }
596 }
597
598 synchronize_hardirq(irq);
599 events = atomic_xchg(&ctrl->pending_events, 0);
600 if (!events) {
601 pci_config_pm_runtime_put(pdev);
602 return IRQ_NONE;
603 }
604
605 /* Check Attention Button Pressed */
606 if (events & PCI_EXP_SLTSTA_ABP) {
607 ctrl_info(ctrl, "Slot(%s): Attention button pressed\n",
608 slot_name(ctrl));
609 pciehp_handle_button_press(ctrl);
610 }
611
612 /* Check Power Fault Detected */
613 if ((events & PCI_EXP_SLTSTA_PFD) && !ctrl->power_fault_detected) {
614 ctrl->power_fault_detected = 1;
615 ctrl_err(ctrl, "Slot(%s): Power fault\n", slot_name(ctrl));
616 pciehp_set_indicators(ctrl, PCI_EXP_SLTCTL_PWR_IND_OFF,
617 PCI_EXP_SLTCTL_ATTN_IND_ON);
618 }
619
620 /*
621 * Disable requests have higher priority than Presence Detect Changed
622 * or Data Link Layer State Changed events.
623 */
624 down_read(&ctrl->reset_lock);
625 if (events & DISABLE_SLOT)
626 pciehp_handle_disable_request(ctrl);
627 else if (events & (PCI_EXP_SLTSTA_PDC | PCI_EXP_SLTSTA_DLLSC))
628 pciehp_handle_presence_or_link_change(ctrl, events);
629 up_read(&ctrl->reset_lock);
630
631 pci_config_pm_runtime_put(pdev);
632 wake_up(&ctrl->requester);
633 return IRQ_HANDLED;
634}
635
636static int pciehp_poll(void *data)
637{
638 struct controller *ctrl = data;
639
640 schedule_timeout_idle(10 * HZ); /* start with 10 sec delay */
641
642 while (!kthread_should_stop()) {
643 /* poll for interrupt events or user requests */
644 while (pciehp_isr(IRQ_NOTCONNECTED, ctrl) == IRQ_WAKE_THREAD ||
645 atomic_read(&ctrl->pending_events))
646 pciehp_ist(IRQ_NOTCONNECTED, ctrl);
647
648 if (pciehp_poll_time <= 0 || pciehp_poll_time > 60)
649 pciehp_poll_time = 2; /* clamp to sane value */
650
651 schedule_timeout_idle(pciehp_poll_time * HZ);
652 }
653
654 return 0;
655}
656
657static void pcie_enable_notification(struct controller *ctrl)
658{
659 u16 cmd, mask;
660
661 /*
662 * TBD: Power fault detected software notification support.
663 *
664 * Power fault detected software notification is not enabled
665 * now, because it caused power fault detected interrupt storm
666 * on some machines. On those machines, power fault detected
667 * bit in the slot status register was set again immediately
668 * when it is cleared in the interrupt service routine, and
669 * next power fault detected interrupt was notified again.
670 */
671
672 /*
673 * Always enable link events: thus link-up and link-down shall
674 * always be treated as hotplug and unplug respectively. Enable
675 * presence detect only if Attention Button is not present.
676 */
677 cmd = PCI_EXP_SLTCTL_DLLSCE;
678 if (ATTN_BUTTN(ctrl))
679 cmd |= PCI_EXP_SLTCTL_ABPE;
680 else
681 cmd |= PCI_EXP_SLTCTL_PDCE;
682 if (!pciehp_poll_mode)
683 cmd |= PCI_EXP_SLTCTL_HPIE | PCI_EXP_SLTCTL_CCIE;
684
685 mask = (PCI_EXP_SLTCTL_PDCE | PCI_EXP_SLTCTL_ABPE |
686 PCI_EXP_SLTCTL_PFDE |
687 PCI_EXP_SLTCTL_HPIE | PCI_EXP_SLTCTL_CCIE |
688 PCI_EXP_SLTCTL_DLLSCE);
689
690 pcie_write_cmd_nowait(ctrl, cmd, mask);
691 ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
692 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, cmd);
693}
694
695static void pcie_disable_notification(struct controller *ctrl)
696{
697 u16 mask;
698
699 mask = (PCI_EXP_SLTCTL_PDCE | PCI_EXP_SLTCTL_ABPE |
700 PCI_EXP_SLTCTL_MRLSCE | PCI_EXP_SLTCTL_PFDE |
701 PCI_EXP_SLTCTL_HPIE | PCI_EXP_SLTCTL_CCIE |
702 PCI_EXP_SLTCTL_DLLSCE);
703 pcie_write_cmd(ctrl, 0, mask);
704 ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
705 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, 0);
706}
707
708void pcie_clear_hotplug_events(struct controller *ctrl)
709{
710 pcie_capability_write_word(ctrl_dev(ctrl), PCI_EXP_SLTSTA,
711 PCI_EXP_SLTSTA_PDC | PCI_EXP_SLTSTA_DLLSC);
712}
713
714void pcie_enable_interrupt(struct controller *ctrl)
715{
716 u16 mask;
717
718 mask = PCI_EXP_SLTCTL_HPIE | PCI_EXP_SLTCTL_DLLSCE;
719 pcie_write_cmd(ctrl, mask, mask);
720}
721
722void pcie_disable_interrupt(struct controller *ctrl)
723{
724 u16 mask;
725
726 /*
727 * Mask hot-plug interrupt to prevent it triggering immediately
728 * when the link goes inactive (we still get PME when any of the
729 * enabled events is detected). Same goes with Link Layer State
730 * changed event which generates PME immediately when the link goes
731 * inactive so mask it as well.
732 */
733 mask = PCI_EXP_SLTCTL_HPIE | PCI_EXP_SLTCTL_DLLSCE;
734 pcie_write_cmd(ctrl, 0, mask);
735}
736
737/*
738 * pciehp has a 1:1 bus:slot relationship so we ultimately want a secondary
739 * bus reset of the bridge, but at the same time we want to ensure that it is
740 * not seen as a hot-unplug, followed by the hot-plug of the device. Thus,
741 * disable link state notification and presence detection change notification
742 * momentarily, if we see that they could interfere. Also, clear any spurious
743 * events after.
744 */
745int pciehp_reset_slot(struct hotplug_slot *hotplug_slot, int probe)
746{
747 struct controller *ctrl = to_ctrl(hotplug_slot);
748 struct pci_dev *pdev = ctrl_dev(ctrl);
749 u16 stat_mask = 0, ctrl_mask = 0;
750 int rc;
751
752 if (probe)
753 return 0;
754
755 down_write(&ctrl->reset_lock);
756
757 if (!ATTN_BUTTN(ctrl)) {
758 ctrl_mask |= PCI_EXP_SLTCTL_PDCE;
759 stat_mask |= PCI_EXP_SLTSTA_PDC;
760 }
761 ctrl_mask |= PCI_EXP_SLTCTL_DLLSCE;
762 stat_mask |= PCI_EXP_SLTSTA_DLLSC;
763
764 pcie_write_cmd(ctrl, 0, ctrl_mask);
765 ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
766 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, 0);
767
768 rc = pci_bridge_secondary_bus_reset(ctrl->pcie->port);
769
770 pcie_capability_write_word(pdev, PCI_EXP_SLTSTA, stat_mask);
771 pcie_write_cmd_nowait(ctrl, ctrl_mask, ctrl_mask);
772 ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
773 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, ctrl_mask);
774
775 up_write(&ctrl->reset_lock);
776 return rc;
777}
778
779int pcie_init_notification(struct controller *ctrl)
780{
781 if (pciehp_request_irq(ctrl))
782 return -1;
783 pcie_enable_notification(ctrl);
784 ctrl->notification_enabled = 1;
785 return 0;
786}
787
788void pcie_shutdown_notification(struct controller *ctrl)
789{
790 if (ctrl->notification_enabled) {
791 pcie_disable_notification(ctrl);
792 pciehp_free_irq(ctrl);
793 ctrl->notification_enabled = 0;
794 }
795}
796
797static inline void dbg_ctrl(struct controller *ctrl)
798{
799 struct pci_dev *pdev = ctrl->pcie->port;
800 u16 reg16;
801
802 ctrl_dbg(ctrl, "Slot Capabilities : 0x%08x\n", ctrl->slot_cap);
803 pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, ®16);
804 ctrl_dbg(ctrl, "Slot Status : 0x%04x\n", reg16);
805 pcie_capability_read_word(pdev, PCI_EXP_SLTCTL, ®16);
806 ctrl_dbg(ctrl, "Slot Control : 0x%04x\n", reg16);
807}
808
809#define FLAG(x, y) (((x) & (y)) ? '+' : '-')
810
811struct controller *pcie_init(struct pcie_device *dev)
812{
813 struct controller *ctrl;
814 u32 slot_cap, link_cap;
815 u8 poweron;
816 struct pci_dev *pdev = dev->port;
817 struct pci_bus *subordinate = pdev->subordinate;
818
819 ctrl = kzalloc(sizeof(*ctrl), GFP_KERNEL);
820 if (!ctrl)
821 return NULL;
822
823 ctrl->pcie = dev;
824 pcie_capability_read_dword(pdev, PCI_EXP_SLTCAP, &slot_cap);
825
826 if (pdev->hotplug_user_indicators)
827 slot_cap &= ~(PCI_EXP_SLTCAP_AIP | PCI_EXP_SLTCAP_PIP);
828
829 /*
830 * We assume no Thunderbolt controllers support Command Complete events,
831 * but some controllers falsely claim they do.
832 */
833 if (pdev->is_thunderbolt)
834 slot_cap |= PCI_EXP_SLTCAP_NCCS;
835
836 ctrl->slot_cap = slot_cap;
837 mutex_init(&ctrl->ctrl_lock);
838 mutex_init(&ctrl->state_lock);
839 init_rwsem(&ctrl->reset_lock);
840 init_waitqueue_head(&ctrl->requester);
841 init_waitqueue_head(&ctrl->queue);
842 INIT_DELAYED_WORK(&ctrl->button_work, pciehp_queue_pushbutton_work);
843 dbg_ctrl(ctrl);
844
845 down_read(&pci_bus_sem);
846 ctrl->state = list_empty(&subordinate->devices) ? OFF_STATE : ON_STATE;
847 up_read(&pci_bus_sem);
848
849 /* Check if Data Link Layer Link Active Reporting is implemented */
850 pcie_capability_read_dword(pdev, PCI_EXP_LNKCAP, &link_cap);
851
852 /* Clear all remaining event bits in Slot Status register. */
853 pcie_capability_write_word(pdev, PCI_EXP_SLTSTA,
854 PCI_EXP_SLTSTA_ABP | PCI_EXP_SLTSTA_PFD |
855 PCI_EXP_SLTSTA_MRLSC | PCI_EXP_SLTSTA_CC |
856 PCI_EXP_SLTSTA_DLLSC | PCI_EXP_SLTSTA_PDC);
857
858 ctrl_info(ctrl, "Slot #%d AttnBtn%c PwrCtrl%c MRL%c AttnInd%c PwrInd%c HotPlug%c Surprise%c Interlock%c NoCompl%c LLActRep%c%s\n",
859 (slot_cap & PCI_EXP_SLTCAP_PSN) >> 19,
860 FLAG(slot_cap, PCI_EXP_SLTCAP_ABP),
861 FLAG(slot_cap, PCI_EXP_SLTCAP_PCP),
862 FLAG(slot_cap, PCI_EXP_SLTCAP_MRLSP),
863 FLAG(slot_cap, PCI_EXP_SLTCAP_AIP),
864 FLAG(slot_cap, PCI_EXP_SLTCAP_PIP),
865 FLAG(slot_cap, PCI_EXP_SLTCAP_HPC),
866 FLAG(slot_cap, PCI_EXP_SLTCAP_HPS),
867 FLAG(slot_cap, PCI_EXP_SLTCAP_EIP),
868 FLAG(slot_cap, PCI_EXP_SLTCAP_NCCS),
869 FLAG(link_cap, PCI_EXP_LNKCAP_DLLLARC),
870 pdev->broken_cmd_compl ? " (with Cmd Compl erratum)" : "");
871
872 /*
873 * If empty slot's power status is on, turn power off. The IRQ isn't
874 * requested yet, so avoid triggering a notification with this command.
875 */
876 if (POWER_CTRL(ctrl)) {
877 pciehp_get_power_status(ctrl, &poweron);
878 if (!pciehp_card_present_or_link_active(ctrl) && poweron) {
879 pcie_disable_notification(ctrl);
880 pciehp_power_off_slot(ctrl);
881 }
882 }
883
884 return ctrl;
885}
886
887void pciehp_release_ctrl(struct controller *ctrl)
888{
889 cancel_delayed_work_sync(&ctrl->button_work);
890 kfree(ctrl);
891}
892
893static void quirk_cmd_compl(struct pci_dev *pdev)
894{
895 u32 slot_cap;
896
897 if (pci_is_pcie(pdev)) {
898 pcie_capability_read_dword(pdev, PCI_EXP_SLTCAP, &slot_cap);
899 if (slot_cap & PCI_EXP_SLTCAP_HPC &&
900 !(slot_cap & PCI_EXP_SLTCAP_NCCS))
901 pdev->broken_cmd_compl = 1;
902 }
903}
904DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, PCI_ANY_ID,
905 PCI_CLASS_BRIDGE_PCI, 8, quirk_cmd_compl);
906DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_QCOM, 0x0400,
907 PCI_CLASS_BRIDGE_PCI, 8, quirk_cmd_compl);
908DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_QCOM, 0x0401,
909 PCI_CLASS_BRIDGE_PCI, 8, quirk_cmd_compl);
910DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_HXT, 0x0401,
911 PCI_CLASS_BRIDGE_PCI, 8, quirk_cmd_compl);