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1/*
2 * This file is part of wl1271
3 *
4 * Copyright (C) 2008-2009 Nokia Corporation
5 *
6 * Contact: Luciano Coelho <luciano.coelho@nokia.com>
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License
10 * version 2 as published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope that it will be useful, but
13 * WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
20 * 02110-1301 USA
21 *
22 */
23
24#include <linux/interrupt.h>
25#include <linux/irq.h>
26#include <linux/module.h>
27#include <linux/crc7.h>
28#include <linux/spi/spi.h>
29#include <linux/wl12xx.h>
30#include <linux/slab.h>
31
32#include "wl12xx.h"
33#include "wl12xx_80211.h"
34#include "io.h"
35
36#include "reg.h"
37
38#define WSPI_CMD_READ 0x40000000
39#define WSPI_CMD_WRITE 0x00000000
40#define WSPI_CMD_FIXED 0x20000000
41#define WSPI_CMD_BYTE_LENGTH 0x1FFE0000
42#define WSPI_CMD_BYTE_LENGTH_OFFSET 17
43#define WSPI_CMD_BYTE_ADDR 0x0001FFFF
44
45#define WSPI_INIT_CMD_CRC_LEN 5
46
47#define WSPI_INIT_CMD_START 0x00
48#define WSPI_INIT_CMD_TX 0x40
49/* the extra bypass bit is sampled by the TNET as '1' */
50#define WSPI_INIT_CMD_BYPASS_BIT 0x80
51#define WSPI_INIT_CMD_FIXEDBUSY_LEN 0x07
52#define WSPI_INIT_CMD_EN_FIXEDBUSY 0x80
53#define WSPI_INIT_CMD_DIS_FIXEDBUSY 0x00
54#define WSPI_INIT_CMD_IOD 0x40
55#define WSPI_INIT_CMD_IP 0x20
56#define WSPI_INIT_CMD_CS 0x10
57#define WSPI_INIT_CMD_WS 0x08
58#define WSPI_INIT_CMD_WSPI 0x01
59#define WSPI_INIT_CMD_END 0x01
60
61#define WSPI_INIT_CMD_LEN 8
62
63#define HW_ACCESS_WSPI_FIXED_BUSY_LEN \
64 ((WL1271_BUSY_WORD_LEN - 4) / sizeof(u32))
65#define HW_ACCESS_WSPI_INIT_CMD_MASK 0
66
67/* HW limitation: maximum possible chunk size is 4095 bytes */
68#define WSPI_MAX_CHUNK_SIZE 4092
69
70#define WSPI_MAX_NUM_OF_CHUNKS (WL1271_AGGR_BUFFER_SIZE / WSPI_MAX_CHUNK_SIZE)
71
72static inline struct spi_device *wl_to_spi(struct wl1271 *wl)
73{
74 return wl->if_priv;
75}
76
77static struct device *wl1271_spi_wl_to_dev(struct wl1271 *wl)
78{
79 return &(wl_to_spi(wl)->dev);
80}
81
82static void wl1271_spi_disable_interrupts(struct wl1271 *wl)
83{
84 disable_irq(wl->irq);
85}
86
87static void wl1271_spi_enable_interrupts(struct wl1271 *wl)
88{
89 enable_irq(wl->irq);
90}
91
92static void wl1271_spi_reset(struct wl1271 *wl)
93{
94 u8 *cmd;
95 struct spi_transfer t;
96 struct spi_message m;
97
98 cmd = kzalloc(WSPI_INIT_CMD_LEN, GFP_KERNEL);
99 if (!cmd) {
100 wl1271_error("could not allocate cmd for spi reset");
101 return;
102 }
103
104 memset(&t, 0, sizeof(t));
105 spi_message_init(&m);
106
107 memset(cmd, 0xff, WSPI_INIT_CMD_LEN);
108
109 t.tx_buf = cmd;
110 t.len = WSPI_INIT_CMD_LEN;
111 spi_message_add_tail(&t, &m);
112
113 spi_sync(wl_to_spi(wl), &m);
114
115 wl1271_dump(DEBUG_SPI, "spi reset -> ", cmd, WSPI_INIT_CMD_LEN);
116 kfree(cmd);
117}
118
119static void wl1271_spi_init(struct wl1271 *wl)
120{
121 u8 crc[WSPI_INIT_CMD_CRC_LEN], *cmd;
122 struct spi_transfer t;
123 struct spi_message m;
124
125 cmd = kzalloc(WSPI_INIT_CMD_LEN, GFP_KERNEL);
126 if (!cmd) {
127 wl1271_error("could not allocate cmd for spi init");
128 return;
129 }
130
131 memset(crc, 0, sizeof(crc));
132 memset(&t, 0, sizeof(t));
133 spi_message_init(&m);
134
135 /*
136 * Set WSPI_INIT_COMMAND
137 * the data is being send from the MSB to LSB
138 */
139 cmd[2] = 0xff;
140 cmd[3] = 0xff;
141 cmd[1] = WSPI_INIT_CMD_START | WSPI_INIT_CMD_TX;
142 cmd[0] = 0;
143 cmd[7] = 0;
144 cmd[6] |= HW_ACCESS_WSPI_INIT_CMD_MASK << 3;
145 cmd[6] |= HW_ACCESS_WSPI_FIXED_BUSY_LEN & WSPI_INIT_CMD_FIXEDBUSY_LEN;
146
147 if (HW_ACCESS_WSPI_FIXED_BUSY_LEN == 0)
148 cmd[5] |= WSPI_INIT_CMD_DIS_FIXEDBUSY;
149 else
150 cmd[5] |= WSPI_INIT_CMD_EN_FIXEDBUSY;
151
152 cmd[5] |= WSPI_INIT_CMD_IOD | WSPI_INIT_CMD_IP | WSPI_INIT_CMD_CS
153 | WSPI_INIT_CMD_WSPI | WSPI_INIT_CMD_WS;
154
155 crc[0] = cmd[1];
156 crc[1] = cmd[0];
157 crc[2] = cmd[7];
158 crc[3] = cmd[6];
159 crc[4] = cmd[5];
160
161 cmd[4] |= crc7(0, crc, WSPI_INIT_CMD_CRC_LEN) << 1;
162 cmd[4] |= WSPI_INIT_CMD_END;
163
164 t.tx_buf = cmd;
165 t.len = WSPI_INIT_CMD_LEN;
166 spi_message_add_tail(&t, &m);
167
168 spi_sync(wl_to_spi(wl), &m);
169 wl1271_dump(DEBUG_SPI, "spi init -> ", cmd, WSPI_INIT_CMD_LEN);
170 kfree(cmd);
171}
172
173#define WL1271_BUSY_WORD_TIMEOUT 1000
174
175static int wl1271_spi_read_busy(struct wl1271 *wl)
176{
177 struct spi_transfer t[1];
178 struct spi_message m;
179 u32 *busy_buf;
180 int num_busy_bytes = 0;
181
182 /*
183 * Read further busy words from SPI until a non-busy word is
184 * encountered, then read the data itself into the buffer.
185 */
186
187 num_busy_bytes = WL1271_BUSY_WORD_TIMEOUT;
188 busy_buf = wl->buffer_busyword;
189 while (num_busy_bytes) {
190 num_busy_bytes--;
191 spi_message_init(&m);
192 memset(t, 0, sizeof(t));
193 t[0].rx_buf = busy_buf;
194 t[0].len = sizeof(u32);
195 t[0].cs_change = true;
196 spi_message_add_tail(&t[0], &m);
197 spi_sync(wl_to_spi(wl), &m);
198
199 if (*busy_buf & 0x1)
200 return 0;
201 }
202
203 /* The SPI bus is unresponsive, the read failed. */
204 wl1271_error("SPI read busy-word timeout!\n");
205 return -ETIMEDOUT;
206}
207
208static void wl1271_spi_raw_read(struct wl1271 *wl, int addr, void *buf,
209 size_t len, bool fixed)
210{
211 struct spi_transfer t[2];
212 struct spi_message m;
213 u32 *busy_buf;
214 u32 *cmd;
215 u32 chunk_len;
216
217 while (len > 0) {
218 chunk_len = min((size_t)WSPI_MAX_CHUNK_SIZE, len);
219
220 cmd = &wl->buffer_cmd;
221 busy_buf = wl->buffer_busyword;
222
223 *cmd = 0;
224 *cmd |= WSPI_CMD_READ;
225 *cmd |= (chunk_len << WSPI_CMD_BYTE_LENGTH_OFFSET) &
226 WSPI_CMD_BYTE_LENGTH;
227 *cmd |= addr & WSPI_CMD_BYTE_ADDR;
228
229 if (fixed)
230 *cmd |= WSPI_CMD_FIXED;
231
232 spi_message_init(&m);
233 memset(t, 0, sizeof(t));
234
235 t[0].tx_buf = cmd;
236 t[0].len = 4;
237 t[0].cs_change = true;
238 spi_message_add_tail(&t[0], &m);
239
240 /* Busy and non busy words read */
241 t[1].rx_buf = busy_buf;
242 t[1].len = WL1271_BUSY_WORD_LEN;
243 t[1].cs_change = true;
244 spi_message_add_tail(&t[1], &m);
245
246 spi_sync(wl_to_spi(wl), &m);
247
248 if (!(busy_buf[WL1271_BUSY_WORD_CNT - 1] & 0x1) &&
249 wl1271_spi_read_busy(wl)) {
250 memset(buf, 0, chunk_len);
251 return;
252 }
253
254 spi_message_init(&m);
255 memset(t, 0, sizeof(t));
256
257 t[0].rx_buf = buf;
258 t[0].len = chunk_len;
259 t[0].cs_change = true;
260 spi_message_add_tail(&t[0], &m);
261
262 spi_sync(wl_to_spi(wl), &m);
263
264 wl1271_dump(DEBUG_SPI, "spi_read cmd -> ", cmd, sizeof(*cmd));
265 wl1271_dump(DEBUG_SPI, "spi_read buf <- ", buf, chunk_len);
266
267 if (!fixed)
268 addr += chunk_len;
269 buf += chunk_len;
270 len -= chunk_len;
271 }
272}
273
274static void wl1271_spi_raw_write(struct wl1271 *wl, int addr, void *buf,
275 size_t len, bool fixed)
276{
277 struct spi_transfer t[2 * WSPI_MAX_NUM_OF_CHUNKS];
278 struct spi_message m;
279 u32 commands[WSPI_MAX_NUM_OF_CHUNKS];
280 u32 *cmd;
281 u32 chunk_len;
282 int i;
283
284 WARN_ON(len > WL1271_AGGR_BUFFER_SIZE);
285
286 spi_message_init(&m);
287 memset(t, 0, sizeof(t));
288
289 cmd = &commands[0];
290 i = 0;
291 while (len > 0) {
292 chunk_len = min((size_t)WSPI_MAX_CHUNK_SIZE, len);
293
294 *cmd = 0;
295 *cmd |= WSPI_CMD_WRITE;
296 *cmd |= (chunk_len << WSPI_CMD_BYTE_LENGTH_OFFSET) &
297 WSPI_CMD_BYTE_LENGTH;
298 *cmd |= addr & WSPI_CMD_BYTE_ADDR;
299
300 if (fixed)
301 *cmd |= WSPI_CMD_FIXED;
302
303 t[i].tx_buf = cmd;
304 t[i].len = sizeof(*cmd);
305 spi_message_add_tail(&t[i++], &m);
306
307 t[i].tx_buf = buf;
308 t[i].len = chunk_len;
309 spi_message_add_tail(&t[i++], &m);
310
311 wl1271_dump(DEBUG_SPI, "spi_write cmd -> ", cmd, sizeof(*cmd));
312 wl1271_dump(DEBUG_SPI, "spi_write buf -> ", buf, chunk_len);
313
314 if (!fixed)
315 addr += chunk_len;
316 buf += chunk_len;
317 len -= chunk_len;
318 cmd++;
319 }
320
321 spi_sync(wl_to_spi(wl), &m);
322}
323
324static irqreturn_t wl1271_hardirq(int irq, void *cookie)
325{
326 struct wl1271 *wl = cookie;
327 unsigned long flags;
328
329 wl1271_debug(DEBUG_IRQ, "IRQ");
330
331 /* complete the ELP completion */
332 spin_lock_irqsave(&wl->wl_lock, flags);
333 set_bit(WL1271_FLAG_IRQ_RUNNING, &wl->flags);
334 if (wl->elp_compl) {
335 complete(wl->elp_compl);
336 wl->elp_compl = NULL;
337 }
338 spin_unlock_irqrestore(&wl->wl_lock, flags);
339
340 return IRQ_WAKE_THREAD;
341}
342
343static int wl1271_spi_set_power(struct wl1271 *wl, bool enable)
344{
345 if (wl->set_power)
346 wl->set_power(enable);
347
348 return 0;
349}
350
351static struct wl1271_if_operations spi_ops = {
352 .read = wl1271_spi_raw_read,
353 .write = wl1271_spi_raw_write,
354 .reset = wl1271_spi_reset,
355 .init = wl1271_spi_init,
356 .power = wl1271_spi_set_power,
357 .dev = wl1271_spi_wl_to_dev,
358 .enable_irq = wl1271_spi_enable_interrupts,
359 .disable_irq = wl1271_spi_disable_interrupts,
360 .set_block_size = NULL,
361};
362
363static int __devinit wl1271_probe(struct spi_device *spi)
364{
365 struct wl12xx_platform_data *pdata;
366 struct ieee80211_hw *hw;
367 struct wl1271 *wl;
368 unsigned long irqflags;
369 int ret;
370
371 pdata = spi->dev.platform_data;
372 if (!pdata) {
373 wl1271_error("no platform data");
374 return -ENODEV;
375 }
376
377 hw = wl1271_alloc_hw();
378 if (IS_ERR(hw))
379 return PTR_ERR(hw);
380
381 wl = hw->priv;
382
383 dev_set_drvdata(&spi->dev, wl);
384 wl->if_priv = spi;
385
386 wl->if_ops = &spi_ops;
387
388 /* This is the only SPI value that we need to set here, the rest
389 * comes from the board-peripherals file */
390 spi->bits_per_word = 32;
391
392 ret = spi_setup(spi);
393 if (ret < 0) {
394 wl1271_error("spi_setup failed");
395 goto out_free;
396 }
397
398 wl->set_power = pdata->set_power;
399 if (!wl->set_power) {
400 wl1271_error("set power function missing in platform data");
401 ret = -ENODEV;
402 goto out_free;
403 }
404
405 wl->ref_clock = pdata->board_ref_clock;
406 wl->tcxo_clock = pdata->board_tcxo_clock;
407 wl->platform_quirks = pdata->platform_quirks;
408
409 if (wl->platform_quirks & WL12XX_PLATFORM_QUIRK_EDGE_IRQ)
410 irqflags = IRQF_TRIGGER_RISING;
411 else
412 irqflags = IRQF_TRIGGER_HIGH | IRQF_ONESHOT;
413
414 wl->irq = spi->irq;
415 if (wl->irq < 0) {
416 wl1271_error("irq missing in platform data");
417 ret = -ENODEV;
418 goto out_free;
419 }
420
421 ret = request_threaded_irq(wl->irq, wl1271_hardirq, wl1271_irq,
422 irqflags,
423 DRIVER_NAME, wl);
424 if (ret < 0) {
425 wl1271_error("request_irq() failed: %d", ret);
426 goto out_free;
427 }
428
429 disable_irq(wl->irq);
430
431 ret = wl1271_init_ieee80211(wl);
432 if (ret)
433 goto out_irq;
434
435 ret = wl1271_register_hw(wl);
436 if (ret)
437 goto out_irq;
438
439 return 0;
440
441 out_irq:
442 free_irq(wl->irq, wl);
443
444 out_free:
445 wl1271_free_hw(wl);
446
447 return ret;
448}
449
450static int __devexit wl1271_remove(struct spi_device *spi)
451{
452 struct wl1271 *wl = dev_get_drvdata(&spi->dev);
453
454 wl1271_unregister_hw(wl);
455 free_irq(wl->irq, wl);
456 wl1271_free_hw(wl);
457
458 return 0;
459}
460
461
462static struct spi_driver wl1271_spi_driver = {
463 .driver = {
464 .name = "wl1271_spi",
465 .bus = &spi_bus_type,
466 .owner = THIS_MODULE,
467 },
468
469 .probe = wl1271_probe,
470 .remove = __devexit_p(wl1271_remove),
471};
472
473static int __init wl1271_init(void)
474{
475 return spi_register_driver(&wl1271_spi_driver);
476}
477
478static void __exit wl1271_exit(void)
479{
480 spi_unregister_driver(&wl1271_spi_driver);
481}
482
483module_init(wl1271_init);
484module_exit(wl1271_exit);
485
486MODULE_LICENSE("GPL");
487MODULE_AUTHOR("Luciano Coelho <coelho@ti.com>");
488MODULE_AUTHOR("Juuso Oikarinen <juuso.oikarinen@nokia.com>");
489MODULE_FIRMWARE(WL1271_FW_NAME);
490MODULE_FIRMWARE(WL128X_FW_NAME);
491MODULE_FIRMWARE(WL127X_AP_FW_NAME);
492MODULE_FIRMWARE(WL128X_AP_FW_NAME);
493MODULE_ALIAS("spi:wl1271");