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1/*
2 * This file is part of wl1271
3 *
4 * Copyright (C) 1998-2009 Texas Instruments. All rights reserved.
5 * Copyright (C) 2008-2010 Nokia Corporation
6 *
7 * Contact: Luciano Coelho <luciano.coelho@nokia.com>
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * version 2 as published by the Free Software Foundation.
12 *
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
21 * 02110-1301 USA
22 *
23 */
24
25#ifndef __ACX_H__
26#define __ACX_H__
27
28#include "wl12xx.h"
29#include "cmd.h"
30
31/*************************************************************************
32
33 Host Interrupt Register (WiLink -> Host)
34
35**************************************************************************/
36/* HW Initiated interrupt Watchdog timer expiration */
37#define WL1271_ACX_INTR_WATCHDOG BIT(0)
38/* Init sequence is done (masked interrupt, detection through polling only ) */
39#define WL1271_ACX_INTR_INIT_COMPLETE BIT(1)
40/* Event was entered to Event MBOX #A*/
41#define WL1271_ACX_INTR_EVENT_A BIT(2)
42/* Event was entered to Event MBOX #B*/
43#define WL1271_ACX_INTR_EVENT_B BIT(3)
44/* Command processing completion*/
45#define WL1271_ACX_INTR_CMD_COMPLETE BIT(4)
46/* Signaling the host on HW wakeup */
47#define WL1271_ACX_INTR_HW_AVAILABLE BIT(5)
48/* The MISC bit is used for aggregation of RX, TxComplete and TX rate update */
49#define WL1271_ACX_INTR_DATA BIT(6)
50/* Trace message on MBOX #A */
51#define WL1271_ACX_INTR_TRACE_A BIT(7)
52/* Trace message on MBOX #B */
53#define WL1271_ACX_INTR_TRACE_B BIT(8)
54
55#define WL1271_ACX_INTR_ALL 0xFFFFFFFF
56#define WL1271_ACX_ALL_EVENTS_VECTOR (WL1271_ACX_INTR_WATCHDOG | \
57 WL1271_ACX_INTR_INIT_COMPLETE | \
58 WL1271_ACX_INTR_EVENT_A | \
59 WL1271_ACX_INTR_EVENT_B | \
60 WL1271_ACX_INTR_CMD_COMPLETE | \
61 WL1271_ACX_INTR_HW_AVAILABLE | \
62 WL1271_ACX_INTR_DATA)
63
64#define WL1271_INTR_MASK (WL1271_ACX_INTR_WATCHDOG | \
65 WL1271_ACX_INTR_EVENT_A | \
66 WL1271_ACX_INTR_EVENT_B | \
67 WL1271_ACX_INTR_HW_AVAILABLE | \
68 WL1271_ACX_INTR_DATA)
69
70/* Target's information element */
71struct acx_header {
72 struct wl1271_cmd_header cmd;
73
74 /* acx (or information element) header */
75 __le16 id;
76
77 /* payload length (not including headers */
78 __le16 len;
79} __packed;
80
81struct acx_error_counter {
82 struct acx_header header;
83
84 /* The number of PLCP errors since the last time this */
85 /* information element was interrogated. This field is */
86 /* automatically cleared when it is interrogated.*/
87 __le32 PLCP_error;
88
89 /* The number of FCS errors since the last time this */
90 /* information element was interrogated. This field is */
91 /* automatically cleared when it is interrogated.*/
92 __le32 FCS_error;
93
94 /* The number of MPDUs without PLCP header errors received*/
95 /* since the last time this information element was interrogated. */
96 /* This field is automatically cleared when it is interrogated.*/
97 __le32 valid_frame;
98
99 /* the number of missed sequence numbers in the squentially */
100 /* values of frames seq numbers */
101 __le32 seq_num_miss;
102} __packed;
103
104enum wl1271_psm_mode {
105 /* Active mode */
106 WL1271_PSM_CAM = 0,
107
108 /* Power save mode */
109 WL1271_PSM_PS = 1,
110
111 /* Extreme low power */
112 WL1271_PSM_ELP = 2,
113};
114
115struct acx_sleep_auth {
116 struct acx_header header;
117
118 /* The sleep level authorization of the device. */
119 /* 0 - Always active*/
120 /* 1 - Power down mode: light / fast sleep*/
121 /* 2 - ELP mode: Deep / Max sleep*/
122 u8 sleep_auth;
123 u8 padding[3];
124} __packed;
125
126enum {
127 HOSTIF_PCI_MASTER_HOST_INDIRECT,
128 HOSTIF_PCI_MASTER_HOST_DIRECT,
129 HOSTIF_SLAVE,
130 HOSTIF_PKT_RING,
131 HOSTIF_DONTCARE = 0xFF
132};
133
134#define DEFAULT_UCAST_PRIORITY 0
135#define DEFAULT_RX_Q_PRIORITY 0
136#define DEFAULT_RXQ_PRIORITY 0 /* low 0 .. 15 high */
137#define DEFAULT_RXQ_TYPE 0x07 /* All frames, Data/Ctrl/Mgmt */
138#define TRACE_BUFFER_MAX_SIZE 256
139
140#define DP_RX_PACKET_RING_CHUNK_SIZE 1600
141#define DP_TX_PACKET_RING_CHUNK_SIZE 1600
142#define DP_RX_PACKET_RING_CHUNK_NUM 2
143#define DP_TX_PACKET_RING_CHUNK_NUM 2
144#define DP_TX_COMPLETE_TIME_OUT 20
145
146#define TX_MSDU_LIFETIME_MIN 0
147#define TX_MSDU_LIFETIME_MAX 3000
148#define TX_MSDU_LIFETIME_DEF 512
149#define RX_MSDU_LIFETIME_MIN 0
150#define RX_MSDU_LIFETIME_MAX 0xFFFFFFFF
151#define RX_MSDU_LIFETIME_DEF 512000
152
153struct acx_rx_msdu_lifetime {
154 struct acx_header header;
155
156 /*
157 * The maximum amount of time, in TU, before the
158 * firmware discards the MSDU.
159 */
160 __le32 lifetime;
161} __packed;
162
163/*
164 * RX Config Options Table
165 * Bit Definition
166 * === ==========
167 * 31:14 Reserved
168 * 13 Copy RX Status - when set, write three receive status words
169 * to top of rx'd MPDUs.
170 * When cleared, do not write three status words (added rev 1.5)
171 * 12 Reserved
172 * 11 RX Complete upon FCS error - when set, give rx complete
173 * interrupt for FCS errors, after the rx filtering, e.g. unicast
174 * frames not to us with FCS error will not generate an interrupt.
175 * 10 SSID Filter Enable - When set, the WiLink discards all beacon,
176 * probe request, and probe response frames with an SSID that does
177 * not match the SSID specified by the host in the START/JOIN
178 * command.
179 * When clear, the WiLink receives frames with any SSID.
180 * 9 Broadcast Filter Enable - When set, the WiLink discards all
181 * broadcast frames. When clear, the WiLink receives all received
182 * broadcast frames.
183 * 8:6 Reserved
184 * 5 BSSID Filter Enable - When set, the WiLink discards any frames
185 * with a BSSID that does not match the BSSID specified by the
186 * host.
187 * When clear, the WiLink receives frames from any BSSID.
188 * 4 MAC Addr Filter - When set, the WiLink discards any frames
189 * with a destination address that does not match the MAC address
190 * of the adaptor.
191 * When clear, the WiLink receives frames destined to any MAC
192 * address.
193 * 3 Promiscuous - When set, the WiLink receives all valid frames
194 * (i.e., all frames that pass the FCS check).
195 * When clear, only frames that pass the other filters specified
196 * are received.
197 * 2 FCS - When set, the WiLink includes the FCS with the received
198 * frame.
199 * When cleared, the FCS is discarded.
200 * 1 PLCP header - When set, write all data from baseband to frame
201 * buffer including PHY header.
202 * 0 Reserved - Always equal to 0.
203 *
204 * RX Filter Options Table
205 * Bit Definition
206 * === ==========
207 * 31:12 Reserved - Always equal to 0.
208 * 11 Association - When set, the WiLink receives all association
209 * related frames (association request/response, reassocation
210 * request/response, and disassociation). When clear, these frames
211 * are discarded.
212 * 10 Auth/De auth - When set, the WiLink receives all authentication
213 * and de-authentication frames. When clear, these frames are
214 * discarded.
215 * 9 Beacon - When set, the WiLink receives all beacon frames.
216 * When clear, these frames are discarded.
217 * 8 Contention Free - When set, the WiLink receives all contention
218 * free frames.
219 * When clear, these frames are discarded.
220 * 7 Control - When set, the WiLink receives all control frames.
221 * When clear, these frames are discarded.
222 * 6 Data - When set, the WiLink receives all data frames.
223 * When clear, these frames are discarded.
224 * 5 FCS Error - When set, the WiLink receives frames that have FCS
225 * errors.
226 * When clear, these frames are discarded.
227 * 4 Management - When set, the WiLink receives all management
228 * frames.
229 * When clear, these frames are discarded.
230 * 3 Probe Request - When set, the WiLink receives all probe request
231 * frames.
232 * When clear, these frames are discarded.
233 * 2 Probe Response - When set, the WiLink receives all probe
234 * response frames.
235 * When clear, these frames are discarded.
236 * 1 RTS/CTS/ACK - When set, the WiLink receives all RTS, CTS and ACK
237 * frames.
238 * When clear, these frames are discarded.
239 * 0 Rsvd Type/Sub Type - When set, the WiLink receives all frames
240 * that have reserved frame types and sub types as defined by the
241 * 802.11 specification.
242 * When clear, these frames are discarded.
243 */
244struct acx_rx_config {
245 struct acx_header header;
246
247 __le32 config_options;
248 __le32 filter_options;
249} __packed;
250
251struct acx_packet_detection {
252 struct acx_header header;
253
254 __le32 threshold;
255} __packed;
256
257
258enum acx_slot_type {
259 SLOT_TIME_LONG = 0,
260 SLOT_TIME_SHORT = 1,
261 DEFAULT_SLOT_TIME = SLOT_TIME_SHORT,
262 MAX_SLOT_TIMES = 0xFF
263};
264
265#define STATION_WONE_INDEX 0
266
267struct acx_slot {
268 struct acx_header header;
269
270 u8 wone_index; /* Reserved */
271 u8 slot_time;
272 u8 reserved[6];
273} __packed;
274
275
276#define ACX_MC_ADDRESS_GROUP_MAX (8)
277#define ADDRESS_GROUP_MAX_LEN (ETH_ALEN * ACX_MC_ADDRESS_GROUP_MAX)
278
279struct acx_dot11_grp_addr_tbl {
280 struct acx_header header;
281
282 u8 enabled;
283 u8 num_groups;
284 u8 pad[2];
285 u8 mac_table[ADDRESS_GROUP_MAX_LEN];
286} __packed;
287
288struct acx_rx_timeout {
289 struct acx_header header;
290
291 __le16 ps_poll_timeout;
292 __le16 upsd_timeout;
293} __packed;
294
295struct acx_rts_threshold {
296 struct acx_header header;
297
298 __le16 threshold;
299 u8 pad[2];
300} __packed;
301
302struct acx_beacon_filter_option {
303 struct acx_header header;
304
305 u8 enable;
306 /*
307 * The number of beacons without the unicast TIM
308 * bit set that the firmware buffers before
309 * signaling the host about ready frames.
310 * When set to 0 and the filter is enabled, beacons
311 * without the unicast TIM bit set are dropped.
312 */
313 u8 max_num_beacons;
314 u8 pad[2];
315} __packed;
316
317/*
318 * ACXBeaconFilterEntry (not 221)
319 * Byte Offset Size (Bytes) Definition
320 * =========== ============ ==========
321 * 0 1 IE identifier
322 * 1 1 Treatment bit mask
323 *
324 * ACXBeaconFilterEntry (221)
325 * Byte Offset Size (Bytes) Definition
326 * =========== ============ ==========
327 * 0 1 IE identifier
328 * 1 1 Treatment bit mask
329 * 2 3 OUI
330 * 5 1 Type
331 * 6 2 Version
332 *
333 *
334 * Treatment bit mask - The information element handling:
335 * bit 0 - The information element is compared and transferred
336 * in case of change.
337 * bit 1 - The information element is transferred to the host
338 * with each appearance or disappearance.
339 * Note that both bits can be set at the same time.
340 */
341#define BEACON_FILTER_TABLE_MAX_IE_NUM (32)
342#define BEACON_FILTER_TABLE_MAX_VENDOR_SPECIFIC_IE_NUM (6)
343#define BEACON_FILTER_TABLE_IE_ENTRY_SIZE (2)
344#define BEACON_FILTER_TABLE_EXTRA_VENDOR_SPECIFIC_IE_SIZE (6)
345#define BEACON_FILTER_TABLE_MAX_SIZE ((BEACON_FILTER_TABLE_MAX_IE_NUM * \
346 BEACON_FILTER_TABLE_IE_ENTRY_SIZE) + \
347 (BEACON_FILTER_TABLE_MAX_VENDOR_SPECIFIC_IE_NUM * \
348 BEACON_FILTER_TABLE_EXTRA_VENDOR_SPECIFIC_IE_SIZE))
349
350struct acx_beacon_filter_ie_table {
351 struct acx_header header;
352
353 u8 num_ie;
354 u8 pad[3];
355 u8 table[BEACON_FILTER_TABLE_MAX_SIZE];
356} __packed;
357
358struct acx_conn_monit_params {
359 struct acx_header header;
360
361 __le32 synch_fail_thold; /* number of beacons missed */
362 __le32 bss_lose_timeout; /* number of TU's from synch fail */
363} __packed;
364
365struct acx_bt_wlan_coex {
366 struct acx_header header;
367
368 u8 enable;
369 u8 pad[3];
370} __packed;
371
372struct acx_sta_bt_wlan_coex_param {
373 struct acx_header header;
374
375 __le32 params[CONF_SG_STA_PARAMS_MAX];
376 u8 param_idx;
377 u8 padding[3];
378} __packed;
379
380struct acx_ap_bt_wlan_coex_param {
381 struct acx_header header;
382
383 __le32 params[CONF_SG_AP_PARAMS_MAX];
384 u8 param_idx;
385 u8 padding[3];
386} __packed;
387
388
389struct acx_dco_itrim_params {
390 struct acx_header header;
391
392 u8 enable;
393 u8 padding[3];
394 __le32 timeout;
395} __packed;
396
397struct acx_energy_detection {
398 struct acx_header header;
399
400 /* The RX Clear Channel Assessment threshold in the PHY */
401 __le16 rx_cca_threshold;
402 u8 tx_energy_detection;
403 u8 pad;
404} __packed;
405
406struct acx_beacon_broadcast {
407 struct acx_header header;
408
409 __le16 beacon_rx_timeout;
410 __le16 broadcast_timeout;
411
412 /* Enables receiving of broadcast packets in PS mode */
413 u8 rx_broadcast_in_ps;
414
415 /* Consecutive PS Poll failures before updating the host */
416 u8 ps_poll_threshold;
417 u8 pad[2];
418} __packed;
419
420struct acx_event_mask {
421 struct acx_header header;
422
423 __le32 event_mask;
424 __le32 high_event_mask; /* Unused */
425} __packed;
426
427#define CFG_RX_FCS BIT(2)
428#define CFG_RX_ALL_GOOD BIT(3)
429#define CFG_UNI_FILTER_EN BIT(4)
430#define CFG_BSSID_FILTER_EN BIT(5)
431#define CFG_MC_FILTER_EN BIT(6)
432#define CFG_MC_ADDR0_EN BIT(7)
433#define CFG_MC_ADDR1_EN BIT(8)
434#define CFG_BC_REJECT_EN BIT(9)
435#define CFG_SSID_FILTER_EN BIT(10)
436#define CFG_RX_INT_FCS_ERROR BIT(11)
437#define CFG_RX_INT_ENCRYPTED BIT(12)
438#define CFG_RX_WR_RX_STATUS BIT(13)
439#define CFG_RX_FILTER_NULTI BIT(14)
440#define CFG_RX_RESERVE BIT(15)
441#define CFG_RX_TIMESTAMP_TSF BIT(16)
442
443#define CFG_RX_RSV_EN BIT(0)
444#define CFG_RX_RCTS_ACK BIT(1)
445#define CFG_RX_PRSP_EN BIT(2)
446#define CFG_RX_PREQ_EN BIT(3)
447#define CFG_RX_MGMT_EN BIT(4)
448#define CFG_RX_FCS_ERROR BIT(5)
449#define CFG_RX_DATA_EN BIT(6)
450#define CFG_RX_CTL_EN BIT(7)
451#define CFG_RX_CF_EN BIT(8)
452#define CFG_RX_BCN_EN BIT(9)
453#define CFG_RX_AUTH_EN BIT(10)
454#define CFG_RX_ASSOC_EN BIT(11)
455
456#define SCAN_PASSIVE BIT(0)
457#define SCAN_5GHZ_BAND BIT(1)
458#define SCAN_TRIGGERED BIT(2)
459#define SCAN_PRIORITY_HIGH BIT(3)
460
461/* When set, disable HW encryption */
462#define DF_ENCRYPTION_DISABLE 0x01
463#define DF_SNIFF_MODE_ENABLE 0x80
464
465struct acx_feature_config {
466 struct acx_header header;
467
468 __le32 options;
469 __le32 data_flow_options;
470} __packed;
471
472struct acx_current_tx_power {
473 struct acx_header header;
474
475 u8 current_tx_power;
476 u8 padding[3];
477} __packed;
478
479struct acx_wake_up_condition {
480 struct acx_header header;
481
482 u8 wake_up_event; /* Only one bit can be set */
483 u8 listen_interval;
484 u8 pad[2];
485} __packed;
486
487struct acx_aid {
488 struct acx_header header;
489
490 /*
491 * To be set when associated with an AP.
492 */
493 __le16 aid;
494 u8 pad[2];
495} __packed;
496
497enum acx_preamble_type {
498 ACX_PREAMBLE_LONG = 0,
499 ACX_PREAMBLE_SHORT = 1
500};
501
502struct acx_preamble {
503 struct acx_header header;
504
505 /*
506 * When set, the WiLink transmits the frames with a short preamble and
507 * when cleared, the WiLink transmits the frames with a long preamble.
508 */
509 u8 preamble;
510 u8 padding[3];
511} __packed;
512
513enum acx_ctsprotect_type {
514 CTSPROTECT_DISABLE = 0,
515 CTSPROTECT_ENABLE = 1
516};
517
518struct acx_ctsprotect {
519 struct acx_header header;
520 u8 ctsprotect;
521 u8 padding[3];
522} __packed;
523
524struct acx_tx_statistics {
525 __le32 internal_desc_overflow;
526} __packed;
527
528struct acx_rx_statistics {
529 __le32 out_of_mem;
530 __le32 hdr_overflow;
531 __le32 hw_stuck;
532 __le32 dropped;
533 __le32 fcs_err;
534 __le32 xfr_hint_trig;
535 __le32 path_reset;
536 __le32 reset_counter;
537} __packed;
538
539struct acx_dma_statistics {
540 __le32 rx_requested;
541 __le32 rx_errors;
542 __le32 tx_requested;
543 __le32 tx_errors;
544} __packed;
545
546struct acx_isr_statistics {
547 /* host command complete */
548 __le32 cmd_cmplt;
549
550 /* fiqisr() */
551 __le32 fiqs;
552
553 /* (INT_STS_ND & INT_TRIG_RX_HEADER) */
554 __le32 rx_headers;
555
556 /* (INT_STS_ND & INT_TRIG_RX_CMPLT) */
557 __le32 rx_completes;
558
559 /* (INT_STS_ND & INT_TRIG_NO_RX_BUF) */
560 __le32 rx_mem_overflow;
561
562 /* (INT_STS_ND & INT_TRIG_S_RX_RDY) */
563 __le32 rx_rdys;
564
565 /* irqisr() */
566 __le32 irqs;
567
568 /* (INT_STS_ND & INT_TRIG_TX_PROC) */
569 __le32 tx_procs;
570
571 /* (INT_STS_ND & INT_TRIG_DECRYPT_DONE) */
572 __le32 decrypt_done;
573
574 /* (INT_STS_ND & INT_TRIG_DMA0) */
575 __le32 dma0_done;
576
577 /* (INT_STS_ND & INT_TRIG_DMA1) */
578 __le32 dma1_done;
579
580 /* (INT_STS_ND & INT_TRIG_TX_EXC_CMPLT) */
581 __le32 tx_exch_complete;
582
583 /* (INT_STS_ND & INT_TRIG_COMMAND) */
584 __le32 commands;
585
586 /* (INT_STS_ND & INT_TRIG_RX_PROC) */
587 __le32 rx_procs;
588
589 /* (INT_STS_ND & INT_TRIG_PM_802) */
590 __le32 hw_pm_mode_changes;
591
592 /* (INT_STS_ND & INT_TRIG_ACKNOWLEDGE) */
593 __le32 host_acknowledges;
594
595 /* (INT_STS_ND & INT_TRIG_PM_PCI) */
596 __le32 pci_pm;
597
598 /* (INT_STS_ND & INT_TRIG_ACM_WAKEUP) */
599 __le32 wakeups;
600
601 /* (INT_STS_ND & INT_TRIG_LOW_RSSI) */
602 __le32 low_rssi;
603} __packed;
604
605struct acx_wep_statistics {
606 /* WEP address keys configured */
607 __le32 addr_key_count;
608
609 /* default keys configured */
610 __le32 default_key_count;
611
612 __le32 reserved;
613
614 /* number of times that WEP key not found on lookup */
615 __le32 key_not_found;
616
617 /* number of times that WEP key decryption failed */
618 __le32 decrypt_fail;
619
620 /* WEP packets decrypted */
621 __le32 packets;
622
623 /* WEP decrypt interrupts */
624 __le32 interrupt;
625} __packed;
626
627#define ACX_MISSED_BEACONS_SPREAD 10
628
629struct acx_pwr_statistics {
630 /* the amount of enters into power save mode (both PD & ELP) */
631 __le32 ps_enter;
632
633 /* the amount of enters into ELP mode */
634 __le32 elp_enter;
635
636 /* the amount of missing beacon interrupts to the host */
637 __le32 missing_bcns;
638
639 /* the amount of wake on host-access times */
640 __le32 wake_on_host;
641
642 /* the amount of wake on timer-expire */
643 __le32 wake_on_timer_exp;
644
645 /* the number of packets that were transmitted with PS bit set */
646 __le32 tx_with_ps;
647
648 /* the number of packets that were transmitted with PS bit clear */
649 __le32 tx_without_ps;
650
651 /* the number of received beacons */
652 __le32 rcvd_beacons;
653
654 /* the number of entering into PowerOn (power save off) */
655 __le32 power_save_off;
656
657 /* the number of entries into power save mode */
658 __le16 enable_ps;
659
660 /*
661 * the number of exits from power save, not including failed PS
662 * transitions
663 */
664 __le16 disable_ps;
665
666 /*
667 * the number of times the TSF counter was adjusted because
668 * of drift
669 */
670 __le32 fix_tsf_ps;
671
672 /* Gives statistics about the spread continuous missed beacons.
673 * The 16 LSB are dedicated for the PS mode.
674 * The 16 MSB are dedicated for the PS mode.
675 * cont_miss_bcns_spread[0] - single missed beacon.
676 * cont_miss_bcns_spread[1] - two continuous missed beacons.
677 * cont_miss_bcns_spread[2] - three continuous missed beacons.
678 * ...
679 * cont_miss_bcns_spread[9] - ten and more continuous missed beacons.
680 */
681 __le32 cont_miss_bcns_spread[ACX_MISSED_BEACONS_SPREAD];
682
683 /* the number of beacons in awake mode */
684 __le32 rcvd_awake_beacons;
685} __packed;
686
687struct acx_mic_statistics {
688 __le32 rx_pkts;
689 __le32 calc_failure;
690} __packed;
691
692struct acx_aes_statistics {
693 __le32 encrypt_fail;
694 __le32 decrypt_fail;
695 __le32 encrypt_packets;
696 __le32 decrypt_packets;
697 __le32 encrypt_interrupt;
698 __le32 decrypt_interrupt;
699} __packed;
700
701struct acx_event_statistics {
702 __le32 heart_beat;
703 __le32 calibration;
704 __le32 rx_mismatch;
705 __le32 rx_mem_empty;
706 __le32 rx_pool;
707 __le32 oom_late;
708 __le32 phy_transmit_error;
709 __le32 tx_stuck;
710} __packed;
711
712struct acx_ps_statistics {
713 __le32 pspoll_timeouts;
714 __le32 upsd_timeouts;
715 __le32 upsd_max_sptime;
716 __le32 upsd_max_apturn;
717 __le32 pspoll_max_apturn;
718 __le32 pspoll_utilization;
719 __le32 upsd_utilization;
720} __packed;
721
722struct acx_rxpipe_statistics {
723 __le32 rx_prep_beacon_drop;
724 __le32 descr_host_int_trig_rx_data;
725 __le32 beacon_buffer_thres_host_int_trig_rx_data;
726 __le32 missed_beacon_host_int_trig_rx_data;
727 __le32 tx_xfr_host_int_trig_rx_data;
728} __packed;
729
730struct acx_statistics {
731 struct acx_header header;
732
733 struct acx_tx_statistics tx;
734 struct acx_rx_statistics rx;
735 struct acx_dma_statistics dma;
736 struct acx_isr_statistics isr;
737 struct acx_wep_statistics wep;
738 struct acx_pwr_statistics pwr;
739 struct acx_aes_statistics aes;
740 struct acx_mic_statistics mic;
741 struct acx_event_statistics event;
742 struct acx_ps_statistics ps;
743 struct acx_rxpipe_statistics rxpipe;
744} __packed;
745
746struct acx_rate_class {
747 __le32 enabled_rates;
748 u8 short_retry_limit;
749 u8 long_retry_limit;
750 u8 aflags;
751 u8 reserved;
752};
753
754#define ACX_TX_BASIC_RATE 0
755#define ACX_TX_AP_FULL_RATE 1
756#define ACX_TX_RATE_POLICY_CNT 2
757struct acx_sta_rate_policy {
758 struct acx_header header;
759
760 __le32 rate_class_cnt;
761 struct acx_rate_class rate_class[CONF_TX_MAX_RATE_CLASSES];
762} __packed;
763
764
765#define ACX_TX_AP_MODE_MGMT_RATE 4
766#define ACX_TX_AP_MODE_BCST_RATE 5
767struct acx_ap_rate_policy {
768 struct acx_header header;
769
770 __le32 rate_policy_idx;
771 struct acx_rate_class rate_policy;
772} __packed;
773
774struct acx_ac_cfg {
775 struct acx_header header;
776 u8 ac;
777 u8 cw_min;
778 __le16 cw_max;
779 u8 aifsn;
780 u8 reserved;
781 __le16 tx_op_limit;
782} __packed;
783
784struct acx_tid_config {
785 struct acx_header header;
786 u8 queue_id;
787 u8 channel_type;
788 u8 tsid;
789 u8 ps_scheme;
790 u8 ack_policy;
791 u8 padding[3];
792 __le32 apsd_conf[2];
793} __packed;
794
795struct acx_frag_threshold {
796 struct acx_header header;
797 __le16 frag_threshold;
798 u8 padding[2];
799} __packed;
800
801struct acx_tx_config_options {
802 struct acx_header header;
803 __le16 tx_compl_timeout; /* msec */
804 __le16 tx_compl_threshold; /* number of packets */
805} __packed;
806
807#define ACX_TX_DESCRIPTORS 32
808
809struct wl1271_acx_ap_config_memory {
810 struct acx_header header;
811
812 u8 rx_mem_block_num;
813 u8 tx_min_mem_block_num;
814 u8 num_stations;
815 u8 num_ssid_profiles;
816 __le32 total_tx_descriptors;
817} __packed;
818
819struct wl1271_acx_sta_config_memory {
820 struct acx_header header;
821
822 u8 rx_mem_block_num;
823 u8 tx_min_mem_block_num;
824 u8 num_stations;
825 u8 num_ssid_profiles;
826 __le32 total_tx_descriptors;
827 u8 dyn_mem_enable;
828 u8 tx_free_req;
829 u8 rx_free_req;
830 u8 tx_min;
831 u8 fwlog_blocks;
832 u8 padding[3];
833} __packed;
834
835struct wl1271_acx_mem_map {
836 struct acx_header header;
837
838 __le32 code_start;
839 __le32 code_end;
840
841 __le32 wep_defkey_start;
842 __le32 wep_defkey_end;
843
844 __le32 sta_table_start;
845 __le32 sta_table_end;
846
847 __le32 packet_template_start;
848 __le32 packet_template_end;
849
850 /* Address of the TX result interface (control block) */
851 __le32 tx_result;
852 __le32 tx_result_queue_start;
853
854 __le32 queue_memory_start;
855 __le32 queue_memory_end;
856
857 __le32 packet_memory_pool_start;
858 __le32 packet_memory_pool_end;
859
860 __le32 debug_buffer1_start;
861 __le32 debug_buffer1_end;
862
863 __le32 debug_buffer2_start;
864 __le32 debug_buffer2_end;
865
866 /* Number of blocks FW allocated for TX packets */
867 __le32 num_tx_mem_blocks;
868
869 /* Number of blocks FW allocated for RX packets */
870 __le32 num_rx_mem_blocks;
871
872 /* the following 4 fields are valid in SLAVE mode only */
873 u8 *tx_cbuf;
874 u8 *rx_cbuf;
875 __le32 rx_ctrl;
876 __le32 tx_ctrl;
877} __packed;
878
879struct wl1271_acx_rx_config_opt {
880 struct acx_header header;
881
882 __le16 mblk_threshold;
883 __le16 threshold;
884 __le16 timeout;
885 u8 queue_type;
886 u8 reserved;
887} __packed;
888
889
890struct wl1271_acx_bet_enable {
891 struct acx_header header;
892
893 u8 enable;
894 u8 max_consecutive;
895 u8 padding[2];
896} __packed;
897
898#define ACX_IPV4_VERSION 4
899#define ACX_IPV6_VERSION 6
900#define ACX_IPV4_ADDR_SIZE 4
901
902/* bitmap of enabled arp_filter features */
903#define ACX_ARP_FILTER_ARP_FILTERING BIT(0)
904#define ACX_ARP_FILTER_AUTO_ARP BIT(1)
905
906struct wl1271_acx_arp_filter {
907 struct acx_header header;
908 u8 version; /* ACX_IPV4_VERSION, ACX_IPV6_VERSION */
909 u8 enable; /* bitmap of enabled ARP filtering features */
910 u8 padding[2];
911 u8 address[16]; /* The configured device IP address - all ARP
912 requests directed to this IP address will pass
913 through. For IPv4, the first four bytes are
914 used. */
915} __packed;
916
917struct wl1271_acx_pm_config {
918 struct acx_header header;
919
920 __le32 host_clk_settling_time;
921 u8 host_fast_wakeup_support;
922 u8 padding[3];
923} __packed;
924
925struct wl1271_acx_keep_alive_mode {
926 struct acx_header header;
927
928 u8 enabled;
929 u8 padding[3];
930} __packed;
931
932enum {
933 ACX_KEEP_ALIVE_NO_TX = 0,
934 ACX_KEEP_ALIVE_PERIOD_ONLY
935};
936
937enum {
938 ACX_KEEP_ALIVE_TPL_INVALID = 0,
939 ACX_KEEP_ALIVE_TPL_VALID
940};
941
942struct wl1271_acx_keep_alive_config {
943 struct acx_header header;
944
945 __le32 period;
946 u8 index;
947 u8 tpl_validation;
948 u8 trigger;
949 u8 padding;
950} __packed;
951
952#define HOST_IF_CFG_RX_FIFO_ENABLE BIT(0)
953#define HOST_IF_CFG_TX_EXTRA_BLKS_SWAP BIT(1)
954#define HOST_IF_CFG_TX_PAD_TO_SDIO_BLK BIT(3)
955
956struct wl1271_acx_host_config_bitmap {
957 struct acx_header header;
958
959 __le32 host_cfg_bitmap;
960} __packed;
961
962enum {
963 WL1271_ACX_TRIG_TYPE_LEVEL = 0,
964 WL1271_ACX_TRIG_TYPE_EDGE,
965};
966
967enum {
968 WL1271_ACX_TRIG_DIR_LOW = 0,
969 WL1271_ACX_TRIG_DIR_HIGH,
970 WL1271_ACX_TRIG_DIR_BIDIR,
971};
972
973enum {
974 WL1271_ACX_TRIG_ENABLE = 1,
975 WL1271_ACX_TRIG_DISABLE,
976};
977
978enum {
979 WL1271_ACX_TRIG_METRIC_RSSI_BEACON = 0,
980 WL1271_ACX_TRIG_METRIC_RSSI_DATA,
981 WL1271_ACX_TRIG_METRIC_SNR_BEACON,
982 WL1271_ACX_TRIG_METRIC_SNR_DATA,
983};
984
985enum {
986 WL1271_ACX_TRIG_IDX_RSSI = 0,
987 WL1271_ACX_TRIG_COUNT = 8,
988};
989
990struct wl1271_acx_rssi_snr_trigger {
991 struct acx_header header;
992
993 __le16 threshold;
994 __le16 pacing; /* 0 - 60000 ms */
995 u8 metric;
996 u8 type;
997 u8 dir;
998 u8 hysteresis;
999 u8 index;
1000 u8 enable;
1001 u8 padding[2];
1002};
1003
1004struct wl1271_acx_rssi_snr_avg_weights {
1005 struct acx_header header;
1006
1007 u8 rssi_beacon;
1008 u8 rssi_data;
1009 u8 snr_beacon;
1010 u8 snr_data;
1011};
1012
1013/*
1014 * ACX_PEER_HT_CAP
1015 * Configure HT capabilities - declare the capabilities of the peer
1016 * we are connected to.
1017 */
1018struct wl1271_acx_ht_capabilities {
1019 struct acx_header header;
1020
1021 /*
1022 * bit 0 - Allow HT Operation
1023 * bit 1 - Allow Greenfield format in TX
1024 * bit 2 - Allow Short GI in TX
1025 * bit 3 - Allow L-SIG TXOP Protection in TX
1026 * bit 4 - Allow HT Control fields in TX.
1027 * Note, driver will still leave space for HT control in packets
1028 * regardless of the value of this field. FW will be responsible
1029 * to drop the HT field from any frame when this Bit set to 0.
1030 * bit 5 - Allow RD initiation in TXOP. FW is allowed to initate RD.
1031 * Exact policy setting for this feature is TBD.
1032 * Note, this bit can only be set to 1 if bit 3 is set to 1.
1033 */
1034 __le32 ht_capabilites;
1035
1036 /*
1037 * Indicates to which peer these capabilities apply.
1038 * For infrastructure use ff:ff:ff:ff:ff:ff that indicates relevance
1039 * for all peers.
1040 * Only valid for IBSS/DLS operation.
1041 */
1042 u8 mac_address[ETH_ALEN];
1043
1044 /*
1045 * This the maximum A-MPDU length supported by the AP. The FW may not
1046 * exceed this length when sending A-MPDUs
1047 */
1048 u8 ampdu_max_length;
1049
1050 /* This is the minimal spacing required when sending A-MPDUs to the AP*/
1051 u8 ampdu_min_spacing;
1052} __packed;
1053
1054/* HT Capabilites Fw Bit Mask Mapping */
1055#define WL1271_ACX_FW_CAP_HT_OPERATION BIT(0)
1056#define WL1271_ACX_FW_CAP_GREENFIELD_FRAME_FORMAT BIT(1)
1057#define WL1271_ACX_FW_CAP_SHORT_GI_FOR_20MHZ_PACKETS BIT(2)
1058#define WL1271_ACX_FW_CAP_LSIG_TXOP_PROTECTION BIT(3)
1059#define WL1271_ACX_FW_CAP_HT_CONTROL_FIELDS BIT(4)
1060#define WL1271_ACX_FW_CAP_RD_INITIATION BIT(5)
1061
1062
1063/*
1064 * ACX_HT_BSS_OPERATION
1065 * Configure HT capabilities - AP rules for behavior in the BSS.
1066 */
1067struct wl1271_acx_ht_information {
1068 struct acx_header header;
1069
1070 /* Values: 0 - RIFS not allowed, 1 - RIFS allowed */
1071 u8 rifs_mode;
1072
1073 /* Values: 0 - 3 like in spec */
1074 u8 ht_protection;
1075
1076 /* Values: 0 - GF protection not required, 1 - GF protection required */
1077 u8 gf_protection;
1078
1079 /*Values: 0 - TX Burst limit not required, 1 - TX Burst Limit required*/
1080 u8 ht_tx_burst_limit;
1081
1082 /*
1083 * Values: 0 - Dual CTS protection not required,
1084 * 1 - Dual CTS Protection required
1085 * Note: When this value is set to 1 FW will protect all TXOP with RTS
1086 * frame and will not use CTS-to-self regardless of the value of the
1087 * ACX_CTS_PROTECTION information element
1088 */
1089 u8 dual_cts_protection;
1090
1091 u8 padding[3];
1092} __packed;
1093
1094#define RX_BA_WIN_SIZE 8
1095
1096struct wl1271_acx_ba_session_policy {
1097 struct acx_header header;
1098 /*
1099 * Specifies role Id, Range 0-7, 0xFF means ANY role.
1100 * Future use. For now this field is irrelevant
1101 */
1102 u8 role_id;
1103 /*
1104 * Specifies Link Id, Range 0-31, 0xFF means ANY Link Id.
1105 * Not applicable if Role Id is set to ANY.
1106 */
1107 u8 link_id;
1108
1109 u8 tid;
1110
1111 u8 enable;
1112
1113 /* Windows size in number of packets */
1114 u16 win_size;
1115
1116 /*
1117 * As initiator inactivity timeout in time units(TU) of 1024us.
1118 * As receiver reserved
1119 */
1120 u16 inactivity_timeout;
1121
1122 /* Initiator = 1/Receiver = 0 */
1123 u8 ba_direction;
1124
1125 u8 padding[3];
1126} __packed;
1127
1128struct wl1271_acx_ba_receiver_setup {
1129 struct acx_header header;
1130
1131 /* Specifies Link Id, Range 0-31, 0xFF means ANY Link Id */
1132 u8 link_id;
1133
1134 u8 tid;
1135
1136 u8 enable;
1137
1138 u8 padding[1];
1139
1140 /* Windows size in number of packets */
1141 u16 win_size;
1142
1143 /* BA session starting sequence number. RANGE 0-FFF */
1144 u16 ssn;
1145} __packed;
1146
1147struct wl1271_acx_fw_tsf_information {
1148 struct acx_header header;
1149
1150 __le32 current_tsf_high;
1151 __le32 current_tsf_low;
1152 __le32 last_bttt_high;
1153 __le32 last_tbtt_low;
1154 u8 last_dtim_count;
1155 u8 padding[3];
1156} __packed;
1157
1158struct wl1271_acx_ps_rx_streaming {
1159 struct acx_header header;
1160
1161 u8 tid;
1162 u8 enable;
1163
1164 /* interval between triggers (10-100 msec) */
1165 u8 period;
1166
1167 /* timeout before first trigger (0-200 msec) */
1168 u8 timeout;
1169} __packed;
1170
1171struct wl1271_acx_ap_max_tx_retry {
1172 struct acx_header header;
1173
1174 /*
1175 * the number of frames transmission failures before
1176 * issuing the aging event.
1177 */
1178 __le16 max_tx_retry;
1179 u8 padding_1[2];
1180} __packed;
1181
1182struct wl1271_acx_config_ps {
1183 struct acx_header header;
1184
1185 u8 exit_retries;
1186 u8 enter_retries;
1187 u8 padding[2];
1188 __le32 null_data_rate;
1189} __packed;
1190
1191struct wl1271_acx_inconnection_sta {
1192 struct acx_header header;
1193
1194 u8 addr[ETH_ALEN];
1195 u8 padding1[2];
1196} __packed;
1197
1198struct acx_ap_beacon_filter {
1199 struct acx_header header;
1200
1201 u8 enable;
1202 u8 pad[3];
1203} __packed;
1204
1205/*
1206 * ACX_FM_COEX_CFG
1207 * set the FM co-existence parameters.
1208 */
1209struct wl1271_acx_fm_coex {
1210 struct acx_header header;
1211 /* enable(1) / disable(0) the FM Coex feature */
1212 u8 enable;
1213 /*
1214 * Swallow period used in COEX PLL swallowing mechanism.
1215 * 0xFF = use FW default
1216 */
1217 u8 swallow_period;
1218 /*
1219 * The N divider used in COEX PLL swallowing mechanism for Fref of
1220 * 38.4/19.2 Mhz. 0xFF = use FW default
1221 */
1222 u8 n_divider_fref_set_1;
1223 /*
1224 * The N divider used in COEX PLL swallowing mechanism for Fref of
1225 * 26/52 Mhz. 0xFF = use FW default
1226 */
1227 u8 n_divider_fref_set_2;
1228 /*
1229 * The M divider used in COEX PLL swallowing mechanism for Fref of
1230 * 38.4/19.2 Mhz. 0xFFFF = use FW default
1231 */
1232 __le16 m_divider_fref_set_1;
1233 /*
1234 * The M divider used in COEX PLL swallowing mechanism for Fref of
1235 * 26/52 Mhz. 0xFFFF = use FW default
1236 */
1237 __le16 m_divider_fref_set_2;
1238 /*
1239 * The time duration in uSec required for COEX PLL to stabilize.
1240 * 0xFFFFFFFF = use FW default
1241 */
1242 __le32 coex_pll_stabilization_time;
1243 /*
1244 * The time duration in uSec required for LDO to stabilize.
1245 * 0xFFFFFFFF = use FW default
1246 */
1247 __le16 ldo_stabilization_time;
1248 /*
1249 * The disturbed frequency band margin around the disturbed frequency
1250 * center (single sided).
1251 * For example, if 2 is configured, the following channels will be
1252 * considered disturbed channel:
1253 * 80 +- 0.1 MHz, 91 +- 0.1 MHz, 98 +- 0.1 MHz, 102 +- 0.1 MH
1254 * 0xFF = use FW default
1255 */
1256 u8 fm_disturbed_band_margin;
1257 /*
1258 * The swallow clock difference of the swallowing mechanism.
1259 * 0xFF = use FW default
1260 */
1261 u8 swallow_clk_diff;
1262} __packed;
1263
1264enum {
1265 ACX_WAKE_UP_CONDITIONS = 0x0002,
1266 ACX_MEM_CFG = 0x0003,
1267 ACX_SLOT = 0x0004,
1268 ACX_AC_CFG = 0x0007,
1269 ACX_MEM_MAP = 0x0008,
1270 ACX_AID = 0x000A,
1271 /* ACX_FW_REV is missing in the ref driver, but seems to work */
1272 ACX_FW_REV = 0x000D,
1273 ACX_MEDIUM_USAGE = 0x000F,
1274 ACX_RX_CFG = 0x0010,
1275 ACX_TX_QUEUE_CFG = 0x0011, /* FIXME: only used by wl1251 */
1276 ACX_STATISTICS = 0x0013, /* Debug API */
1277 ACX_PWR_CONSUMPTION_STATISTICS = 0x0014,
1278 ACX_FEATURE_CFG = 0x0015,
1279 ACX_TID_CFG = 0x001A,
1280 ACX_PS_RX_STREAMING = 0x001B,
1281 ACX_BEACON_FILTER_OPT = 0x001F,
1282 ACX_AP_BEACON_FILTER_OPT = 0x0020,
1283 ACX_NOISE_HIST = 0x0021,
1284 ACX_HDK_VERSION = 0x0022, /* ??? */
1285 ACX_PD_THRESHOLD = 0x0023,
1286 ACX_TX_CONFIG_OPT = 0x0024,
1287 ACX_CCA_THRESHOLD = 0x0025,
1288 ACX_EVENT_MBOX_MASK = 0x0026,
1289 ACX_CONN_MONIT_PARAMS = 0x002D,
1290 ACX_CONS_TX_FAILURE = 0x002F,
1291 ACX_BCN_DTIM_OPTIONS = 0x0031,
1292 ACX_SG_ENABLE = 0x0032,
1293 ACX_SG_CFG = 0x0033,
1294 ACX_FM_COEX_CFG = 0x0034,
1295 ACX_BEACON_FILTER_TABLE = 0x0038,
1296 ACX_ARP_IP_FILTER = 0x0039,
1297 ACX_ROAMING_STATISTICS_TBL = 0x003B,
1298 ACX_RATE_POLICY = 0x003D,
1299 ACX_CTS_PROTECTION = 0x003E,
1300 ACX_SLEEP_AUTH = 0x003F,
1301 ACX_PREAMBLE_TYPE = 0x0040,
1302 ACX_ERROR_CNT = 0x0041,
1303 ACX_IBSS_FILTER = 0x0044,
1304 ACX_SERVICE_PERIOD_TIMEOUT = 0x0045,
1305 ACX_TSF_INFO = 0x0046,
1306 ACX_CONFIG_PS_WMM = 0x0049,
1307 ACX_ENABLE_RX_DATA_FILTER = 0x004A,
1308 ACX_SET_RX_DATA_FILTER = 0x004B,
1309 ACX_GET_DATA_FILTER_STATISTICS = 0x004C,
1310 ACX_RX_CONFIG_OPT = 0x004E,
1311 ACX_FRAG_CFG = 0x004F,
1312 ACX_BET_ENABLE = 0x0050,
1313 ACX_RSSI_SNR_TRIGGER = 0x0051,
1314 ACX_RSSI_SNR_WEIGHTS = 0x0052,
1315 ACX_KEEP_ALIVE_MODE = 0x0053,
1316 ACX_SET_KEEP_ALIVE_CONFIG = 0x0054,
1317 ACX_BA_SESSION_POLICY_CFG = 0x0055,
1318 ACX_BA_SESSION_RX_SETUP = 0x0056,
1319 ACX_PEER_HT_CAP = 0x0057,
1320 ACX_HT_BSS_OPERATION = 0x0058,
1321 ACX_COEX_ACTIVITY = 0x0059,
1322 ACX_SET_DCO_ITRIM_PARAMS = 0x0061,
1323 ACX_GEN_FW_CMD = 0x0070,
1324 ACX_HOST_IF_CFG_BITMAP = 0x0071,
1325 ACX_MAX_TX_FAILURE = 0x0072,
1326 ACX_UPDATE_INCONNECTION_STA_LIST = 0x0073,
1327 DOT11_RX_MSDU_LIFE_TIME = 0x1004,
1328 DOT11_CUR_TX_PWR = 0x100D,
1329 DOT11_RX_DOT11_MODE = 0x1012,
1330 DOT11_RTS_THRESHOLD = 0x1013,
1331 DOT11_GROUP_ADDRESS_TBL = 0x1014,
1332 ACX_PM_CONFIG = 0x1016,
1333 ACX_CONFIG_PS = 0x1017,
1334 ACX_CONFIG_HANGOVER = 0x1018,
1335};
1336
1337
1338int wl1271_acx_wake_up_conditions(struct wl1271 *wl);
1339int wl1271_acx_sleep_auth(struct wl1271 *wl, u8 sleep_auth);
1340int wl1271_acx_tx_power(struct wl1271 *wl, int power);
1341int wl1271_acx_feature_cfg(struct wl1271 *wl);
1342int wl1271_acx_mem_map(struct wl1271 *wl,
1343 struct acx_header *mem_map, size_t len);
1344int wl1271_acx_rx_msdu_life_time(struct wl1271 *wl);
1345int wl1271_acx_rx_config(struct wl1271 *wl, u32 config, u32 filter);
1346int wl1271_acx_pd_threshold(struct wl1271 *wl);
1347int wl1271_acx_slot(struct wl1271 *wl, enum acx_slot_type slot_time);
1348int wl1271_acx_group_address_tbl(struct wl1271 *wl, bool enable,
1349 void *mc_list, u32 mc_list_len);
1350int wl1271_acx_service_period_timeout(struct wl1271 *wl);
1351int wl1271_acx_rts_threshold(struct wl1271 *wl, u32 rts_threshold);
1352int wl1271_acx_dco_itrim_params(struct wl1271 *wl);
1353int wl1271_acx_beacon_filter_opt(struct wl1271 *wl, bool enable_filter);
1354int wl1271_acx_beacon_filter_table(struct wl1271 *wl);
1355int wl1271_acx_conn_monit_params(struct wl1271 *wl, bool enable);
1356int wl1271_acx_sg_enable(struct wl1271 *wl, bool enable);
1357int wl1271_acx_sta_sg_cfg(struct wl1271 *wl);
1358int wl1271_acx_ap_sg_cfg(struct wl1271 *wl);
1359int wl1271_acx_cca_threshold(struct wl1271 *wl);
1360int wl1271_acx_bcn_dtim_options(struct wl1271 *wl);
1361int wl1271_acx_aid(struct wl1271 *wl, u16 aid);
1362int wl1271_acx_event_mbox_mask(struct wl1271 *wl, u32 event_mask);
1363int wl1271_acx_set_preamble(struct wl1271 *wl, enum acx_preamble_type preamble);
1364int wl1271_acx_cts_protect(struct wl1271 *wl,
1365 enum acx_ctsprotect_type ctsprotect);
1366int wl1271_acx_statistics(struct wl1271 *wl, struct acx_statistics *stats);
1367int wl1271_acx_sta_rate_policies(struct wl1271 *wl);
1368int wl1271_acx_ap_rate_policy(struct wl1271 *wl, struct conf_tx_rate_class *c,
1369 u8 idx);
1370int wl1271_acx_ac_cfg(struct wl1271 *wl, u8 ac, u8 cw_min, u16 cw_max,
1371 u8 aifsn, u16 txop);
1372int wl1271_acx_tid_cfg(struct wl1271 *wl, u8 queue_id, u8 channel_type,
1373 u8 tsid, u8 ps_scheme, u8 ack_policy,
1374 u32 apsd_conf0, u32 apsd_conf1);
1375int wl1271_acx_frag_threshold(struct wl1271 *wl, u32 frag_threshold);
1376int wl1271_acx_tx_config_options(struct wl1271 *wl);
1377int wl1271_acx_ap_mem_cfg(struct wl1271 *wl);
1378int wl1271_acx_sta_mem_cfg(struct wl1271 *wl);
1379int wl1271_acx_init_mem_config(struct wl1271 *wl);
1380int wl1271_acx_host_if_cfg_bitmap(struct wl1271 *wl, u32 host_cfg_bitmap);
1381int wl1271_acx_init_rx_interrupt(struct wl1271 *wl);
1382int wl1271_acx_smart_reflex(struct wl1271 *wl);
1383int wl1271_acx_bet_enable(struct wl1271 *wl, bool enable);
1384int wl1271_acx_arp_ip_filter(struct wl1271 *wl, u8 enable, __be32 address);
1385int wl1271_acx_pm_config(struct wl1271 *wl);
1386int wl1271_acx_keep_alive_mode(struct wl1271 *wl, bool enable);
1387int wl1271_acx_keep_alive_config(struct wl1271 *wl, u8 index, u8 tpl_valid);
1388int wl1271_acx_rssi_snr_trigger(struct wl1271 *wl, bool enable,
1389 s16 thold, u8 hyst);
1390int wl1271_acx_rssi_snr_avg_weights(struct wl1271 *wl);
1391int wl1271_acx_set_ht_capabilities(struct wl1271 *wl,
1392 struct ieee80211_sta_ht_cap *ht_cap,
1393 bool allow_ht_operation);
1394int wl1271_acx_set_ht_information(struct wl1271 *wl,
1395 u16 ht_operation_mode);
1396int wl1271_acx_set_ba_session(struct wl1271 *wl,
1397 enum ieee80211_back_parties direction,
1398 u8 tid_index, u8 policy);
1399int wl1271_acx_set_ba_receiver_session(struct wl1271 *wl, u8 tid_index, u16 ssn,
1400 bool enable);
1401int wl1271_acx_tsf_info(struct wl1271 *wl, u64 *mactime);
1402int wl1271_acx_ps_rx_streaming(struct wl1271 *wl, bool enable);
1403int wl1271_acx_ap_max_tx_retry(struct wl1271 *wl);
1404int wl1271_acx_config_ps(struct wl1271 *wl);
1405int wl1271_acx_set_inconnection_sta(struct wl1271 *wl, u8 *addr);
1406int wl1271_acx_set_ap_beacon_filter(struct wl1271 *wl, bool enable);
1407int wl1271_acx_fm_coex(struct wl1271 *wl);
1408
1409#endif /* __WL1271_ACX_H__ */