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1/******************************************************************************
2 *
3 * Copyright(c) 2009-2010 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
22 * wlanfae <wlanfae@realtek.com>
23 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
24 * Hsinchu 300, Taiwan.
25 *
26 * Larry Finger <Larry.Finger@lwfinger.net>
27 *
28 *****************************************************************************/
29
30#ifndef __RTL92D_REG_H__
31#define __RTL92D_REG_H__
32
33/* ----------------------------------------------------- */
34/* 0x0000h ~ 0x00FFh System Configuration */
35/* ----------------------------------------------------- */
36#define REG_SYS_ISO_CTRL 0x0000
37#define REG_SYS_FUNC_EN 0x0002
38#define REG_APS_FSMCO 0x0004
39#define REG_SYS_CLKR 0x0008
40#define REG_9346CR 0x000A
41#define REG_EE_VPD 0x000C
42#define REG_AFE_MISC 0x0010
43#define REG_SPS0_CTRL 0x0011
44#define REG_POWER_OFF_IN_PROCESS 0x0017
45#define REG_SPS_OCP_CFG 0x0018
46#define REG_RSV_CTRL 0x001C
47#define REG_RF_CTRL 0x001F
48#define REG_LDOA15_CTRL 0x0020
49#define REG_LDOV12D_CTRL 0x0021
50#define REG_LDOHCI12_CTRL 0x0022
51#define REG_LPLDO_CTRL 0x0023
52#define REG_AFE_XTAL_CTRL 0x0024
53#define REG_AFE_PLL_CTRL 0x0028
54/* for 92d, DMDP,SMSP,DMSP contrl */
55#define REG_MAC_PHY_CTRL 0x002c
56#define REG_EFUSE_CTRL 0x0030
57#define REG_EFUSE_TEST 0x0034
58#define REG_PWR_DATA 0x0038
59#define REG_CAL_TIMER 0x003C
60#define REG_ACLK_MON 0x003E
61#define REG_GPIO_MUXCFG 0x0040
62#define REG_GPIO_IO_SEL 0x0042
63#define REG_MAC_PINMUX_CFG 0x0043
64#define REG_GPIO_PIN_CTRL 0x0044
65#define REG_GPIO_INTM 0x0048
66#define REG_LEDCFG0 0x004C
67#define REG_LEDCFG1 0x004D
68#define REG_LEDCFG2 0x004E
69#define REG_LEDCFG3 0x004F
70#define REG_FSIMR 0x0050
71#define REG_FSISR 0x0054
72
73#define REG_MCUFWDL 0x0080
74
75#define REG_HMEBOX_EXT_0 0x0088
76#define REG_HMEBOX_EXT_1 0x008A
77#define REG_HMEBOX_EXT_2 0x008C
78#define REG_HMEBOX_EXT_3 0x008E
79
80#define REG_BIST_SCAN 0x00D0
81#define REG_BIST_RPT 0x00D4
82#define REG_BIST_ROM_RPT 0x00D8
83#define REG_USB_SIE_INTF 0x00E0
84#define REG_PCIE_MIO_INTF 0x00E4
85#define REG_PCIE_MIO_INTD 0x00E8
86#define REG_HPON_FSM 0x00EC
87#define REG_SYS_CFG 0x00F0
88#define REG_MAC_PHY_CTRL_NORMAL 0x00f8
89
90#define REG_MAC0 0x0081
91#define REG_MAC1 0x0053
92#define FW_MAC0_READY 0x18
93#define FW_MAC1_READY 0x1A
94#define MAC0_ON BIT(7)
95#define MAC1_ON BIT(0)
96#define MAC0_READY BIT(0)
97#define MAC1_READY BIT(0)
98
99/* ----------------------------------------------------- */
100/* 0x0100h ~ 0x01FFh MACTOP General Configuration */
101/* ----------------------------------------------------- */
102#define REG_CR 0x0100
103#define REG_PBP 0x0104
104#define REG_TRXDMA_CTRL 0x010C
105#define REG_TRXFF_BNDY 0x0114
106#define REG_TRXFF_STATUS 0x0118
107#define REG_RXFF_PTR 0x011C
108#define REG_HIMR 0x0120
109#define REG_HISR 0x0124
110#define REG_HIMRE 0x0128
111#define REG_HISRE 0x012C
112#define REG_CPWM 0x012F
113#define REG_FWIMR 0x0130
114#define REG_FWISR 0x0134
115#define REG_PKTBUF_DBG_CTRL 0x0140
116#define REG_PKTBUF_DBG_DATA_L 0x0144
117#define REG_PKTBUF_DBG_DATA_H 0x0148
118
119#define REG_TC0_CTRL 0x0150
120#define REG_TC1_CTRL 0x0154
121#define REG_TC2_CTRL 0x0158
122#define REG_TC3_CTRL 0x015C
123#define REG_TC4_CTRL 0x0160
124#define REG_TCUNIT_BASE 0x0164
125#define REG_MBIST_START 0x0174
126#define REG_MBIST_DONE 0x0178
127#define REG_MBIST_FAIL 0x017C
128#define REG_C2HEVT_MSG_NORMAL 0x01A0
129#define REG_C2HEVT_MSG_TEST 0x01B8
130#define REG_C2HEVT_CLEAR 0x01BF
131#define REG_MCUTST_1 0x01c0
132#define REG_FMETHR 0x01C8
133#define REG_HMETFR 0x01CC
134#define REG_HMEBOX_0 0x01D0
135#define REG_HMEBOX_1 0x01D4
136#define REG_HMEBOX_2 0x01D8
137#define REG_HMEBOX_3 0x01DC
138
139#define REG_LLT_INIT 0x01E0
140#define REG_BB_ACCEESS_CTRL 0x01E8
141#define REG_BB_ACCESS_DATA 0x01EC
142
143
144/* ----------------------------------------------------- */
145/* 0x0200h ~ 0x027Fh TXDMA Configuration */
146/* ----------------------------------------------------- */
147#define REG_RQPN 0x0200
148#define REG_FIFOPAGE 0x0204
149#define REG_TDECTRL 0x0208
150#define REG_TXDMA_OFFSET_CHK 0x020C
151#define REG_TXDMA_STATUS 0x0210
152#define REG_RQPN_NPQ 0x0214
153
154/* ----------------------------------------------------- */
155/* 0x0280h ~ 0x02FFh RXDMA Configuration */
156/* ----------------------------------------------------- */
157#define REG_RXDMA_AGG_PG_TH 0x0280
158#define REG_RXPKT_NUM 0x0284
159#define REG_RXDMA_STATUS 0x0288
160
161/* ----------------------------------------------------- */
162/* 0x0300h ~ 0x03FFh PCIe */
163/* ----------------------------------------------------- */
164#define REG_PCIE_CTRL_REG 0x0300
165#define REG_INT_MIG 0x0304
166#define REG_BCNQ_DESA 0x0308
167#define REG_HQ_DESA 0x0310
168#define REG_MGQ_DESA 0x0318
169#define REG_VOQ_DESA 0x0320
170#define REG_VIQ_DESA 0x0328
171#define REG_BEQ_DESA 0x0330
172#define REG_BKQ_DESA 0x0338
173#define REG_RX_DESA 0x0340
174#define REG_DBI 0x0348
175#define REG_DBI_WDATA 0x0348
176#define REG_DBI_RDATA 0x034C
177#define REG_DBI_CTRL 0x0350
178#define REG_DBI_FLAG 0x0352
179#define REG_MDIO 0x0354
180#define REG_DBG_SEL 0x0360
181#define REG_PCIE_HRPWM 0x0361
182#define REG_PCIE_HCPWM 0x0363
183#define REG_UART_CTRL 0x0364
184#define REG_UART_TX_DESA 0x0370
185#define REG_UART_RX_DESA 0x0378
186
187/* ----------------------------------------------------- */
188/* 0x0400h ~ 0x047Fh Protocol Configuration */
189/* ----------------------------------------------------- */
190#define REG_VOQ_INFORMATION 0x0400
191#define REG_VIQ_INFORMATION 0x0404
192#define REG_BEQ_INFORMATION 0x0408
193#define REG_BKQ_INFORMATION 0x040C
194#define REG_MGQ_INFORMATION 0x0410
195#define REG_HGQ_INFORMATION 0x0414
196#define REG_BCNQ_INFORMATION 0x0418
197
198
199#define REG_CPU_MGQ_INFORMATION 0x041C
200#define REG_FWHW_TXQ_CTRL 0x0420
201#define REG_HWSEQ_CTRL 0x0423
202#define REG_TXPKTBUF_BCNQ_BDNY 0x0424
203#define REG_TXPKTBUF_MGQ_BDNY 0x0425
204#define REG_MULTI_BCNQ_EN 0x0426
205#define REG_MULTI_BCNQ_OFFSET 0x0427
206#define REG_SPEC_SIFS 0x0428
207#define REG_RL 0x042A
208#define REG_DARFRC 0x0430
209#define REG_RARFRC 0x0438
210#define REG_RRSR 0x0440
211#define REG_ARFR0 0x0444
212#define REG_ARFR1 0x0448
213#define REG_ARFR2 0x044C
214#define REG_ARFR3 0x0450
215#define REG_AGGLEN_LMT 0x0458
216#define REG_AMPDU_MIN_SPACE 0x045C
217#define REG_TXPKTBUF_WMAC_LBK_BF_HD 0x045D
218#define REG_FAST_EDCA_CTRL 0x0460
219#define REG_RD_RESP_PKT_TH 0x0463
220#define REG_INIRTS_RATE_SEL 0x0480
221#define REG_INIDATA_RATE_SEL 0x0484
222#define REG_POWER_STATUS 0x04A4
223#define REG_POWER_STAGE1 0x04B4
224#define REG_POWER_STAGE2 0x04B8
225#define REG_PKT_LIFE_TIME 0x04C0
226#define REG_STBC_SETTING 0x04C4
227#define REG_PROT_MODE_CTRL 0x04C8
228#define REG_MAX_AGGR_NUM 0x04CA
229#define REG_RTS_MAX_AGGR_NUM 0x04CB
230#define REG_BAR_MODE_CTRL 0x04CC
231#define REG_RA_TRY_RATE_AGG_LMT 0x04CF
232#define REG_EARLY_MODE_CONTROL 0x4D0
233#define REG_NQOS_SEQ 0x04DC
234#define REG_QOS_SEQ 0x04DE
235#define REG_NEED_CPU_HANDLE 0x04E0
236#define REG_PKT_LOSE_RPT 0x04E1
237#define REG_PTCL_ERR_STATUS 0x04E2
238#define REG_DUMMY 0x04FC
239
240/* ----------------------------------------------------- */
241/* 0x0500h ~ 0x05FFh EDCA Configuration */
242/* ----------------------------------------------------- */
243#define REG_EDCA_VO_PARAM 0x0500
244#define REG_EDCA_VI_PARAM 0x0504
245#define REG_EDCA_BE_PARAM 0x0508
246#define REG_EDCA_BK_PARAM 0x050C
247#define REG_BCNTCFG 0x0510
248#define REG_PIFS 0x0512
249#define REG_RDG_PIFS 0x0513
250#define REG_SIFS_CTX 0x0514
251#define REG_SIFS_TRX 0x0516
252#define REG_AGGR_BREAK_TIME 0x051A
253#define REG_SLOT 0x051B
254#define REG_TX_PTCL_CTRL 0x0520
255#define REG_TXPAUSE 0x0522
256#define REG_DIS_TXREQ_CLR 0x0523
257#define REG_RD_CTRL 0x0524
258#define REG_TBTT_PROHIBIT 0x0540
259#define REG_RD_NAV_NXT 0x0544
260#define REG_NAV_PROT_LEN 0x0546
261#define REG_BCN_CTRL 0x0550
262#define REG_USTIME_TSF 0x0551
263#define REG_MBID_NUM 0x0552
264#define REG_DUAL_TSF_RST 0x0553
265#define REG_BCN_INTERVAL 0x0554
266#define REG_MBSSID_BCN_SPACE 0x0554
267#define REG_DRVERLYINT 0x0558
268#define REG_BCNDMATIM 0x0559
269#define REG_ATIMWND 0x055A
270#define REG_BCN_MAX_ERR 0x055D
271#define REG_RXTSF_OFFSET_CCK 0x055E
272#define REG_RXTSF_OFFSET_OFDM 0x055F
273#define REG_TSFTR 0x0560
274#define REG_INIT_TSFTR 0x0564
275#define REG_PSTIMER 0x0580
276#define REG_TIMER0 0x0584
277#define REG_TIMER1 0x0588
278#define REG_ACMHWCTRL 0x05C0
279#define REG_ACMRSTCTRL 0x05C1
280#define REG_ACMAVG 0x05C2
281#define REG_VO_ADMTIME 0x05C4
282#define REG_VI_ADMTIME 0x05C6
283#define REG_BE_ADMTIME 0x05C8
284#define REG_EDCA_RANDOM_GEN 0x05CC
285#define REG_SCH_TXCMD 0x05D0
286
287/* Dual MAC Co-Existence Register */
288#define REG_DMC 0x05F0
289
290/* ----------------------------------------------------- */
291/* 0x0600h ~ 0x07FFh WMAC Configuration */
292/* ----------------------------------------------------- */
293#define REG_APSD_CTRL 0x0600
294#define REG_BWOPMODE 0x0603
295#define REG_TCR 0x0604
296#define REG_RCR 0x0608
297#define REG_RX_PKT_LIMIT 0x060C
298#define REG_RX_DLK_TIME 0x060D
299#define REG_RX_DRVINFO_SZ 0x060F
300
301#define REG_MACID 0x0610
302#define REG_BSSID 0x0618
303#define REG_MAR 0x0620
304#define REG_MBIDCAMCFG 0x0628
305
306#define REG_USTIME_EDCA 0x0638
307#define REG_MAC_SPEC_SIFS 0x063A
308#define REG_RESP_SIFS_CCK 0x063C
309#define REG_RESP_SIFS_OFDM 0x063E
310#define REG_ACKTO 0x0640
311#define REG_CTS2TO 0x0641
312#define REG_EIFS 0x0642
313
314
315/* WMA, BA, CCX */
316#define REG_NAV_CTRL 0x0650
317#define REG_BACAMCMD 0x0654
318#define REG_BACAMCONTENT 0x0658
319#define REG_LBDLY 0x0660
320#define REG_FWDLY 0x0661
321#define REG_RXERR_RPT 0x0664
322#define REG_WMAC_TRXPTCL_CTL 0x0668
323
324
325/* Security */
326#define REG_CAMCMD 0x0670
327#define REG_CAMWRITE 0x0674
328#define REG_CAMREAD 0x0678
329#define REG_CAMDBG 0x067C
330#define REG_SECCFG 0x0680
331
332/* Power */
333#define REG_WOW_CTRL 0x0690
334#define REG_PSSTATUS 0x0691
335#define REG_PS_RX_INFO 0x0692
336#define REG_LPNAV_CTRL 0x0694
337#define REG_WKFMCAM_CMD 0x0698
338#define REG_WKFMCAM_RWD 0x069C
339#define REG_RXFLTMAP0 0x06A0
340#define REG_RXFLTMAP1 0x06A2
341#define REG_RXFLTMAP2 0x06A4
342#define REG_BCN_PSR_RPT 0x06A8
343#define REG_CALB32K_CTRL 0x06AC
344#define REG_PKT_MON_CTRL 0x06B4
345#define REG_BT_COEX_TABLE 0x06C0
346#define REG_WMAC_RESP_TXINFO 0x06D8
347
348
349/* ----------------------------------------------------- */
350/* Redifine 8192C register definition for compatibility */
351/* ----------------------------------------------------- */
352#define CR9346 REG_9346CR
353#define MSR (REG_CR + 2)
354#define ISR REG_HISR
355#define TSFR REG_TSFTR
356
357#define MACIDR0 REG_MACID
358#define MACIDR4 (REG_MACID + 4)
359
360#define PBP REG_PBP
361
362#define IDR0 MACIDR0
363#define IDR4 MACIDR4
364
365/* ----------------------------------------------------- */
366/* 8192C (MSR) Media Status Register(Offset 0x4C, 8 bits)*/
367/* ----------------------------------------------------- */
368#define MSR_NOLINK 0x00
369#define MSR_ADHOC 0x01
370#define MSR_INFRA 0x02
371#define MSR_AP 0x03
372
373/* 6. Adaptive Control Registers (Offset: 0x0160 - 0x01CF) */
374/* ----------------------------------------------------- */
375/* 8192C Response Rate Set Register(offset 0x181, 24bits)*/
376/* ----------------------------------------------------- */
377#define RRSR_RSC_OFFSET 21
378#define RRSR_SHORT_OFFSET 23
379#define RRSR_RSC_BW_40M 0x600000
380#define RRSR_RSC_UPSUBCHNL 0x400000
381#define RRSR_RSC_LOWSUBCHNL 0x200000
382#define RRSR_SHORT 0x800000
383#define RRSR_1M BIT0
384#define RRSR_2M BIT1
385#define RRSR_5_5M BIT2
386#define RRSR_11M BIT3
387#define RRSR_6M BIT4
388#define RRSR_9M BIT5
389#define RRSR_12M BIT6
390#define RRSR_18M BIT7
391#define RRSR_24M BIT8
392#define RRSR_36M BIT9
393#define RRSR_48M BIT10
394#define RRSR_54M BIT11
395#define RRSR_MCS0 BIT12
396#define RRSR_MCS1 BIT13
397#define RRSR_MCS2 BIT14
398#define RRSR_MCS3 BIT15
399#define RRSR_MCS4 BIT16
400#define RRSR_MCS5 BIT17
401#define RRSR_MCS6 BIT18
402#define RRSR_MCS7 BIT19
403#define BRSR_ACKSHORTPMB BIT23
404
405/* ----------------------------------------------------- */
406/* 8192C Rate Definition */
407/* ----------------------------------------------------- */
408/* CCK */
409#define RATR_1M 0x00000001
410#define RATR_2M 0x00000002
411#define RATR_55M 0x00000004
412#define RATR_11M 0x00000008
413/* OFDM */
414#define RATR_6M 0x00000010
415#define RATR_9M 0x00000020
416#define RATR_12M 0x00000040
417#define RATR_18M 0x00000080
418#define RATR_24M 0x00000100
419#define RATR_36M 0x00000200
420#define RATR_48M 0x00000400
421#define RATR_54M 0x00000800
422/* MCS 1 Spatial Stream */
423#define RATR_MCS0 0x00001000
424#define RATR_MCS1 0x00002000
425#define RATR_MCS2 0x00004000
426#define RATR_MCS3 0x00008000
427#define RATR_MCS4 0x00010000
428#define RATR_MCS5 0x00020000
429#define RATR_MCS6 0x00040000
430#define RATR_MCS7 0x00080000
431/* MCS 2 Spatial Stream */
432#define RATR_MCS8 0x00100000
433#define RATR_MCS9 0x00200000
434#define RATR_MCS10 0x00400000
435#define RATR_MCS11 0x00800000
436#define RATR_MCS12 0x01000000
437#define RATR_MCS13 0x02000000
438#define RATR_MCS14 0x04000000
439#define RATR_MCS15 0x08000000
440
441/* CCK */
442#define RATE_1M BIT(0)
443#define RATE_2M BIT(1)
444#define RATE_5_5M BIT(2)
445#define RATE_11M BIT(3)
446/* OFDM */
447#define RATE_6M BIT(4)
448#define RATE_9M BIT(5)
449#define RATE_12M BIT(6)
450#define RATE_18M BIT(7)
451#define RATE_24M BIT(8)
452#define RATE_36M BIT(9)
453#define RATE_48M BIT(10)
454#define RATE_54M BIT(11)
455/* MCS 1 Spatial Stream */
456#define RATE_MCS0 BIT(12)
457#define RATE_MCS1 BIT(13)
458#define RATE_MCS2 BIT(14)
459#define RATE_MCS3 BIT(15)
460#define RATE_MCS4 BIT(16)
461#define RATE_MCS5 BIT(17)
462#define RATE_MCS6 BIT(18)
463#define RATE_MCS7 BIT(19)
464/* MCS 2 Spatial Stream */
465#define RATE_MCS8 BIT(20)
466#define RATE_MCS9 BIT(21)
467#define RATE_MCS10 BIT(22)
468#define RATE_MCS11 BIT(23)
469#define RATE_MCS12 BIT(24)
470#define RATE_MCS13 BIT(25)
471#define RATE_MCS14 BIT(26)
472#define RATE_MCS15 BIT(27)
473
474/* ALL CCK Rate */
475#define RATE_ALL_CCK (RATR_1M | RATR_2M | RATR_55M | \
476 RATR_11M)
477#define RATE_ALL_OFDM_AG (RATR_6M | RATR_9M | RATR_12M | \
478 RATR_18M | RATR_24M | \
479 RATR_36M | RATR_48M | RATR_54M)
480#define RATE_ALL_OFDM_1SS (RATR_MCS0 | RATR_MCS1 | RATR_MCS2 | \
481 RATR_MCS3 | RATR_MCS4 | RATR_MCS5 | \
482 RATR_MCS6 | RATR_MCS7)
483#define RATE_ALL_OFDM_2SS (RATR_MCS8 | RATR_MCS9 | RATR_MCS10 | \
484 RATR_MCS11 | RATR_MCS12 | RATR_MCS13 | \
485 RATR_MCS14 | RATR_MCS15)
486
487/* ----------------------------------------------------- */
488/* 8192C BW_OPMODE bits (Offset 0x203, 8bit) */
489/* ----------------------------------------------------- */
490#define BW_OPMODE_20MHZ BIT(2)
491#define BW_OPMODE_5G BIT(1)
492#define BW_OPMODE_11J BIT(0)
493
494
495/* ----------------------------------------------------- */
496/* 8192C CAM Config Setting (offset 0x250, 1 byte) */
497/* ----------------------------------------------------- */
498#define CAM_VALID BIT(15)
499#define CAM_NOTVALID 0x0000
500#define CAM_USEDK BIT(5)
501
502#define CAM_NONE 0x0
503#define CAM_WEP40 0x01
504#define CAM_TKIP 0x02
505#define CAM_AES 0x04
506#define CAM_WEP104 0x05
507#define CAM_SMS4 0x6
508
509
510#define TOTAL_CAM_ENTRY 32
511#define HALF_CAM_ENTRY 16
512
513#define CAM_WRITE BIT(16)
514#define CAM_READ 0x00000000
515#define CAM_POLLINIG BIT(31)
516
517/* 10. Power Save Control Registers (Offset: 0x0260 - 0x02DF) */
518#define WOW_PMEN BIT0 /* Power management Enable. */
519#define WOW_WOMEN BIT1 /* WoW function on or off. */
520#define WOW_MAGIC BIT2 /* Magic packet */
521#define WOW_UWF BIT3 /* Unicast Wakeup frame. */
522
523/* 12. Host Interrupt Status Registers (Offset: 0x0300 - 0x030F) */
524/* ----------------------------------------------------- */
525/* 8190 IMR/ISR bits (offset 0xfd, 8bits) */
526/* ----------------------------------------------------- */
527#define IMR8190_DISABLED 0x0
528#define IMR_BCNDMAINT6 BIT(31)
529#define IMR_BCNDMAINT5 BIT(30)
530#define IMR_BCNDMAINT4 BIT(29)
531#define IMR_BCNDMAINT3 BIT(28)
532#define IMR_BCNDMAINT2 BIT(27)
533#define IMR_BCNDMAINT1 BIT(26)
534#define IMR_BCNDOK8 BIT(25)
535#define IMR_BCNDOK7 BIT(24)
536#define IMR_BCNDOK6 BIT(23)
537#define IMR_BCNDOK5 BIT(22)
538#define IMR_BCNDOK4 BIT(21)
539#define IMR_BCNDOK3 BIT(20)
540#define IMR_BCNDOK2 BIT(19)
541#define IMR_BCNDOK1 BIT(18)
542#define IMR_TIMEOUT2 BIT(17)
543#define IMR_TIMEOUT1 BIT(16)
544#define IMR_TXFOVW BIT(15)
545#define IMR_PSTIMEOUT BIT(14)
546#define IMR_BcnInt BIT(13)
547#define IMR_RXFOVW BIT(12)
548#define IMR_RDU BIT(11)
549#define IMR_ATIMEND BIT(10)
550#define IMR_BDOK BIT(9)
551#define IMR_HIGHDOK BIT(8)
552#define IMR_TBDOK BIT(7)
553#define IMR_MGNTDOK BIT(6)
554#define IMR_TBDER BIT(5)
555#define IMR_BKDOK BIT(4)
556#define IMR_BEDOK BIT(3)
557#define IMR_VIDOK BIT(2)
558#define IMR_VODOK BIT(1)
559#define IMR_ROK BIT(0)
560
561#define IMR_TXERR BIT(11)
562#define IMR_RXERR BIT(10)
563#define IMR_C2HCMD BIT(9)
564#define IMR_CPWM BIT(8)
565#define IMR_OCPINT BIT(1)
566#define IMR_WLANOFF BIT(0)
567
568/* ----------------------------------------------------- */
569/* 8192C EFUSE */
570/* ----------------------------------------------------- */
571#define HWSET_MAX_SIZE 256
572#define EFUSE_MAX_SECTION 32
573#define EFUSE_REAL_CONTENT_LEN 512
574
575/* ----------------------------------------------------- */
576/* 8192C EEPROM/EFUSE share register definition. */
577/* ----------------------------------------------------- */
578#define EEPROM_DEFAULT_TSSI 0x0
579#define EEPROM_DEFAULT_CRYSTALCAP 0x0
580#define EEPROM_DEFAULT_THERMALMETER 0x12
581
582#define EEPROM_DEFAULT_TXPOWERLEVEL_2G 0x2C
583#define EEPROM_DEFAULT_TXPOWERLEVEL_5G 0x22
584
585#define EEPROM_DEFAULT_HT40_2SDIFF 0x0
586/* HT20<->40 default Tx Power Index Difference */
587#define EEPROM_DEFAULT_HT20_DIFF 2
588/* OFDM Tx Power index diff */
589#define EEPROM_DEFAULT_LEGACYHTTXPOWERDIFF 0x4
590#define EEPROM_DEFAULT_HT40_PWRMAXOFFSET 0
591#define EEPROM_DEFAULT_HT20_PWRMAXOFFSET 0
592
593#define EEPROM_CHANNEL_PLAN_FCC 0x0
594#define EEPROM_CHANNEL_PLAN_IC 0x1
595#define EEPROM_CHANNEL_PLAN_ETSI 0x2
596#define EEPROM_CHANNEL_PLAN_SPAIN 0x3
597#define EEPROM_CHANNEL_PLAN_FRANCE 0x4
598#define EEPROM_CHANNEL_PLAN_MKK 0x5
599#define EEPROM_CHANNEL_PLAN_MKK1 0x6
600#define EEPROM_CHANNEL_PLAN_ISRAEL 0x7
601#define EEPROM_CHANNEL_PLAN_TELEC 0x8
602#define EEPROM_CHANNEL_PLAN_GLOBAL_DOMAIN 0x9
603#define EEPROM_CHANNEL_PLAN_WORLD_WIDE_13 0xA
604#define EEPROM_CHANNEL_PLAN_NCC 0xB
605#define EEPROM_CHANNEL_PLAN_BY_HW_MASK 0x80
606
607#define EEPROM_CID_DEFAULT 0x0
608#define EEPROM_CID_TOSHIBA 0x4
609#define EEPROM_CID_CCX 0x10
610#define EEPROM_CID_QMI 0x0D
611#define EEPROM_CID_WHQL 0xFE
612
613
614#define RTL8192_EEPROM_ID 0x8129
615#define EEPROM_WAPI_SUPPORT 0x78
616
617
618#define RTL8190_EEPROM_ID 0x8129 /* 0-1 */
619#define EEPROM_HPON 0x02 /* LDO settings.2-5 */
620#define EEPROM_CLK 0x06 /* Clock settings.6-7 */
621#define EEPROM_MAC_FUNCTION 0x08 /* SE Test mode.8 */
622
623#define EEPROM_VID 0x28 /* SE Vendor ID.A-B */
624#define EEPROM_DID 0x2A /* SE Device ID. C-D */
625#define EEPROM_SVID 0x2C /* SE Vendor ID.E-F */
626#define EEPROM_SMID 0x2E /* SE PCI Subsystem ID. 10-11 */
627
628#define EEPROM_MAC_ADDR 0x16 /* SEMAC Address. 12-17 */
629#define EEPROM_MAC_ADDR_MAC0_92D 0x55
630#define EEPROM_MAC_ADDR_MAC1_92D 0x5B
631
632/* 2.4G band Tx power index setting */
633#define EEPROM_CCK_TX_PWR_INX_2G 0x61
634#define EEPROM_HT40_1S_TX_PWR_INX_2G 0x67
635#define EEPROM_HT40_2S_TX_PWR_INX_DIFF_2G 0x6D
636#define EEPROM_HT20_TX_PWR_INX_DIFF_2G 0x70
637#define EEPROM_OFDM_TX_PWR_INX_DIFF_2G 0x73
638#define EEPROM_HT40_MAX_PWR_OFFSET_2G 0x76
639#define EEPROM_HT20_MAX_PWR_OFFSET_2G 0x79
640
641/*5GL channel 32-64 */
642#define EEPROM_HT40_1S_TX_PWR_INX_5GL 0x7C
643#define EEPROM_HT40_2S_TX_PWR_INX_DIFF_5GL 0x82
644#define EEPROM_HT20_TX_PWR_INX_DIFF_5GL 0x85
645#define EEPROM_OFDM_TX_PWR_INX_DIFF_5GL 0x88
646#define EEPROM_HT40_MAX_PWR_OFFSET_5GL 0x8B
647#define EEPROM_HT20_MAX_PWR_OFFSET_5GL 0x8E
648
649/* 5GM channel 100-140 */
650#define EEPROM_HT40_1S_TX_PWR_INX_5GM 0x91
651#define EEPROM_HT40_2S_TX_PWR_INX_DIFF_5GM 0x97
652#define EEPROM_HT20_TX_PWR_INX_DIFF_5GM 0x9A
653#define EEPROM_OFDM_TX_PWR_INX_DIFF_5GM 0x9D
654#define EEPROM_HT40_MAX_PWR_OFFSET_5GM 0xA0
655#define EEPROM_HT20_MAX_PWR_OFFSET_5GM 0xA3
656
657/* 5GH channel 149-165 */
658#define EEPROM_HT40_1S_TX_PWR_INX_5GH 0xA6
659#define EEPROM_HT40_2S_TX_PWR_INX_DIFF_5GH 0xAC
660#define EEPROM_HT20_TX_PWR_INX_DIFF_5GH 0xAF
661#define EEPROM_OFDM_TX_PWR_INX_DIFF_5GH 0xB2
662#define EEPROM_HT40_MAX_PWR_OFFSET_5GH 0xB5
663#define EEPROM_HT20_MAX_PWR_OFFSET_5GH 0xB8
664
665/* Map of supported channels. */
666#define EEPROM_CHANNEL_PLAN 0xBB
667#define EEPROM_IQK_DELTA 0xBC
668#define EEPROM_LCK_DELTA 0xBC
669#define EEPROM_XTAL_K 0xBD /* [7:5] */
670#define EEPROM_TSSI_A_5G 0xBE
671#define EEPROM_TSSI_B_5G 0xBF
672#define EEPROM_TSSI_AB_5G 0xC0
673#define EEPROM_THERMAL_METER 0xC3 /* [4:0] */
674#define EEPROM_RF_OPT1 0xC4
675#define EEPROM_RF_OPT2 0xC5
676#define EEPROM_RF_OPT3 0xC6
677#define EEPROM_RF_OPT4 0xC7
678#define EEPROM_RF_OPT5 0xC8
679#define EEPROM_RF_OPT6 0xC9
680#define EEPROM_VERSION 0xCA
681#define EEPROM_CUSTOMER_ID 0xCB
682#define EEPROM_RF_OPT7 0xCC
683
684#define EEPROM_DEF_PART_NO 0x3FD /* Byte */
685#define EEPROME_CHIP_VERSION_L 0x3FF
686#define EEPROME_CHIP_VERSION_H 0x3FE
687
688/*
689 * Current IOREG MAP
690 * 0x0000h ~ 0x00FFh System Configuration (256 Bytes)
691 * 0x0100h ~ 0x01FFh MACTOP General Configuration (256 Bytes)
692 * 0x0200h ~ 0x027Fh TXDMA Configuration (128 Bytes)
693 * 0x0280h ~ 0x02FFh RXDMA Configuration (128 Bytes)
694 * 0x0300h ~ 0x03FFh PCIE EMAC Reserved Region (256 Bytes)
695 * 0x0400h ~ 0x04FFh Protocol Configuration (256 Bytes)
696 * 0x0500h ~ 0x05FFh EDCA Configuration (256 Bytes)
697 * 0x0600h ~ 0x07FFh WMAC Configuration (512 Bytes)
698 * 0x2000h ~ 0x3FFFh 8051 FW Download Region (8196 Bytes)
699 */
700
701/* ----------------------------------------------------- */
702/* 8192C (RCR) (Offset 0x608, 32 bits) */
703/* ----------------------------------------------------- */
704#define RCR_APPFCS BIT(31)
705#define RCR_APP_MIC BIT(30)
706#define RCR_APP_ICV BIT(29)
707#define RCR_APP_PHYST_RXFF BIT(28)
708#define RCR_APP_BA_SSN BIT(27)
709#define RCR_ENMBID BIT(24)
710#define RCR_LSIGEN BIT(23)
711#define RCR_MFBEN BIT(22)
712#define RCR_HTC_LOC_CTRL BIT(14)
713#define RCR_AMF BIT(13)
714#define RCR_ACF BIT(12)
715#define RCR_ADF BIT(11)
716#define RCR_AICV BIT(9)
717#define RCR_ACRC32 BIT(8)
718#define RCR_CBSSID_BCN BIT(7)
719#define RCR_CBSSID_DATA BIT(6)
720#define RCR_APWRMGT BIT(5)
721#define RCR_ADD3 BIT(4)
722#define RCR_AB BIT(3)
723#define RCR_AM BIT(2)
724#define RCR_APM BIT(1)
725#define RCR_AAP BIT(0)
726#define RCR_MXDMA_OFFSET 8
727#define RCR_FIFO_OFFSET 13
728
729/* ----------------------------------------------------- */
730/* 8192C Regsiter Bit and Content definition */
731/* ----------------------------------------------------- */
732/* ----------------------------------------------------- */
733/* 0x0000h ~ 0x00FFh System Configuration */
734/* ----------------------------------------------------- */
735
736/* SPS0_CTRL */
737#define SW18_FPWM BIT(3)
738
739
740/* SYS_ISO_CTRL */
741#define ISO_MD2PP BIT(0)
742#define ISO_UA2USB BIT(1)
743#define ISO_UD2CORE BIT(2)
744#define ISO_PA2PCIE BIT(3)
745#define ISO_PD2CORE BIT(4)
746#define ISO_IP2MAC BIT(5)
747#define ISO_DIOP BIT(6)
748#define ISO_DIOE BIT(7)
749#define ISO_EB2CORE BIT(8)
750#define ISO_DIOR BIT(9)
751
752#define PWC_EV25V BIT(14)
753#define PWC_EV12V BIT(15)
754
755
756/* SYS_FUNC_EN */
757#define FEN_BBRSTB BIT(0)
758#define FEN_BB_GLB_RSTn BIT(1)
759#define FEN_USBA BIT(2)
760#define FEN_UPLL BIT(3)
761#define FEN_USBD BIT(4)
762#define FEN_DIO_PCIE BIT(5)
763#define FEN_PCIEA BIT(6)
764#define FEN_PPLL BIT(7)
765#define FEN_PCIED BIT(8)
766#define FEN_DIOE BIT(9)
767#define FEN_CPUEN BIT(10)
768#define FEN_DCORE BIT(11)
769#define FEN_ELDR BIT(12)
770#define FEN_DIO_RF BIT(13)
771#define FEN_HWPDN BIT(14)
772#define FEN_MREGEN BIT(15)
773
774/* APS_FSMCO */
775#define PFM_LDALL BIT(0)
776#define PFM_ALDN BIT(1)
777#define PFM_LDKP BIT(2)
778#define PFM_WOWL BIT(3)
779#define EnPDN BIT(4)
780#define PDN_PL BIT(5)
781#define APFM_ONMAC BIT(8)
782#define APFM_OFF BIT(9)
783#define APFM_RSM BIT(10)
784#define AFSM_HSUS BIT(11)
785#define AFSM_PCIE BIT(12)
786#define APDM_MAC BIT(13)
787#define APDM_HOST BIT(14)
788#define APDM_HPDN BIT(15)
789#define RDY_MACON BIT(16)
790#define SUS_HOST BIT(17)
791#define ROP_ALD BIT(20)
792#define ROP_PWR BIT(21)
793#define ROP_SPS BIT(22)
794#define SOP_MRST BIT(25)
795#define SOP_FUSE BIT(26)
796#define SOP_ABG BIT(27)
797#define SOP_AMB BIT(28)
798#define SOP_RCK BIT(29)
799#define SOP_A8M BIT(30)
800#define XOP_BTCK BIT(31)
801
802/* SYS_CLKR */
803#define ANAD16V_EN BIT(0)
804#define ANA8M BIT(1)
805#define MACSLP BIT(4)
806#define LOADER_CLK_EN BIT(5)
807#define _80M_SSC_DIS BIT(7)
808#define _80M_SSC_EN_HO BIT(8)
809#define PHY_SSC_RSTB BIT(9)
810#define SEC_CLK_EN BIT(10)
811#define MAC_CLK_EN BIT(11)
812#define SYS_CLK_EN BIT(12)
813#define RING_CLK_EN BIT(13)
814
815
816/* 9346CR */
817#define BOOT_FROM_EEPROM BIT(4)
818#define EEPROM_EN BIT(5)
819
820/* AFE_MISC */
821#define AFE_BGEN BIT(0)
822#define AFE_MBEN BIT(1)
823#define MAC_ID_EN BIT(7)
824
825/* RSV_CTRL */
826#define WLOCK_ALL BIT(0)
827#define WLOCK_00 BIT(1)
828#define WLOCK_04 BIT(2)
829#define WLOCK_08 BIT(3)
830#define WLOCK_40 BIT(4)
831#define R_DIS_PRST_0 BIT(5)
832#define R_DIS_PRST_1 BIT(6)
833#define LOCK_ALL_EN BIT(7)
834
835/* RF_CTRL */
836#define RF_EN BIT(0)
837#define RF_RSTB BIT(1)
838#define RF_SDMRSTB BIT(2)
839
840
841
842/* LDOA15_CTRL */
843#define LDA15_EN BIT(0)
844#define LDA15_STBY BIT(1)
845#define LDA15_OBUF BIT(2)
846#define LDA15_REG_VOS BIT(3)
847#define _LDA15_VOADJ(x) (((x) & 0x7) << 4)
848
849
850
851/* LDOV12D_CTRL */
852#define LDV12_EN BIT(0)
853#define LDV12_SDBY BIT(1)
854#define LPLDO_HSM BIT(2)
855#define LPLDO_LSM_DIS BIT(3)
856#define _LDV12_VADJ(x) (((x) & 0xF) << 4)
857
858
859/* AFE_XTAL_CTRL */
860#define XTAL_EN BIT(0)
861#define XTAL_BSEL BIT(1)
862#define _XTAL_BOSC(x) (((x) & 0x3) << 2)
863#define _XTAL_CADJ(x) (((x) & 0xF) << 4)
864#define XTAL_GATE_USB BIT(8)
865#define _XTAL_USB_DRV(x) (((x) & 0x3) << 9)
866#define XTAL_GATE_AFE BIT(11)
867#define _XTAL_AFE_DRV(x) (((x) & 0x3) << 12)
868#define XTAL_RF_GATE BIT(14)
869#define _XTAL_RF_DRV(x) (((x) & 0x3) << 15)
870#define XTAL_GATE_DIG BIT(17)
871#define _XTAL_DIG_DRV(x) (((x) & 0x3) << 18)
872#define XTAL_BT_GATE BIT(20)
873#define _XTAL_BT_DRV(x) (((x) & 0x3) << 21)
874#define _XTAL_GPIO(x) (((x) & 0x7) << 23)
875
876
877#define CKDLY_AFE BIT(26)
878#define CKDLY_USB BIT(27)
879#define CKDLY_DIG BIT(28)
880#define CKDLY_BT BIT(29)
881
882
883/* AFE_PLL_CTRL */
884#define APLL_EN BIT(0)
885#define APLL_320_EN BIT(1)
886#define APLL_FREF_SEL BIT(2)
887#define APLL_EDGE_SEL BIT(3)
888#define APLL_WDOGB BIT(4)
889#define APLL_LPFEN BIT(5)
890
891#define APLL_REF_CLK_13MHZ 0x1
892#define APLL_REF_CLK_19_2MHZ 0x2
893#define APLL_REF_CLK_20MHZ 0x3
894#define APLL_REF_CLK_25MHZ 0x4
895#define APLL_REF_CLK_26MHZ 0x5
896#define APLL_REF_CLK_38_4MHZ 0x6
897#define APLL_REF_CLK_40MHZ 0x7
898
899#define APLL_320EN BIT(14)
900#define APLL_80EN BIT(15)
901#define APLL_1MEN BIT(24)
902
903
904/* EFUSE_CTRL */
905#define ALD_EN BIT(18)
906#define EF_PD BIT(19)
907#define EF_FLAG BIT(31)
908
909/* EFUSE_TEST */
910#define EF_TRPT BIT(7)
911#define LDOE25_EN BIT(31)
912
913/* MCUFWDL */
914#define MCUFWDL_EN BIT(0)
915#define MCUFWDL_RDY BIT(1)
916#define FWDL_ChkSum_rpt BIT(2)
917#define MACINI_RDY BIT(3)
918#define BBINI_RDY BIT(4)
919#define RFINI_RDY BIT(5)
920#define WINTINI_RDY BIT(6)
921#define MAC1_WINTINI_RDY BIT(11)
922#define CPRST BIT(23)
923
924/* REG_SYS_CFG */
925#define XCLK_VLD BIT(0)
926#define ACLK_VLD BIT(1)
927#define UCLK_VLD BIT(2)
928#define PCLK_VLD BIT(3)
929#define PCIRSTB BIT(4)
930#define V15_VLD BIT(5)
931#define TRP_B15V_EN BIT(7)
932#define SIC_IDLE BIT(8)
933#define BD_MAC2 BIT(9)
934#define BD_MAC1 BIT(10)
935#define IC_MACPHY_MODE BIT(11)
936#define PAD_HWPD_IDN BIT(22)
937#define TRP_VAUX_EN BIT(23)
938#define TRP_BT_EN BIT(24)
939#define BD_PKG_SEL BIT(25)
940#define BD_HCI_SEL BIT(26)
941#define TYPE_ID BIT(27)
942
943/* LLT_INIT */
944#define _LLT_NO_ACTIVE 0x0
945#define _LLT_WRITE_ACCESS 0x1
946#define _LLT_READ_ACCESS 0x2
947
948#define _LLT_INIT_DATA(x) ((x) & 0xFF)
949#define _LLT_INIT_ADDR(x) (((x) & 0xFF) << 8)
950#define _LLT_OP(x) (((x) & 0x3) << 30)
951#define _LLT_OP_VALUE(x) (((x) >> 30) & 0x3)
952
953
954/* ----------------------------------------------------- */
955/* 0x0400h ~ 0x047Fh Protocol Configuration */
956/* ----------------------------------------------------- */
957#define RETRY_LIMIT_SHORT_SHIFT 8
958#define RETRY_LIMIT_LONG_SHIFT 0
959
960
961/* ----------------------------------------------------- */
962/* 0x0500h ~ 0x05FFh EDCA Configuration */
963/* ----------------------------------------------------- */
964/* EDCA setting */
965#define AC_PARAM_TXOP_LIMIT_OFFSET 16
966#define AC_PARAM_ECW_MAX_OFFSET 12
967#define AC_PARAM_ECW_MIN_OFFSET 8
968#define AC_PARAM_AIFS_OFFSET 0
969
970/* ACMHWCTRL */
971#define ACMHW_HWEN BIT(0)
972#define ACMHW_BEQEN BIT(1)
973#define ACMHW_VIQEN BIT(2)
974#define ACMHW_VOQEN BIT(3)
975
976/* ----------------------------------------------------- */
977/* 0x0600h ~ 0x07FFh WMAC Configuration */
978/* ----------------------------------------------------- */
979
980/* TCR */
981#define TSFRST BIT(0)
982#define DIS_GCLK BIT(1)
983#define PAD_SEL BIT(2)
984#define PWR_ST BIT(6)
985#define PWRBIT_OW_EN BIT(7)
986#define ACRC BIT(8)
987#define CFENDFORM BIT(9)
988#define ICV BIT(10)
989
990/* SECCFG */
991#define SCR_TXUSEDK BIT(0)
992#define SCR_RXUSEDK BIT(1)
993#define SCR_TXENCENABLE BIT(2)
994#define SCR_RXENCENABLE BIT(3)
995#define SCR_SKBYA2 BIT(4)
996#define SCR_NOSKMC BIT(5)
997#define SCR_TXBCUSEDK BIT(6)
998#define SCR_RXBCUSEDK BIT(7)
999
1000/* General definitions */
1001#define MAC_ADDR_LEN 6
1002#define LAST_ENTRY_OF_TX_PKT_BUFFER 255
1003#define LAST_ENTRY_OF_TX_PKT_BUFFER_DUAL_MAC 127
1004
1005#define POLLING_LLT_THRESHOLD 20
1006#define POLLING_READY_TIMEOUT_COUNT 1000
1007
1008/* Min Spacing related settings. */
1009#define MAX_MSS_DENSITY_2T 0x13
1010#define MAX_MSS_DENSITY_1T 0x0A
1011
1012
1013/* BB-PHY register PMAC 0x100 PHY 0x800 - 0xEFF */
1014/* 1. PMAC duplicate register due to connection: */
1015/* RF_Mode, TRxRN, NumOf L-STF */
1016/* 2. 0x800/0x900/0xA00/0xC00/0xD00/0xE00 */
1017/* 3. RF register 0x00-2E */
1018/* 4. Bit Mask for BB/RF register */
1019/* 5. Other defintion for BB/RF R/W */
1020
1021/* 3. Page8(0x800) */
1022#define RFPGA0_RFMOD 0x800
1023
1024#define RFPGA0_TXINFO 0x804
1025#define RFPGA0_PSDFUNCTION 0x808
1026
1027#define RFPGA0_TXGAINSTAGE 0x80c
1028
1029#define RFPGA0_RFTIMING1 0x810
1030#define RFPGA0_RFTIMING2 0x814
1031
1032#define RFPGA0_XA_HSSIPARAMETER1 0x820
1033#define RFPGA0_XA_HSSIPARAMETER2 0x824
1034#define RFPGA0_XB_HSSIPARAMETER1 0x828
1035#define RFPGA0_XB_HSSIPARAMETER2 0x82c
1036
1037#define RFPGA0_XA_LSSIPARAMETER 0x840
1038#define RFPGA0_XB_LSSIPARAMETER 0x844
1039
1040#define RFPGA0_RFWAkEUPPARAMETER 0x850
1041#define RFPGA0_RFSLEEPUPPARAMETER 0x854
1042
1043#define RFPGA0_XAB_SWITCHCONTROL 0x858
1044#define RFPGA0_XCD_SWITCHCONTROL 0x85c
1045
1046#define RFPGA0_XA_RFINTERFACEOE 0x860
1047#define RFPGA0_XB_RFINTERFACEOE 0x864
1048
1049#define RFPGA0_XAB_RFINTERFACESW 0x870
1050#define RFPGA0_XCD_RFINTERFACESW 0x874
1051
1052#define RFPGA0_XAB_RFPARAMETER 0x878
1053#define RFPGA0_XCD_RFPARAMETER 0x87c
1054
1055#define RFPGA0_ANALOGPARAMETER1 0x880
1056#define RFPGA0_ANALOGPARAMETER2 0x884
1057#define RFPGA0_ANALOGPARAMETER3 0x888
1058#define RFPGA0_ADDALLOCKEN 0x888
1059#define RFPGA0_ANALOGPARAMETER4 0x88c
1060
1061#define RFPGA0_XA_LSSIREADBACK 0x8a0
1062#define RFPGA0_XB_LSSIREADBACK 0x8a4
1063#define RFPGA0_XC_LSSIREADBACK 0x8a8
1064#define RFPGA0_XD_LSSIREADBACK 0x8ac
1065
1066#define RFPGA0_PSDREPORT 0x8b4
1067#define TRANSCEIVERA_HSPI_READBACK 0x8b8
1068#define TRANSCEIVERB_HSPI_READBACK 0x8bc
1069#define RFPGA0_XAB_RFINTERFACERB 0x8e0
1070#define RFPGA0_XCD_RFINTERFACERB 0x8e4
1071
1072/* 4. Page9(0x900) */
1073#define RFPGA1_RFMOD 0x900
1074
1075#define RFPGA1_TXBLOCK 0x904
1076#define RFPGA1_DEBUGSELECT 0x908
1077#define RFPGA1_TXINFO 0x90c
1078
1079/* 5. PageA(0xA00) */
1080#define RCCK0_SYSTEM 0xa00
1081
1082#define RCCK0_AFESSTTING 0xa04
1083#define RCCK0_CCA 0xa08
1084
1085#define RCCK0_RXAGC1 0xa0c
1086#define RCCK0_RXAGC2 0xa10
1087
1088#define RCCK0_RXHP 0xa14
1089
1090#define RCCK0_DSPPARAMETER1 0xa18
1091#define RCCK0_DSPPARAMETER2 0xa1c
1092
1093#define RCCK0_TXFILTER1 0xa20
1094#define RCCK0_TXFILTER2 0xa24
1095#define RCCK0_DEBUGPORT 0xa28
1096#define RCCK0_FALSEALARMREPORT 0xa2c
1097#define RCCK0_TRSSIREPORT 0xa50
1098#define RCCK0_RXREPORT 0xa54
1099#define RCCK0_FACOUNTERLOWER 0xa5c
1100#define RCCK0_FACOUNTERUPPER 0xa58
1101
1102/* 6. PageC(0xC00) */
1103#define ROFDM0_LSTF 0xc00
1104
1105#define ROFDM0_TRXPATHENABLE 0xc04
1106#define ROFDM0_TRMUXPAR 0xc08
1107#define ROFDM0_TRSWISOLATION 0xc0c
1108
1109#define ROFDM0_XARXAFE 0xc10
1110#define ROFDM0_XARXIQIMBALANCE 0xc14
1111#define ROFDM0_XBRXAFE 0xc18
1112#define ROFDM0_XBRXIQIMBALANCE 0xc1c
1113#define ROFDM0_XCRXAFE 0xc20
1114#define ROFDM0_XCRXIQIMBALANCE 0xc24
1115#define ROFDM0_XDRXAFE 0xc28
1116#define ROFDM0_XDRXIQIMBALANCE 0xc2c
1117
1118#define ROFDM0_RXDETECTOR1 0xc30
1119#define ROFDM0_RXDETECTOR2 0xc34
1120#define ROFDM0_RXDETECTOR3 0xc38
1121#define ROFDM0_RXDETECTOR4 0xc3c
1122
1123#define ROFDM0_RXDSP 0xc40
1124#define ROFDM0_CFOANDDAGC 0xc44
1125#define ROFDM0_CCADROPTHRESHOLD 0xc48
1126#define ROFDM0_ECCATHRESHOLD 0xc4c
1127
1128#define ROFDM0_XAAGCCORE1 0xc50
1129#define ROFDM0_XAAGCCORE2 0xc54
1130#define ROFDM0_XBAGCCORE1 0xc58
1131#define ROFDM0_XBAGCCORE2 0xc5c
1132#define ROFDM0_XCAGCCORE1 0xc60
1133#define ROFDM0_XCAGCCORE2 0xc64
1134#define ROFDM0_XDAGCCORE1 0xc68
1135#define ROFDM0_XDAGCCORE2 0xc6c
1136
1137#define ROFDM0_AGCPARAMETER1 0xc70
1138#define ROFDM0_AGCPARAMETER2 0xc74
1139#define ROFDM0_AGCRSSITABLE 0xc78
1140#define ROFDM0_HTSTFAGC 0xc7c
1141
1142#define ROFDM0_XATxIQIMBALANCE 0xc80
1143#define ROFDM0_XATxAFE 0xc84
1144#define ROFDM0_XBTxIQIMBALANCE 0xc88
1145#define ROFDM0_XBTxAFE 0xc8c
1146#define ROFDM0_XCTxIQIMBALANCE 0xc90
1147#define ROFDM0_XCTxAFE 0xc94
1148#define ROFDM0_XDTxIQIMBALANCE 0xc98
1149#define ROFDM0_XDTxAFE 0xc9c
1150
1151#define ROFDM0_RXHPPARAMETER 0xce0
1152#define ROFDM0_TXPSEUDONOISEWGT 0xce4
1153#define ROFDM0_FRAMESYNC 0xcf0
1154#define ROFDM0_DFSREPORT 0xcf4
1155#define ROFDM0_TXCOEFF1 0xca4
1156#define ROFDM0_TXCOEFF2 0xca8
1157#define ROFDM0_TXCOEFF3 0xcac
1158#define ROFDM0_TXCOEFF4 0xcb0
1159#define ROFDM0_TXCOEFF5 0xcb4
1160#define ROFDM0_TXCOEFF6 0xcb8
1161
1162/* 7. PageD(0xD00) */
1163#define ROFDM1_LSTF 0xd00
1164#define ROFDM1_TRXPATHENABLE 0xd04
1165
1166#define ROFDM1_CFO 0xd08
1167#define ROFDM1_CSI1 0xd10
1168#define ROFDM1_SBD 0xd14
1169#define ROFDM1_CSI2 0xd18
1170#define ROFDM1_CFOTRACKING 0xd2c
1171#define ROFDM1_TRXMESAURE1 0xd34
1172#define ROFDM1_INTFDET 0xd3c
1173#define ROFDM1_PSEUDONOISESTATEAB 0xd50
1174#define ROFDM1_PSEUDONOISESTATECD 0xd54
1175#define ROFDM1_RXPSEUDONOISEWGT 0xd58
1176
1177#define ROFDM_PHYCOUNTER1 0xda0
1178#define ROFDM_PHYCOUNTER2 0xda4
1179#define ROFDM_PHYCOUNTER3 0xda8
1180
1181#define ROFDM_SHORTCFOAB 0xdac
1182#define ROFDM_SHORTCFOCD 0xdb0
1183#define ROFDM_LONGCFOAB 0xdb4
1184#define ROFDM_LONGCFOCD 0xdb8
1185#define ROFDM_TAILCFOAB 0xdbc
1186#define ROFDM_TAILCFOCD 0xdc0
1187#define ROFDM_PWMEASURE1 0xdc4
1188#define ROFDM_PWMEASURE2 0xdc8
1189#define ROFDM_BWREPORT 0xdcc
1190#define ROFDM_AGCREPORT 0xdd0
1191#define ROFDM_RXSNR 0xdd4
1192#define ROFDM_RXEVMCSI 0xdd8
1193#define ROFDM_SIGReport 0xddc
1194
1195/* 8. PageE(0xE00) */
1196#define RTXAGC_A_RATE18_06 0xe00
1197#define RTXAGC_A_RATE54_24 0xe04
1198#define RTXAGC_A_CCK1_MCS32 0xe08
1199#define RTXAGC_A_MCS03_MCS00 0xe10
1200#define RTXAGC_A_MCS07_MCS04 0xe14
1201#define RTXAGC_A_MCS11_MCS08 0xe18
1202#define RTXAGC_A_MCS15_MCS12 0xe1c
1203
1204#define RTXAGC_B_RATE18_06 0x830
1205#define RTXAGC_B_RATE54_24 0x834
1206#define RTXAGC_B_CCK1_55_MCS32 0x838
1207#define RTXAGC_B_MCS03_MCS00 0x83c
1208#define RTXAGC_B_MCS07_MCS04 0x848
1209#define RTXAGC_B_MCS11_MCS08 0x84c
1210#define RTXAGC_B_MCS15_MCS12 0x868
1211#define RTXAGC_B_CCK11_A_CCK2_11 0x86c
1212
1213/* RL6052 Register definition */
1214#define RF_AC 0x00
1215
1216#define RF_IQADJ_G1 0x01
1217#define RF_IQADJ_G2 0x02
1218#define RF_POW_TRSW 0x05
1219
1220#define RF_GAIN_RX 0x06
1221#define RF_GAIN_TX 0x07
1222
1223#define RF_TXM_IDAC 0x08
1224#define RF_BS_IQGEN 0x0F
1225
1226#define RF_MODE1 0x10
1227#define RF_MODE2 0x11
1228
1229#define RF_RX_AGC_HP 0x12
1230#define RF_TX_AGC 0x13
1231#define RF_BIAS 0x14
1232#define RF_IPA 0x15
1233#define RF_POW_ABILITY 0x17
1234#define RF_MODE_AG 0x18
1235#define rRfChannel 0x18
1236#define RF_CHNLBW 0x18
1237#define RF_TOP 0x19
1238
1239#define RF_RX_G1 0x1A
1240#define RF_RX_G2 0x1B
1241
1242#define RF_RX_BB2 0x1C
1243#define RF_RX_BB1 0x1D
1244
1245#define RF_RCK1 0x1E
1246#define RF_RCK2 0x1F
1247
1248#define RF_TX_G1 0x20
1249#define RF_TX_G2 0x21
1250#define RF_TX_G3 0x22
1251
1252#define RF_TX_BB1 0x23
1253
1254#define RF_T_METER 0x42
1255
1256#define RF_SYN_G1 0x25
1257#define RF_SYN_G2 0x26
1258#define RF_SYN_G3 0x27
1259#define RF_SYN_G4 0x28
1260#define RF_SYN_G5 0x29
1261#define RF_SYN_G6 0x2A
1262#define RF_SYN_G7 0x2B
1263#define RF_SYN_G8 0x2C
1264
1265#define RF_RCK_OS 0x30
1266
1267#define RF_TXPA_G1 0x31
1268#define RF_TXPA_G2 0x32
1269#define RF_TXPA_G3 0x33
1270
1271/* Bit Mask */
1272
1273/* 2. Page8(0x800) */
1274#define BRFMOD 0x1
1275#define BCCKTXSC 0x30
1276#define BCCKEN 0x1000000
1277#define BOFDMEN 0x2000000
1278
1279#define B3WIREDATALENGTH 0x800
1280#define B3WIREADDRESSLENGTH 0x400
1281
1282#define BRFSI_RFENV 0x10
1283
1284#define BLSSIREADADDRESS 0x7f800000
1285#define BLSSIREADEDGE 0x80000000
1286#define BLSSIREADBACKDATA 0xfffff
1287/* 4. PageA(0xA00) */
1288#define BCCKSIDEBAND 0x10
1289
1290/* Other Definition */
1291#define BBYTE0 0x1
1292#define BBYTE1 0x2
1293#define BBYTE2 0x4
1294#define BBYTE3 0x8
1295#define BWORD0 0x3
1296#define BWORD1 0xc
1297#define BDWORD 0xf
1298
1299#define BMASKBYTE0 0xff
1300#define BMASKBYTE1 0xff00
1301#define BMASKBYTE2 0xff0000
1302#define BMASKBYTE3 0xff000000
1303#define BMASKHWORD 0xffff0000
1304#define BMASKLWORD 0x0000ffff
1305#define BMASKDWORD 0xffffffff
1306#define BMASK12BITS 0xfff
1307#define BMASKH4BITS 0xf0000000
1308#define BMASKOFDM_D 0xffc00000
1309#define BMASKCCK 0x3f3f3f3f
1310
1311#define BRFREGOFFSETMASK 0xfffff
1312
1313#endif