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1/*
2 * Marvell Wireless LAN device driver: SDIO specific definitions
3 *
4 * Copyright (C) 2011, Marvell International Ltd.
5 *
6 * This software file (the "File") is distributed by Marvell International
7 * Ltd. under the terms of the GNU General Public License Version 2, June 1991
8 * (the "License"). You may use, redistribute and/or modify this File in
9 * accordance with the terms and conditions of the License, a copy of which
10 * is available by writing to the Free Software Foundation, Inc.,
11 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA or on the
12 * worldwide web at http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt.
13 *
14 * THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE
15 * IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE
16 * ARE EXPRESSLY DISCLAIMED. The License provides additional details about
17 * this warranty disclaimer.
18 */
19
20#ifndef _MWIFIEX_SDIO_H
21#define _MWIFIEX_SDIO_H
22
23
24#include <linux/mmc/sdio.h>
25#include <linux/mmc/sdio_ids.h>
26#include <linux/mmc/sdio_func.h>
27#include <linux/mmc/card.h>
28
29#include "main.h"
30
31#define SD8787_DEFAULT_FW_NAME "mrvl/sd8787_uapsta.bin"
32
33#define BLOCK_MODE 1
34#define BYTE_MODE 0
35
36#define REG_PORT 0
37#define RD_BITMAP_L 0x04
38#define RD_BITMAP_U 0x05
39#define WR_BITMAP_L 0x06
40#define WR_BITMAP_U 0x07
41#define RD_LEN_P0_L 0x08
42#define RD_LEN_P0_U 0x09
43
44#define MWIFIEX_SDIO_IO_PORT_MASK 0xfffff
45
46#define MWIFIEX_SDIO_BYTE_MODE_MASK 0x80000000
47
48#define CTRL_PORT 0
49#define CTRL_PORT_MASK 0x0001
50#define DATA_PORT_MASK 0xfffe
51
52#define MAX_MP_REGS 64
53#define MAX_PORT 16
54
55#define SDIO_MP_AGGR_DEF_PKT_LIMIT 8
56
57#define SDIO_MP_TX_AGGR_DEF_BUF_SIZE (8192) /* 8K */
58
59/* Multi port RX aggregation buffer size */
60#define SDIO_MP_RX_AGGR_DEF_BUF_SIZE (16384) /* 16K */
61
62/* Misc. Config Register : Auto Re-enable interrupts */
63#define AUTO_RE_ENABLE_INT BIT(4)
64
65/* Host Control Registers */
66/* Host Control Registers : I/O port 0 */
67#define IO_PORT_0_REG 0x78
68/* Host Control Registers : I/O port 1 */
69#define IO_PORT_1_REG 0x79
70/* Host Control Registers : I/O port 2 */
71#define IO_PORT_2_REG 0x7A
72
73/* Host Control Registers : Configuration */
74#define CONFIGURATION_REG 0x00
75/* Host Control Registers : Host without Command 53 finish host*/
76#define HOST_TO_CARD_EVENT (0x1U << 3)
77/* Host Control Registers : Host without Command 53 finish host */
78#define HOST_WO_CMD53_FINISH_HOST (0x1U << 2)
79/* Host Control Registers : Host power up */
80#define HOST_POWER_UP (0x1U << 1)
81/* Host Control Registers : Host power down */
82#define HOST_POWER_DOWN (0x1U << 0)
83
84/* Host Control Registers : Host interrupt mask */
85#define HOST_INT_MASK_REG 0x02
86/* Host Control Registers : Upload host interrupt mask */
87#define UP_LD_HOST_INT_MASK (0x1U)
88/* Host Control Registers : Download host interrupt mask */
89#define DN_LD_HOST_INT_MASK (0x2U)
90/* Enable Host interrupt mask */
91#define HOST_INT_ENABLE (UP_LD_HOST_INT_MASK | DN_LD_HOST_INT_MASK)
92/* Disable Host interrupt mask */
93#define HOST_INT_DISABLE 0xff
94
95/* Host Control Registers : Host interrupt status */
96#define HOST_INTSTATUS_REG 0x03
97/* Host Control Registers : Upload host interrupt status */
98#define UP_LD_HOST_INT_STATUS (0x1U)
99/* Host Control Registers : Download host interrupt status */
100#define DN_LD_HOST_INT_STATUS (0x2U)
101
102/* Host Control Registers : Host interrupt RSR */
103#define HOST_INT_RSR_REG 0x01
104/* Host Control Registers : Upload host interrupt RSR */
105#define UP_LD_HOST_INT_RSR (0x1U)
106#define SDIO_INT_MASK 0x3F
107
108/* Host Control Registers : Host interrupt status */
109#define HOST_INT_STATUS_REG 0x28
110/* Host Control Registers : Upload CRC error */
111#define UP_LD_CRC_ERR (0x1U << 2)
112/* Host Control Registers : Upload restart */
113#define UP_LD_RESTART (0x1U << 1)
114/* Host Control Registers : Download restart */
115#define DN_LD_RESTART (0x1U << 0)
116
117/* Card Control Registers : Card status register */
118#define CARD_STATUS_REG 0x30
119/* Card Control Registers : Card I/O ready */
120#define CARD_IO_READY (0x1U << 3)
121/* Card Control Registers : CIS card ready */
122#define CIS_CARD_RDY (0x1U << 2)
123/* Card Control Registers : Upload card ready */
124#define UP_LD_CARD_RDY (0x1U << 1)
125/* Card Control Registers : Download card ready */
126#define DN_LD_CARD_RDY (0x1U << 0)
127
128/* Card Control Registers : Host interrupt mask register */
129#define HOST_INTERRUPT_MASK_REG 0x34
130/* Card Control Registers : Host power interrupt mask */
131#define HOST_POWER_INT_MASK (0x1U << 3)
132/* Card Control Registers : Abort card interrupt mask */
133#define ABORT_CARD_INT_MASK (0x1U << 2)
134/* Card Control Registers : Upload card interrupt mask */
135#define UP_LD_CARD_INT_MASK (0x1U << 1)
136/* Card Control Registers : Download card interrupt mask */
137#define DN_LD_CARD_INT_MASK (0x1U << 0)
138
139/* Card Control Registers : Card interrupt status register */
140#define CARD_INTERRUPT_STATUS_REG 0x38
141/* Card Control Registers : Power up interrupt */
142#define POWER_UP_INT (0x1U << 4)
143/* Card Control Registers : Power down interrupt */
144#define POWER_DOWN_INT (0x1U << 3)
145
146/* Card Control Registers : Card interrupt RSR register */
147#define CARD_INTERRUPT_RSR_REG 0x3c
148/* Card Control Registers : Power up RSR */
149#define POWER_UP_RSR (0x1U << 4)
150/* Card Control Registers : Power down RSR */
151#define POWER_DOWN_RSR (0x1U << 3)
152
153/* Card Control Registers : Miscellaneous Configuration Register */
154#define CARD_MISC_CFG_REG 0x6C
155
156/* Host F1 read base 0 */
157#define HOST_F1_RD_BASE_0 0x0040
158/* Host F1 read base 1 */
159#define HOST_F1_RD_BASE_1 0x0041
160/* Host F1 card ready */
161#define HOST_F1_CARD_RDY 0x0020
162
163/* Firmware status 0 register */
164#define CARD_FW_STATUS0_REG 0x60
165/* Firmware status 1 register */
166#define CARD_FW_STATUS1_REG 0x61
167/* Rx length register */
168#define CARD_RX_LEN_REG 0x62
169/* Rx unit register */
170#define CARD_RX_UNIT_REG 0x63
171
172/* Event header len w/o 4 bytes of interface header */
173#define MWIFIEX_EVENT_HEADER_LEN 4
174
175/* Max retry number of CMD53 write */
176#define MAX_WRITE_IOMEM_RETRY 2
177
178/* SDIO Tx aggregation in progress ? */
179#define MP_TX_AGGR_IN_PROGRESS(a) (a->mpa_tx.pkt_cnt > 0)
180
181/* SDIO Tx aggregation buffer room for next packet ? */
182#define MP_TX_AGGR_BUF_HAS_ROOM(a, len) ((a->mpa_tx.buf_len+len) \
183 <= a->mpa_tx.buf_size)
184
185/* Copy current packet (SDIO Tx aggregation buffer) to SDIO buffer */
186#define MP_TX_AGGR_BUF_PUT(a, payload, pkt_len, port) do { \
187 memmove(&a->mpa_tx.buf[a->mpa_tx.buf_len], \
188 payload, pkt_len); \
189 a->mpa_tx.buf_len += pkt_len; \
190 if (!a->mpa_tx.pkt_cnt) \
191 a->mpa_tx.start_port = port; \
192 if (a->mpa_tx.start_port <= port) \
193 a->mpa_tx.ports |= (1<<(a->mpa_tx.pkt_cnt)); \
194 else \
195 a->mpa_tx.ports |= (1<<(a->mpa_tx.pkt_cnt+1+(MAX_PORT - \
196 a->mp_end_port))); \
197 a->mpa_tx.pkt_cnt++; \
198} while (0);
199
200/* SDIO Tx aggregation limit ? */
201#define MP_TX_AGGR_PKT_LIMIT_REACHED(a) \
202 (a->mpa_tx.pkt_cnt == a->mpa_tx.pkt_aggr_limit)
203
204/* SDIO Tx aggregation port limit ? */
205#define MP_TX_AGGR_PORT_LIMIT_REACHED(a) ((a->curr_wr_port < \
206 a->mpa_tx.start_port) && (((MAX_PORT - \
207 a->mpa_tx.start_port) + a->curr_wr_port) >= \
208 SDIO_MP_AGGR_DEF_PKT_LIMIT))
209
210/* Reset SDIO Tx aggregation buffer parameters */
211#define MP_TX_AGGR_BUF_RESET(a) do { \
212 a->mpa_tx.pkt_cnt = 0; \
213 a->mpa_tx.buf_len = 0; \
214 a->mpa_tx.ports = 0; \
215 a->mpa_tx.start_port = 0; \
216} while (0);
217
218/* SDIO Rx aggregation limit ? */
219#define MP_RX_AGGR_PKT_LIMIT_REACHED(a) \
220 (a->mpa_rx.pkt_cnt == a->mpa_rx.pkt_aggr_limit)
221
222/* SDIO Tx aggregation port limit ? */
223#define MP_RX_AGGR_PORT_LIMIT_REACHED(a) ((a->curr_rd_port < \
224 a->mpa_rx.start_port) && (((MAX_PORT - \
225 a->mpa_rx.start_port) + a->curr_rd_port) >= \
226 SDIO_MP_AGGR_DEF_PKT_LIMIT))
227
228/* SDIO Rx aggregation in progress ? */
229#define MP_RX_AGGR_IN_PROGRESS(a) (a->mpa_rx.pkt_cnt > 0)
230
231/* SDIO Rx aggregation buffer room for next packet ? */
232#define MP_RX_AGGR_BUF_HAS_ROOM(a, rx_len) \
233 ((a->mpa_rx.buf_len+rx_len) <= a->mpa_rx.buf_size)
234
235/* Prepare to copy current packet from card to SDIO Rx aggregation buffer */
236#define MP_RX_AGGR_SETUP(a, skb, port) do { \
237 a->mpa_rx.buf_len += skb->len; \
238 if (!a->mpa_rx.pkt_cnt) \
239 a->mpa_rx.start_port = port; \
240 if (a->mpa_rx.start_port <= port) \
241 a->mpa_rx.ports |= (1<<(a->mpa_rx.pkt_cnt)); \
242 else \
243 a->mpa_rx.ports |= (1<<(a->mpa_rx.pkt_cnt+1)); \
244 a->mpa_rx.skb_arr[a->mpa_rx.pkt_cnt] = skb; \
245 a->mpa_rx.len_arr[a->mpa_rx.pkt_cnt] = skb->len; \
246 a->mpa_rx.pkt_cnt++; \
247} while (0);
248
249/* Reset SDIO Rx aggregation buffer parameters */
250#define MP_RX_AGGR_BUF_RESET(a) do { \
251 a->mpa_rx.pkt_cnt = 0; \
252 a->mpa_rx.buf_len = 0; \
253 a->mpa_rx.ports = 0; \
254 a->mpa_rx.start_port = 0; \
255} while (0);
256
257
258/* data structure for SDIO MPA TX */
259struct mwifiex_sdio_mpa_tx {
260 /* multiport tx aggregation buffer pointer */
261 u8 *buf;
262 u32 buf_len;
263 u32 pkt_cnt;
264 u16 ports;
265 u16 start_port;
266 u8 enabled;
267 u32 buf_size;
268 u32 pkt_aggr_limit;
269};
270
271struct mwifiex_sdio_mpa_rx {
272 u8 *buf;
273 u32 buf_len;
274 u32 pkt_cnt;
275 u16 ports;
276 u16 start_port;
277
278 struct sk_buff *skb_arr[SDIO_MP_AGGR_DEF_PKT_LIMIT];
279 u32 len_arr[SDIO_MP_AGGR_DEF_PKT_LIMIT];
280
281 u8 enabled;
282 u32 buf_size;
283 u32 pkt_aggr_limit;
284};
285
286int mwifiex_bus_register(void);
287void mwifiex_bus_unregister(void);
288
289struct sdio_mmc_card {
290 struct sdio_func *func;
291 struct mwifiex_adapter *adapter;
292
293 u16 mp_rd_bitmap;
294 u16 mp_wr_bitmap;
295
296 u16 mp_end_port;
297 u16 mp_data_port_mask;
298
299 u8 curr_rd_port;
300 u8 curr_wr_port;
301
302 u8 *mp_regs;
303
304 struct mwifiex_sdio_mpa_tx mpa_tx;
305 struct mwifiex_sdio_mpa_rx mpa_rx;
306};
307#endif /* _MWIFIEX_SDIO_H */