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1#ifndef B43legacy_XMIT_H_
2#define B43legacy_XMIT_H_
3
4#include "main.h"
5
6
7#define _b43legacy_declare_plcp_hdr(size) \
8 struct b43legacy_plcp_hdr##size { \
9 union { \
10 __le32 data; \
11 __u8 raw[size]; \
12 } __packed; \
13 } __packed
14
15/* struct b43legacy_plcp_hdr4 */
16_b43legacy_declare_plcp_hdr(4);
17/* struct b43legacy_plcp_hdr6 */
18_b43legacy_declare_plcp_hdr(6);
19
20#undef _b43legacy_declare_plcp_hdr
21
22
23/* TX header for v3 firmware */
24struct b43legacy_txhdr_fw3 {
25 __le32 mac_ctl; /* MAC TX control */
26 __le16 mac_frame_ctl; /* Copy of the FrameControl */
27 __le16 tx_fes_time_norm; /* TX FES Time Normal */
28 __le16 phy_ctl; /* PHY TX control */
29 __u8 iv[16]; /* Encryption IV */
30 __u8 tx_receiver[6]; /* TX Frame Receiver address */
31 __le16 tx_fes_time_fb; /* TX FES Time Fallback */
32 struct b43legacy_plcp_hdr4 rts_plcp_fb; /* RTS fallback PLCP */
33 __le16 rts_dur_fb; /* RTS fallback duration */
34 struct b43legacy_plcp_hdr4 plcp_fb; /* Fallback PLCP */
35 __le16 dur_fb; /* Fallback duration */
36 PAD_BYTES(2);
37 __le16 cookie;
38 __le16 unknown_scb_stuff;
39 struct b43legacy_plcp_hdr6 rts_plcp; /* RTS PLCP */
40 __u8 rts_frame[18]; /* The RTS frame (if used) */
41 struct b43legacy_plcp_hdr6 plcp;
42} __packed;
43
44/* MAC TX control */
45#define B43legacy_TX4_MAC_KEYIDX 0x0FF00000 /* Security key index */
46#define B43legacy_TX4_MAC_KEYIDX_SHIFT 20
47#define B43legacy_TX4_MAC_KEYALG 0x00070000 /* Security key algorithm */
48#define B43legacy_TX4_MAC_KEYALG_SHIFT 16
49#define B43legacy_TX4_MAC_LIFETIME 0x00001000
50#define B43legacy_TX4_MAC_FRAMEBURST 0x00000800
51#define B43legacy_TX4_MAC_SENDCTS 0x00000400
52#define B43legacy_TX4_MAC_AMPDU 0x00000300
53#define B43legacy_TX4_MAC_AMPDU_SHIFT 8
54#define B43legacy_TX4_MAC_CTSFALLBACKOFDM 0x00000200
55#define B43legacy_TX4_MAC_FALLBACKOFDM 0x00000100
56#define B43legacy_TX4_MAC_5GHZ 0x00000080
57#define B43legacy_TX4_MAC_IGNPMQ 0x00000020
58#define B43legacy_TX4_MAC_HWSEQ 0x00000010 /* Use Hardware Seq No */
59#define B43legacy_TX4_MAC_STMSDU 0x00000008 /* Start MSDU */
60#define B43legacy_TX4_MAC_SENDRTS 0x00000004
61#define B43legacy_TX4_MAC_LONGFRAME 0x00000002
62#define B43legacy_TX4_MAC_ACK 0x00000001
63
64/* Extra Frame Types */
65#define B43legacy_TX4_EFT_FBOFDM 0x0001 /* Data frame fb rate type */
66#define B43legacy_TX4_EFT_RTSOFDM 0x0004 /* RTS/CTS rate type */
67#define B43legacy_TX4_EFT_RTSFBOFDM 0x0010 /* RTS/CTS fallback rate type */
68
69/* PHY TX control word */
70#define B43legacy_TX4_PHY_ENC 0x0003 /* Data frame encoding */
71#define B43legacy_TX4_PHY_ENC_CCK 0x0000 /* CCK */
72#define B43legacy_TX4_PHY_ENC_OFDM 0x0001 /* Data frame rate type */
73#define B43legacy_TX4_PHY_SHORTPRMBL 0x0010 /* Use short preamble */
74#define B43legacy_TX4_PHY_ANT 0x03C0 /* Antenna selection */
75#define B43legacy_TX4_PHY_ANT0 0x0000 /* Use antenna 0 */
76#define B43legacy_TX4_PHY_ANT1 0x0100 /* Use antenna 1 */
77#define B43legacy_TX4_PHY_ANTLAST 0x0300 /* Use last used antenna */
78
79
80
81int b43legacy_generate_txhdr(struct b43legacy_wldev *dev,
82 u8 *txhdr,
83 const unsigned char *fragment_data,
84 unsigned int fragment_len,
85 struct ieee80211_tx_info *info,
86 u16 cookie);
87
88
89/* Transmit Status */
90struct b43legacy_txstatus {
91 u16 cookie; /* The cookie from the txhdr */
92 u16 seq; /* Sequence number */
93 u8 phy_stat; /* PHY TX status */
94 u8 frame_count; /* Frame transmit count */
95 u8 rts_count; /* RTS transmit count */
96 u8 supp_reason; /* Suppression reason */
97 /* flags */
98 u8 pm_indicated;/* PM mode indicated to AP */
99 u8 intermediate;/* Intermediate status notification */
100 u8 for_ampdu; /* Status is for an AMPDU (afterburner) */
101 u8 acked; /* Wireless ACK received */
102};
103
104/* txstatus supp_reason values */
105enum {
106 B43legacy_TXST_SUPP_NONE, /* Not suppressed */
107 B43legacy_TXST_SUPP_PMQ, /* Suppressed due to PMQ entry */
108 B43legacy_TXST_SUPP_FLUSH, /* Suppressed due to flush request */
109 B43legacy_TXST_SUPP_PREV, /* Previous fragment failed */
110 B43legacy_TXST_SUPP_CHAN, /* Channel mismatch */
111 B43legacy_TXST_SUPP_LIFE, /* Lifetime expired */
112 B43legacy_TXST_SUPP_UNDER, /* Buffer underflow */
113 B43legacy_TXST_SUPP_ABNACK, /* Afterburner NACK */
114};
115
116/* Transmit Status as received through DMA/PIO on old chips */
117struct b43legacy_hwtxstatus {
118 PAD_BYTES(4);
119 __le16 cookie;
120 u8 flags;
121 u8 count;
122 PAD_BYTES(2);
123 __le16 seq;
124 u8 phy_stat;
125 PAD_BYTES(1);
126} __packed;
127
128
129/* Receive header for v3 firmware. */
130struct b43legacy_rxhdr_fw3 {
131 __le16 frame_len; /* Frame length */
132 PAD_BYTES(2);
133 __le16 phy_status0; /* PHY RX Status 0 */
134 __u8 jssi; /* PHY RX Status 1: JSSI */
135 __u8 sig_qual; /* PHY RX Status 1: Signal Quality */
136 PAD_BYTES(2); /* PHY RX Status 2 */
137 __le16 phy_status3; /* PHY RX Status 3 */
138 __le16 mac_status; /* MAC RX status */
139 __le16 mac_time;
140 __le16 channel;
141} __packed;
142
143
144/* PHY RX Status 0 */
145#define B43legacy_RX_PHYST0_GAINCTL 0x4000 /* Gain Control */
146#define B43legacy_RX_PHYST0_PLCPHCF 0x0200
147#define B43legacy_RX_PHYST0_PLCPFV 0x0100
148#define B43legacy_RX_PHYST0_SHORTPRMBL 0x0080 /* Recvd with Short Preamble */
149#define B43legacy_RX_PHYST0_LCRS 0x0040
150#define B43legacy_RX_PHYST0_ANT 0x0020 /* Antenna */
151#define B43legacy_RX_PHYST0_UNSRATE 0x0010
152#define B43legacy_RX_PHYST0_CLIP 0x000C
153#define B43legacy_RX_PHYST0_CLIP_SHIFT 2
154#define B43legacy_RX_PHYST0_FTYPE 0x0003 /* Frame type */
155#define B43legacy_RX_PHYST0_CCK 0x0000 /* Frame type: CCK */
156#define B43legacy_RX_PHYST0_OFDM 0x0001 /* Frame type: OFDM */
157#define B43legacy_RX_PHYST0_PRE_N 0x0002 /* Pre-standard N-PHY frame */
158#define B43legacy_RX_PHYST0_STD_N 0x0003 /* Standard N-PHY frame */
159
160/* PHY RX Status 2 */
161#define B43legacy_RX_PHYST2_LNAG 0xC000 /* LNA Gain */
162#define B43legacy_RX_PHYST2_LNAG_SHIFT 14
163#define B43legacy_RX_PHYST2_PNAG 0x3C00 /* PNA Gain */
164#define B43legacy_RX_PHYST2_PNAG_SHIFT 10
165#define B43legacy_RX_PHYST2_FOFF 0x03FF /* F offset */
166
167/* PHY RX Status 3 */
168#define B43legacy_RX_PHYST3_DIGG 0x1800 /* DIG Gain */
169#define B43legacy_RX_PHYST3_DIGG_SHIFT 11
170#define B43legacy_RX_PHYST3_TRSTATE 0x0400 /* TR state */
171
172/* MAC RX Status */
173#define B43legacy_RX_MAC_BEACONSENT 0x00008000 /* Beacon send flag */
174#define B43legacy_RX_MAC_KEYIDX 0x000007E0 /* Key index */
175#define B43legacy_RX_MAC_KEYIDX_SHIFT 5
176#define B43legacy_RX_MAC_DECERR 0x00000010 /* Decrypt error */
177#define B43legacy_RX_MAC_DEC 0x00000008 /* Decryption attempted */
178#define B43legacy_RX_MAC_PADDING 0x00000004 /* Pad bytes present */
179#define B43legacy_RX_MAC_RESP 0x00000002 /* Response frame xmitted */
180#define B43legacy_RX_MAC_FCSERR 0x00000001 /* FCS error */
181
182/* RX channel */
183#define B43legacy_RX_CHAN_GAIN 0xFC00 /* Gain */
184#define B43legacy_RX_CHAN_GAIN_SHIFT 10
185#define B43legacy_RX_CHAN_ID 0x03FC /* Channel ID */
186#define B43legacy_RX_CHAN_ID_SHIFT 2
187#define B43legacy_RX_CHAN_PHYTYPE 0x0003 /* PHY type */
188
189
190
191u8 b43legacy_plcp_get_ratecode_cck(const u8 bitrate);
192u8 b43legacy_plcp_get_ratecode_ofdm(const u8 bitrate);
193
194void b43legacy_generate_plcp_hdr(struct b43legacy_plcp_hdr4 *plcp,
195 const u16 octets, const u8 bitrate);
196
197void b43legacy_rx(struct b43legacy_wldev *dev,
198 struct sk_buff *skb,
199 const void *_rxhdr);
200
201void b43legacy_handle_txstatus(struct b43legacy_wldev *dev,
202 const struct b43legacy_txstatus *status);
203
204void b43legacy_handle_hwtxstatus(struct b43legacy_wldev *dev,
205 const struct b43legacy_hwtxstatus *hw);
206
207void b43legacy_tx_suspend(struct b43legacy_wldev *dev);
208void b43legacy_tx_resume(struct b43legacy_wldev *dev);
209
210
211#define B43legacy_NR_QOSPARMS 22
212enum {
213 B43legacy_QOSPARM_TXOP = 0,
214 B43legacy_QOSPARM_CWMIN,
215 B43legacy_QOSPARM_CWMAX,
216 B43legacy_QOSPARM_CWCUR,
217 B43legacy_QOSPARM_AIFS,
218 B43legacy_QOSPARM_BSLOTS,
219 B43legacy_QOSPARM_REGGAP,
220 B43legacy_QOSPARM_STATUS,
221};
222
223void b43legacy_qos_init(struct b43legacy_wldev *dev);
224
225
226/* Helper functions for converting the key-table index from "firmware-format"
227 * to "raw-format" and back. The firmware API changed for this at some revision.
228 * We need to account for that here. */
229static inline
230int b43legacy_new_kidx_api(struct b43legacy_wldev *dev)
231{
232 /* FIXME: Not sure the change was at rev 351 */
233 return (dev->fw.rev >= 351);
234}
235static inline
236u8 b43legacy_kidx_to_fw(struct b43legacy_wldev *dev, u8 raw_kidx)
237{
238 u8 firmware_kidx;
239 if (b43legacy_new_kidx_api(dev))
240 firmware_kidx = raw_kidx;
241 else {
242 if (raw_kidx >= 4) /* Is per STA key? */
243 firmware_kidx = raw_kidx - 4;
244 else
245 firmware_kidx = raw_kidx; /* TX default key */
246 }
247 return firmware_kidx;
248}
249static inline
250u8 b43legacy_kidx_to_raw(struct b43legacy_wldev *dev, u8 firmware_kidx)
251{
252 u8 raw_kidx;
253 if (b43legacy_new_kidx_api(dev))
254 raw_kidx = firmware_kidx;
255 else
256 /* RX default keys or per STA keys */
257 raw_kidx = firmware_kidx + 4;
258 return raw_kidx;
259}
260
261#endif /* B43legacy_XMIT_H_ */