1// SPDX-License-Identifier: GPL-2.0+
  2/*
  3 * DaVinci MDIO Module driver
  4 *
  5 * Copyright (C) 2010 Texas Instruments.
  6 *
  7 * Shamelessly ripped out of davinci_emac.c, original copyrights follow:
  8 *
  9 * Copyright (C) 2009 Texas Instruments.
 10 *
 11 */
 12#include <linux/module.h>
 13#include <linux/kernel.h>
 14#include <linux/platform_device.h>
 15#include <linux/delay.h>
 16#include <linux/sched.h>
 17#include <linux/slab.h>
 18#include <linux/phy.h>
 19#include <linux/clk.h>
 20#include <linux/err.h>
 21#include <linux/io.h>
 22#include <linux/iopoll.h>
 23#include <linux/pm_runtime.h>
 24#include <linux/davinci_emac.h>
 25#include <linux/of.h>
 26#include <linux/of_device.h>
 27#include <linux/of_mdio.h>
 28#include <linux/pinctrl/consumer.h>
 29
 30/*
 31 * This timeout definition is a worst-case ultra defensive measure against
 32 * unexpected controller lock ups.  Ideally, we should never ever hit this
 33 * scenario in practice.
 34 */
 35#define MDIO_TIMEOUT		100 /* msecs */
 36
 37#define PHY_REG_MASK		0x1f
 38#define PHY_ID_MASK		0x1f
 39
 40#define DEF_OUT_FREQ		2200000		/* 2.2 MHz */
 41
 42struct davinci_mdio_of_param {
 43	int autosuspend_delay_ms;
 44};
 45
 46struct davinci_mdio_regs {
 47	u32	version;
 48	u32	control;
 49#define CONTROL_IDLE		BIT(31)
 50#define CONTROL_ENABLE		BIT(30)
 51#define CONTROL_MAX_DIV		(0xffff)
 52
 53	u32	alive;
 54	u32	link;
 55	u32	linkintraw;
 56	u32	linkintmasked;
 57	u32	__reserved_0[2];
 58	u32	userintraw;
 59	u32	userintmasked;
 60	u32	userintmaskset;
 61	u32	userintmaskclr;
 62	u32	__reserved_1[20];
 63
 64	struct {
 65		u32	access;
 66#define USERACCESS_GO		BIT(31)
 67#define USERACCESS_WRITE	BIT(30)
 68#define USERACCESS_ACK		BIT(29)
 69#define USERACCESS_READ		(0)
 70#define USERACCESS_DATA		(0xffff)
 71
 72		u32	physel;
 73	}	user[0];
 74};
 75
 76static const struct mdio_platform_data default_pdata = {
 77	.bus_freq = DEF_OUT_FREQ,
 78};
 79
 80struct davinci_mdio_data {
 81	struct mdio_platform_data pdata;
 82	struct davinci_mdio_regs __iomem *regs;
 83	struct clk	*clk;
 84	struct device	*dev;
 85	struct mii_bus	*bus;
 86	bool            active_in_suspend;
 87	unsigned long	access_time; /* jiffies */
 88	/* Indicates that driver shouldn't modify phy_mask in case
 89	 * if MDIO bus is registered from DT.
 90	 */
 91	bool		skip_scan;
 92	u32		clk_div;
 93};
 94
 95static void davinci_mdio_init_clk(struct davinci_mdio_data *data)
 96{
 97	u32 mdio_in, div, mdio_out_khz, access_time;
 98
 99	mdio_in = clk_get_rate(data->clk);
100	div = (mdio_in / data->pdata.bus_freq) - 1;
101	if (div > CONTROL_MAX_DIV)
102		div = CONTROL_MAX_DIV;
103
104	data->clk_div = div;
105	/*
106	 * One mdio transaction consists of:
107	 *	32 bits of preamble
108	 *	32 bits of transferred data
109	 *	24 bits of bus yield (not needed unless shared?)
110	 */
111	mdio_out_khz = mdio_in / (1000 * (div + 1));
112	access_time  = (88 * 1000) / mdio_out_khz;
113
114	/*
115	 * In the worst case, we could be kicking off a user-access immediately
116	 * after the mdio bus scan state-machine triggered its own read.  If
117	 * so, our request could get deferred by one access cycle.  We
118	 * defensively allow for 4 access cycles.
119	 */
120	data->access_time = usecs_to_jiffies(access_time * 4);
121	if (!data->access_time)
122		data->access_time = 1;
123}
124
125static void davinci_mdio_enable(struct davinci_mdio_data *data)
126{
127	/* set enable and clock divider */
128	writel(data->clk_div | CONTROL_ENABLE, &data->regs->control);
129}
130
131static int davinci_mdio_reset(struct mii_bus *bus)
132{
133	struct davinci_mdio_data *data = bus->priv;
134	u32 phy_mask, ver;
135	int ret;
136
137	ret = pm_runtime_get_sync(data->dev);
138	if (ret < 0) {
139		pm_runtime_put_noidle(data->dev);
140		return ret;
141	}
142
143	/* wait for scan logic to settle */
144	msleep(PHY_MAX_ADDR * data->access_time);
145
146	/* dump hardware version info */
147	ver = readl(&data->regs->version);
148	dev_info(data->dev,
149		 "davinci mdio revision %d.%d, bus freq %ld\n",
150		 (ver >> 8) & 0xff, ver & 0xff,
151		 data->pdata.bus_freq);
152
153	if (data->skip_scan)
154		goto done;
155
156	/* get phy mask from the alive register */
157	phy_mask = readl(&data->regs->alive);
158	if (phy_mask) {
159		/* restrict mdio bus to live phys only */
160		dev_info(data->dev, "detected phy mask %x\n", ~phy_mask);
161		phy_mask = ~phy_mask;
162	} else {
163		/* desperately scan all phys */
164		dev_warn(data->dev, "no live phy, scanning all\n");
165		phy_mask = 0;
166	}
167	data->bus->phy_mask = phy_mask;
168
169done:
170	pm_runtime_mark_last_busy(data->dev);
171	pm_runtime_put_autosuspend(data->dev);
172
173	return 0;
174}
175
176/* wait until hardware is ready for another user access */
177static inline int wait_for_user_access(struct davinci_mdio_data *data)
178{
179	struct davinci_mdio_regs __iomem *regs = data->regs;
180	unsigned long timeout = jiffies + msecs_to_jiffies(MDIO_TIMEOUT);
181	u32 reg;
182
183	while (time_after(timeout, jiffies)) {
184		reg = readl(&regs->user[0].access);
185		if ((reg & USERACCESS_GO) == 0)
186			return 0;
187
188		reg = readl(&regs->control);
189		if ((reg & CONTROL_IDLE) == 0) {
190			usleep_range(100, 200);
191			continue;
192		}
193
194		/*
195		 * An emac soft_reset may have clobbered the mdio controller's
196		 * state machine.  We need to reset and retry the current
197		 * operation
198		 */
199		dev_warn(data->dev, "resetting idled controller\n");
200		davinci_mdio_enable(data);
201		return -EAGAIN;
202	}
203
204	reg = readl(&regs->user[0].access);
205	if ((reg & USERACCESS_GO) == 0)
206		return 0;
207
208	dev_err(data->dev, "timed out waiting for user access\n");
209	return -ETIMEDOUT;
210}
211
212/* wait until hardware state machine is idle */
213static inline int wait_for_idle(struct davinci_mdio_data *data)
214{
215	struct davinci_mdio_regs __iomem *regs = data->regs;
216	u32 val, ret;
217
218	ret = readl_poll_timeout(&regs->control, val, val & CONTROL_IDLE,
219				 0, MDIO_TIMEOUT * 1000);
220	if (ret)
221		dev_err(data->dev, "timed out waiting for idle\n");
222
223	return ret;
224}
225
226static int davinci_mdio_read(struct mii_bus *bus, int phy_id, int phy_reg)
227{
228	struct davinci_mdio_data *data = bus->priv;
229	u32 reg;
230	int ret;
231
232	if (phy_reg & ~PHY_REG_MASK || phy_id & ~PHY_ID_MASK)
233		return -EINVAL;
234
235	ret = pm_runtime_get_sync(data->dev);
236	if (ret < 0) {
237		pm_runtime_put_noidle(data->dev);
238		return ret;
239	}
240
241	reg = (USERACCESS_GO | USERACCESS_READ | (phy_reg << 21) |
242	       (phy_id << 16));
243
244	while (1) {
245		ret = wait_for_user_access(data);
246		if (ret == -EAGAIN)
247			continue;
248		if (ret < 0)
249			break;
250
251		writel(reg, &data->regs->user[0].access);
252
253		ret = wait_for_user_access(data);
254		if (ret == -EAGAIN)
255			continue;
256		if (ret < 0)
257			break;
258
259		reg = readl(&data->regs->user[0].access);
260		ret = (reg & USERACCESS_ACK) ? (reg & USERACCESS_DATA) : -EIO;
261		break;
262	}
263
264	pm_runtime_mark_last_busy(data->dev);
265	pm_runtime_put_autosuspend(data->dev);
266	return ret;
267}
268
269static int davinci_mdio_write(struct mii_bus *bus, int phy_id,
270			      int phy_reg, u16 phy_data)
271{
272	struct davinci_mdio_data *data = bus->priv;
273	u32 reg;
274	int ret;
275
276	if (phy_reg & ~PHY_REG_MASK || phy_id & ~PHY_ID_MASK)
277		return -EINVAL;
278
279	ret = pm_runtime_get_sync(data->dev);
280	if (ret < 0) {
281		pm_runtime_put_noidle(data->dev);
282		return ret;
283	}
284
285	reg = (USERACCESS_GO | USERACCESS_WRITE | (phy_reg << 21) |
286		   (phy_id << 16) | (phy_data & USERACCESS_DATA));
287
288	while (1) {
289		ret = wait_for_user_access(data);
290		if (ret == -EAGAIN)
291			continue;
292		if (ret < 0)
293			break;
294
295		writel(reg, &data->regs->user[0].access);
296
297		ret = wait_for_user_access(data);
298		if (ret == -EAGAIN)
299			continue;
300		break;
301	}
302
303	pm_runtime_mark_last_busy(data->dev);
304	pm_runtime_put_autosuspend(data->dev);
305
306	return ret;
307}
308
309static int davinci_mdio_probe_dt(struct mdio_platform_data *data,
310			 struct platform_device *pdev)
311{
312	struct device_node *node = pdev->dev.of_node;
313	u32 prop;
314
315	if (!node)
316		return -EINVAL;
317
318	if (of_property_read_u32(node, "bus_freq", &prop)) {
319		dev_err(&pdev->dev, "Missing bus_freq property in the DT.\n");
320		return -EINVAL;
321	}
322	data->bus_freq = prop;
323
324	return 0;
325}
326
327#if IS_ENABLED(CONFIG_OF)
328static const struct davinci_mdio_of_param of_cpsw_mdio_data = {
329	.autosuspend_delay_ms = 100,
330};
331
332static const struct of_device_id davinci_mdio_of_mtable[] = {
333	{ .compatible = "ti,davinci_mdio", },
334	{ .compatible = "ti,cpsw-mdio", .data = &of_cpsw_mdio_data},
335	{ /* sentinel */ },
336};
337MODULE_DEVICE_TABLE(of, davinci_mdio_of_mtable);
338#endif
339
340static int davinci_mdio_probe(struct platform_device *pdev)
341{
342	struct mdio_platform_data *pdata = dev_get_platdata(&pdev->dev);
343	struct device *dev = &pdev->dev;
344	struct davinci_mdio_data *data;
345	struct resource *res;
346	struct phy_device *phy;
347	int ret, addr;
348	int autosuspend_delay_ms = -1;
349
350	data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
351	if (!data)
352		return -ENOMEM;
353
354	data->bus = devm_mdiobus_alloc(dev);
355	if (!data->bus) {
356		dev_err(dev, "failed to alloc mii bus\n");
357		return -ENOMEM;
358	}
359
360	if (IS_ENABLED(CONFIG_OF) && dev->of_node) {
361		const struct of_device_id	*of_id;
362
363		ret = davinci_mdio_probe_dt(&data->pdata, pdev);
364		if (ret)
365			return ret;
366		snprintf(data->bus->id, MII_BUS_ID_SIZE, "%s", pdev->name);
367
368		of_id = of_match_device(davinci_mdio_of_mtable, &pdev->dev);
369		if (of_id) {
370			const struct davinci_mdio_of_param *of_mdio_data;
371
372			of_mdio_data = of_id->data;
373			if (of_mdio_data)
374				autosuspend_delay_ms =
375					of_mdio_data->autosuspend_delay_ms;
376		}
377	} else {
378		data->pdata = pdata ? (*pdata) : default_pdata;
379		snprintf(data->bus->id, MII_BUS_ID_SIZE, "%s-%x",
380			 pdev->name, pdev->id);
381	}
382
383	data->bus->name		= dev_name(dev);
384	data->bus->read		= davinci_mdio_read,
385	data->bus->write	= davinci_mdio_write,
386	data->bus->reset	= davinci_mdio_reset,
387	data->bus->parent	= dev;
388	data->bus->priv		= data;
389
390	data->clk = devm_clk_get(dev, "fck");
391	if (IS_ERR(data->clk)) {
392		dev_err(dev, "failed to get device clock\n");
393		return PTR_ERR(data->clk);
394	}
395
396	dev_set_drvdata(dev, data);
397	data->dev = dev;
398
399	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
400	data->regs = devm_ioremap(dev, res->start, resource_size(res));
401	if (!data->regs)
402		return -ENOMEM;
403
404	davinci_mdio_init_clk(data);
405
406	pm_runtime_set_autosuspend_delay(&pdev->dev, autosuspend_delay_ms);
407	pm_runtime_use_autosuspend(&pdev->dev);
408	pm_runtime_enable(&pdev->dev);
409
410	/* register the mii bus
411	 * Create PHYs from DT only in case if PHY child nodes are explicitly
412	 * defined to support backward compatibility with DTs which assume that
413	 * Davinci MDIO will always scan the bus for PHYs detection.
414	 */
415	if (dev->of_node && of_get_child_count(dev->of_node))
416		data->skip_scan = true;
417
418	ret = of_mdiobus_register(data->bus, dev->of_node);
419	if (ret)
420		goto bail_out;
421
422	/* scan and dump the bus */
423	for (addr = 0; addr < PHY_MAX_ADDR; addr++) {
424		phy = mdiobus_get_phy(data->bus, addr);
425		if (phy) {
426			dev_info(dev, "phy[%d]: device %s, driver %s\n",
427				 phy->mdio.addr, phydev_name(phy),
428				 phy->drv ? phy->drv->name : "unknown");
429		}
430	}
431
432	return 0;
433
434bail_out:
435	pm_runtime_dont_use_autosuspend(&pdev->dev);
436	pm_runtime_disable(&pdev->dev);
437	return ret;
438}
439
440static int davinci_mdio_remove(struct platform_device *pdev)
441{
442	struct davinci_mdio_data *data = platform_get_drvdata(pdev);
443
444	if (data->bus)
445		mdiobus_unregister(data->bus);
446
447	pm_runtime_dont_use_autosuspend(&pdev->dev);
448	pm_runtime_disable(&pdev->dev);
449
450	return 0;
451}
452
453#ifdef CONFIG_PM
454static int davinci_mdio_runtime_suspend(struct device *dev)
455{
456	struct davinci_mdio_data *data = dev_get_drvdata(dev);
457	u32 ctrl;
458
459	/* shutdown the scan state machine */
460	ctrl = readl(&data->regs->control);
461	ctrl &= ~CONTROL_ENABLE;
462	writel(ctrl, &data->regs->control);
463	wait_for_idle(data);
464
465	return 0;
466}
467
468static int davinci_mdio_runtime_resume(struct device *dev)
469{
470	struct davinci_mdio_data *data = dev_get_drvdata(dev);
471
472	davinci_mdio_enable(data);
473	return 0;
474}
475#endif
476
477#ifdef CONFIG_PM_SLEEP
478static int davinci_mdio_suspend(struct device *dev)
479{
480	struct davinci_mdio_data *data = dev_get_drvdata(dev);
481	int ret = 0;
482
483	data->active_in_suspend = !pm_runtime_status_suspended(dev);
484	if (data->active_in_suspend)
485		ret = pm_runtime_force_suspend(dev);
486	if (ret < 0)
487		return ret;
488
489	/* Select sleep pin state */
490	pinctrl_pm_select_sleep_state(dev);
491
492	return 0;
493}
494
495static int davinci_mdio_resume(struct device *dev)
496{
497	struct davinci_mdio_data *data = dev_get_drvdata(dev);
498
499	/* Select default pin state */
500	pinctrl_pm_select_default_state(dev);
501
502	if (data->active_in_suspend)
503		pm_runtime_force_resume(dev);
504
505	return 0;
506}
507#endif
508
509static const struct dev_pm_ops davinci_mdio_pm_ops = {
510	SET_RUNTIME_PM_OPS(davinci_mdio_runtime_suspend,
511			   davinci_mdio_runtime_resume, NULL)
512	SET_LATE_SYSTEM_SLEEP_PM_OPS(davinci_mdio_suspend, davinci_mdio_resume)
513};
514
515static struct platform_driver davinci_mdio_driver = {
516	.driver = {
517		.name	 = "davinci_mdio",
518		.pm	 = &davinci_mdio_pm_ops,
519		.of_match_table = of_match_ptr(davinci_mdio_of_mtable),
520	},
521	.probe = davinci_mdio_probe,
522	.remove = davinci_mdio_remove,
523};
524
525static int __init davinci_mdio_init(void)
526{
527	return platform_driver_register(&davinci_mdio_driver);
528}
529device_initcall(davinci_mdio_init);
530
531static void __exit davinci_mdio_exit(void)
532{
533	platform_driver_unregister(&davinci_mdio_driver);
534}
535module_exit(davinci_mdio_exit);
536
537MODULE_LICENSE("GPL");
538MODULE_DESCRIPTION("DaVinci MDIO driver");