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1// SPDX-License-Identifier: GPL-2.0-only
2/****************************************************************************
3 * Driver for Solarflare network controllers and boards
4 * Copyright 2005-2006 Fen Systems Ltd.
5 * Copyright 2006-2013 Solarflare Communications Inc.
6 */
7
8#include <linux/bitops.h>
9#include <linux/delay.h>
10#include <linux/interrupt.h>
11#include <linux/pci.h>
12#include <linux/module.h>
13#include <linux/seq_file.h>
14#include <linux/cpu_rmap.h>
15#include "net_driver.h"
16#include "bitfield.h"
17#include "efx.h"
18#include "nic.h"
19#include "ef10_regs.h"
20#include "farch_regs.h"
21#include "io.h"
22#include "workarounds.h"
23
24/**************************************************************************
25 *
26 * Generic buffer handling
27 * These buffers are used for interrupt status, MAC stats, etc.
28 *
29 **************************************************************************/
30
31int efx_nic_alloc_buffer(struct efx_nic *efx, struct efx_buffer *buffer,
32 unsigned int len, gfp_t gfp_flags)
33{
34 buffer->addr = dma_alloc_coherent(&efx->pci_dev->dev, len,
35 &buffer->dma_addr, gfp_flags);
36 if (!buffer->addr)
37 return -ENOMEM;
38 buffer->len = len;
39 return 0;
40}
41
42void efx_nic_free_buffer(struct efx_nic *efx, struct efx_buffer *buffer)
43{
44 if (buffer->addr) {
45 dma_free_coherent(&efx->pci_dev->dev, buffer->len,
46 buffer->addr, buffer->dma_addr);
47 buffer->addr = NULL;
48 }
49}
50
51/* Check whether an event is present in the eventq at the current
52 * read pointer. Only useful for self-test.
53 */
54bool efx_nic_event_present(struct efx_channel *channel)
55{
56 return efx_event_present(efx_event(channel, channel->eventq_read_ptr));
57}
58
59void efx_nic_event_test_start(struct efx_channel *channel)
60{
61 channel->event_test_cpu = -1;
62 smp_wmb();
63 channel->efx->type->ev_test_generate(channel);
64}
65
66int efx_nic_irq_test_start(struct efx_nic *efx)
67{
68 efx->last_irq_cpu = -1;
69 smp_wmb();
70 return efx->type->irq_test_generate(efx);
71}
72
73/* Hook interrupt handler(s)
74 * Try MSI and then legacy interrupts.
75 */
76int efx_nic_init_interrupt(struct efx_nic *efx)
77{
78 struct efx_channel *channel;
79 unsigned int n_irqs;
80 int rc;
81
82 if (!EFX_INT_MODE_USE_MSI(efx)) {
83 rc = request_irq(efx->legacy_irq,
84 efx->type->irq_handle_legacy, IRQF_SHARED,
85 efx->name, efx);
86 if (rc) {
87 netif_err(efx, drv, efx->net_dev,
88 "failed to hook legacy IRQ %d\n",
89 efx->pci_dev->irq);
90 goto fail1;
91 }
92 return 0;
93 }
94
95#ifdef CONFIG_RFS_ACCEL
96 if (efx->interrupt_mode == EFX_INT_MODE_MSIX) {
97 efx->net_dev->rx_cpu_rmap =
98 alloc_irq_cpu_rmap(efx->n_rx_channels);
99 if (!efx->net_dev->rx_cpu_rmap) {
100 rc = -ENOMEM;
101 goto fail1;
102 }
103 }
104#endif
105
106 /* Hook MSI or MSI-X interrupt */
107 n_irqs = 0;
108 efx_for_each_channel(channel, efx) {
109 rc = request_irq(channel->irq, efx->type->irq_handle_msi,
110 IRQF_PROBE_SHARED, /* Not shared */
111 efx->msi_context[channel->channel].name,
112 &efx->msi_context[channel->channel]);
113 if (rc) {
114 netif_err(efx, drv, efx->net_dev,
115 "failed to hook IRQ %d\n", channel->irq);
116 goto fail2;
117 }
118 ++n_irqs;
119
120#ifdef CONFIG_RFS_ACCEL
121 if (efx->interrupt_mode == EFX_INT_MODE_MSIX &&
122 channel->channel < efx->n_rx_channels) {
123 rc = irq_cpu_rmap_add(efx->net_dev->rx_cpu_rmap,
124 channel->irq);
125 if (rc)
126 goto fail2;
127 }
128#endif
129 }
130
131 return 0;
132
133 fail2:
134#ifdef CONFIG_RFS_ACCEL
135 free_irq_cpu_rmap(efx->net_dev->rx_cpu_rmap);
136 efx->net_dev->rx_cpu_rmap = NULL;
137#endif
138 efx_for_each_channel(channel, efx) {
139 if (n_irqs-- == 0)
140 break;
141 free_irq(channel->irq, &efx->msi_context[channel->channel]);
142 }
143 fail1:
144 return rc;
145}
146
147void efx_nic_fini_interrupt(struct efx_nic *efx)
148{
149 struct efx_channel *channel;
150
151#ifdef CONFIG_RFS_ACCEL
152 free_irq_cpu_rmap(efx->net_dev->rx_cpu_rmap);
153 efx->net_dev->rx_cpu_rmap = NULL;
154#endif
155
156 if (EFX_INT_MODE_USE_MSI(efx)) {
157 /* Disable MSI/MSI-X interrupts */
158 efx_for_each_channel(channel, efx)
159 free_irq(channel->irq,
160 &efx->msi_context[channel->channel]);
161 } else {
162 /* Disable legacy interrupt */
163 free_irq(efx->legacy_irq, efx);
164 }
165}
166
167/* Register dump */
168
169#define REGISTER_REVISION_FA 1
170#define REGISTER_REVISION_FB 2
171#define REGISTER_REVISION_FC 3
172#define REGISTER_REVISION_FZ 3 /* last Falcon arch revision */
173#define REGISTER_REVISION_ED 4
174#define REGISTER_REVISION_EZ 4 /* latest EF10 revision */
175
176struct efx_nic_reg {
177 u32 offset:24;
178 u32 min_revision:3, max_revision:3;
179};
180
181#define REGISTER(name, arch, min_rev, max_rev) { \
182 arch ## R_ ## min_rev ## max_rev ## _ ## name, \
183 REGISTER_REVISION_ ## arch ## min_rev, \
184 REGISTER_REVISION_ ## arch ## max_rev \
185}
186#define REGISTER_AA(name) REGISTER(name, F, A, A)
187#define REGISTER_AB(name) REGISTER(name, F, A, B)
188#define REGISTER_AZ(name) REGISTER(name, F, A, Z)
189#define REGISTER_BB(name) REGISTER(name, F, B, B)
190#define REGISTER_BZ(name) REGISTER(name, F, B, Z)
191#define REGISTER_CZ(name) REGISTER(name, F, C, Z)
192#define REGISTER_DZ(name) REGISTER(name, E, D, Z)
193
194static const struct efx_nic_reg efx_nic_regs[] = {
195 REGISTER_AZ(ADR_REGION),
196 REGISTER_AZ(INT_EN_KER),
197 REGISTER_BZ(INT_EN_CHAR),
198 REGISTER_AZ(INT_ADR_KER),
199 REGISTER_BZ(INT_ADR_CHAR),
200 /* INT_ACK_KER is WO */
201 /* INT_ISR0 is RC */
202 REGISTER_AZ(HW_INIT),
203 REGISTER_CZ(USR_EV_CFG),
204 REGISTER_AB(EE_SPI_HCMD),
205 REGISTER_AB(EE_SPI_HADR),
206 REGISTER_AB(EE_SPI_HDATA),
207 REGISTER_AB(EE_BASE_PAGE),
208 REGISTER_AB(EE_VPD_CFG0),
209 /* EE_VPD_SW_CNTL and EE_VPD_SW_DATA are not used */
210 /* PMBX_DBG_IADDR and PBMX_DBG_IDATA are indirect */
211 /* PCIE_CORE_INDIRECT is indirect */
212 REGISTER_AB(NIC_STAT),
213 REGISTER_AB(GPIO_CTL),
214 REGISTER_AB(GLB_CTL),
215 /* FATAL_INTR_KER and FATAL_INTR_CHAR are partly RC */
216 REGISTER_BZ(DP_CTRL),
217 REGISTER_AZ(MEM_STAT),
218 REGISTER_AZ(CS_DEBUG),
219 REGISTER_AZ(ALTERA_BUILD),
220 REGISTER_AZ(CSR_SPARE),
221 REGISTER_AB(PCIE_SD_CTL0123),
222 REGISTER_AB(PCIE_SD_CTL45),
223 REGISTER_AB(PCIE_PCS_CTL_STAT),
224 /* DEBUG_DATA_OUT is not used */
225 /* DRV_EV is WO */
226 REGISTER_AZ(EVQ_CTL),
227 REGISTER_AZ(EVQ_CNT1),
228 REGISTER_AZ(EVQ_CNT2),
229 REGISTER_AZ(BUF_TBL_CFG),
230 REGISTER_AZ(SRM_RX_DC_CFG),
231 REGISTER_AZ(SRM_TX_DC_CFG),
232 REGISTER_AZ(SRM_CFG),
233 /* BUF_TBL_UPD is WO */
234 REGISTER_AZ(SRM_UPD_EVQ),
235 REGISTER_AZ(SRAM_PARITY),
236 REGISTER_AZ(RX_CFG),
237 REGISTER_BZ(RX_FILTER_CTL),
238 /* RX_FLUSH_DESCQ is WO */
239 REGISTER_AZ(RX_DC_CFG),
240 REGISTER_AZ(RX_DC_PF_WM),
241 REGISTER_BZ(RX_RSS_TKEY),
242 /* RX_NODESC_DROP is RC */
243 REGISTER_AA(RX_SELF_RST),
244 /* RX_DEBUG, RX_PUSH_DROP are not used */
245 REGISTER_CZ(RX_RSS_IPV6_REG1),
246 REGISTER_CZ(RX_RSS_IPV6_REG2),
247 REGISTER_CZ(RX_RSS_IPV6_REG3),
248 /* TX_FLUSH_DESCQ is WO */
249 REGISTER_AZ(TX_DC_CFG),
250 REGISTER_AA(TX_CHKSM_CFG),
251 REGISTER_AZ(TX_CFG),
252 /* TX_PUSH_DROP is not used */
253 REGISTER_AZ(TX_RESERVED),
254 REGISTER_BZ(TX_PACE),
255 /* TX_PACE_DROP_QID is RC */
256 REGISTER_BB(TX_VLAN),
257 REGISTER_BZ(TX_IPFIL_PORTEN),
258 REGISTER_AB(MD_TXD),
259 REGISTER_AB(MD_RXD),
260 REGISTER_AB(MD_CS),
261 REGISTER_AB(MD_PHY_ADR),
262 REGISTER_AB(MD_ID),
263 /* MD_STAT is RC */
264 REGISTER_AB(MAC_STAT_DMA),
265 REGISTER_AB(MAC_CTRL),
266 REGISTER_BB(GEN_MODE),
267 REGISTER_AB(MAC_MC_HASH_REG0),
268 REGISTER_AB(MAC_MC_HASH_REG1),
269 REGISTER_AB(GM_CFG1),
270 REGISTER_AB(GM_CFG2),
271 /* GM_IPG and GM_HD are not used */
272 REGISTER_AB(GM_MAX_FLEN),
273 /* GM_TEST is not used */
274 REGISTER_AB(GM_ADR1),
275 REGISTER_AB(GM_ADR2),
276 REGISTER_AB(GMF_CFG0),
277 REGISTER_AB(GMF_CFG1),
278 REGISTER_AB(GMF_CFG2),
279 REGISTER_AB(GMF_CFG3),
280 REGISTER_AB(GMF_CFG4),
281 REGISTER_AB(GMF_CFG5),
282 REGISTER_BB(TX_SRC_MAC_CTL),
283 REGISTER_AB(XM_ADR_LO),
284 REGISTER_AB(XM_ADR_HI),
285 REGISTER_AB(XM_GLB_CFG),
286 REGISTER_AB(XM_TX_CFG),
287 REGISTER_AB(XM_RX_CFG),
288 REGISTER_AB(XM_MGT_INT_MASK),
289 REGISTER_AB(XM_FC),
290 REGISTER_AB(XM_PAUSE_TIME),
291 REGISTER_AB(XM_TX_PARAM),
292 REGISTER_AB(XM_RX_PARAM),
293 /* XM_MGT_INT_MSK (note no 'A') is RC */
294 REGISTER_AB(XX_PWR_RST),
295 REGISTER_AB(XX_SD_CTL),
296 REGISTER_AB(XX_TXDRV_CTL),
297 /* XX_PRBS_CTL, XX_PRBS_CHK and XX_PRBS_ERR are not used */
298 /* XX_CORE_STAT is partly RC */
299 REGISTER_DZ(BIU_HW_REV_ID),
300 REGISTER_DZ(MC_DB_LWRD),
301 REGISTER_DZ(MC_DB_HWRD),
302};
303
304struct efx_nic_reg_table {
305 u32 offset:24;
306 u32 min_revision:3, max_revision:3;
307 u32 step:6, rows:21;
308};
309
310#define REGISTER_TABLE_DIMENSIONS(_, offset, arch, min_rev, max_rev, step, rows) { \
311 offset, \
312 REGISTER_REVISION_ ## arch ## min_rev, \
313 REGISTER_REVISION_ ## arch ## max_rev, \
314 step, rows \
315}
316#define REGISTER_TABLE(name, arch, min_rev, max_rev) \
317 REGISTER_TABLE_DIMENSIONS( \
318 name, arch ## R_ ## min_rev ## max_rev ## _ ## name, \
319 arch, min_rev, max_rev, \
320 arch ## R_ ## min_rev ## max_rev ## _ ## name ## _STEP, \
321 arch ## R_ ## min_rev ## max_rev ## _ ## name ## _ROWS)
322#define REGISTER_TABLE_AA(name) REGISTER_TABLE(name, F, A, A)
323#define REGISTER_TABLE_AZ(name) REGISTER_TABLE(name, F, A, Z)
324#define REGISTER_TABLE_BB(name) REGISTER_TABLE(name, F, B, B)
325#define REGISTER_TABLE_BZ(name) REGISTER_TABLE(name, F, B, Z)
326#define REGISTER_TABLE_BB_CZ(name) \
327 REGISTER_TABLE_DIMENSIONS(name, FR_BZ_ ## name, F, B, B, \
328 FR_BZ_ ## name ## _STEP, \
329 FR_BB_ ## name ## _ROWS), \
330 REGISTER_TABLE_DIMENSIONS(name, FR_BZ_ ## name, F, C, Z, \
331 FR_BZ_ ## name ## _STEP, \
332 FR_CZ_ ## name ## _ROWS)
333#define REGISTER_TABLE_CZ(name) REGISTER_TABLE(name, F, C, Z)
334#define REGISTER_TABLE_DZ(name) REGISTER_TABLE(name, E, D, Z)
335
336static const struct efx_nic_reg_table efx_nic_reg_tables[] = {
337 /* DRIVER is not used */
338 /* EVQ_RPTR, TIMER_COMMAND, USR_EV and {RX,TX}_DESC_UPD are WO */
339 REGISTER_TABLE_BB(TX_IPFIL_TBL),
340 REGISTER_TABLE_BB(TX_SRC_MAC_TBL),
341 REGISTER_TABLE_AA(RX_DESC_PTR_TBL_KER),
342 REGISTER_TABLE_BB_CZ(RX_DESC_PTR_TBL),
343 REGISTER_TABLE_AA(TX_DESC_PTR_TBL_KER),
344 REGISTER_TABLE_BB_CZ(TX_DESC_PTR_TBL),
345 REGISTER_TABLE_AA(EVQ_PTR_TBL_KER),
346 REGISTER_TABLE_BB_CZ(EVQ_PTR_TBL),
347 /* We can't reasonably read all of the buffer table (up to 8MB!).
348 * However this driver will only use a few entries. Reading
349 * 1K entries allows for some expansion of queue count and
350 * size before we need to change the version. */
351 REGISTER_TABLE_DIMENSIONS(BUF_FULL_TBL_KER, FR_AA_BUF_FULL_TBL_KER,
352 F, A, A, 8, 1024),
353 REGISTER_TABLE_DIMENSIONS(BUF_FULL_TBL, FR_BZ_BUF_FULL_TBL,
354 F, B, Z, 8, 1024),
355 REGISTER_TABLE_CZ(RX_MAC_FILTER_TBL0),
356 REGISTER_TABLE_BB_CZ(TIMER_TBL),
357 REGISTER_TABLE_BB_CZ(TX_PACE_TBL),
358 REGISTER_TABLE_BZ(RX_INDIRECTION_TBL),
359 /* TX_FILTER_TBL0 is huge and not used by this driver */
360 REGISTER_TABLE_CZ(TX_MAC_FILTER_TBL0),
361 REGISTER_TABLE_CZ(MC_TREG_SMEM),
362 /* MSIX_PBA_TABLE is not mapped */
363 /* SRM_DBG is not mapped (and is redundant with BUF_FLL_TBL) */
364 REGISTER_TABLE_BZ(RX_FILTER_TBL0),
365 REGISTER_TABLE_DZ(BIU_MC_SFT_STATUS),
366};
367
368size_t efx_nic_get_regs_len(struct efx_nic *efx)
369{
370 const struct efx_nic_reg *reg;
371 const struct efx_nic_reg_table *table;
372 size_t len = 0;
373
374 for (reg = efx_nic_regs;
375 reg < efx_nic_regs + ARRAY_SIZE(efx_nic_regs);
376 reg++)
377 if (efx->type->revision >= reg->min_revision &&
378 efx->type->revision <= reg->max_revision)
379 len += sizeof(efx_oword_t);
380
381 for (table = efx_nic_reg_tables;
382 table < efx_nic_reg_tables + ARRAY_SIZE(efx_nic_reg_tables);
383 table++)
384 if (efx->type->revision >= table->min_revision &&
385 efx->type->revision <= table->max_revision)
386 len += table->rows * min_t(size_t, table->step, 16);
387
388 return len;
389}
390
391void efx_nic_get_regs(struct efx_nic *efx, void *buf)
392{
393 const struct efx_nic_reg *reg;
394 const struct efx_nic_reg_table *table;
395
396 for (reg = efx_nic_regs;
397 reg < efx_nic_regs + ARRAY_SIZE(efx_nic_regs);
398 reg++) {
399 if (efx->type->revision >= reg->min_revision &&
400 efx->type->revision <= reg->max_revision) {
401 efx_reado(efx, (efx_oword_t *)buf, reg->offset);
402 buf += sizeof(efx_oword_t);
403 }
404 }
405
406 for (table = efx_nic_reg_tables;
407 table < efx_nic_reg_tables + ARRAY_SIZE(efx_nic_reg_tables);
408 table++) {
409 size_t size, i;
410
411 if (!(efx->type->revision >= table->min_revision &&
412 efx->type->revision <= table->max_revision))
413 continue;
414
415 size = min_t(size_t, table->step, 16);
416
417 for (i = 0; i < table->rows; i++) {
418 switch (table->step) {
419 case 4: /* 32-bit SRAM */
420 efx_readd(efx, buf, table->offset + 4 * i);
421 break;
422 case 8: /* 64-bit SRAM */
423 efx_sram_readq(efx,
424 efx->membase + table->offset,
425 buf, i);
426 break;
427 case 16: /* 128-bit-readable register */
428 efx_reado_table(efx, buf, table->offset, i);
429 break;
430 case 32: /* 128-bit register, interleaved */
431 efx_reado_table(efx, buf, table->offset, 2 * i);
432 break;
433 default:
434 WARN_ON(1);
435 return;
436 }
437 buf += size;
438 }
439 }
440}
441
442/**
443 * efx_nic_describe_stats - Describe supported statistics for ethtool
444 * @desc: Array of &struct efx_hw_stat_desc describing the statistics
445 * @count: Length of the @desc array
446 * @mask: Bitmask of which elements of @desc are enabled
447 * @names: Buffer to copy names to, or %NULL. The names are copied
448 * starting at intervals of %ETH_GSTRING_LEN bytes.
449 *
450 * Returns the number of visible statistics, i.e. the number of set
451 * bits in the first @count bits of @mask for which a name is defined.
452 */
453size_t efx_nic_describe_stats(const struct efx_hw_stat_desc *desc, size_t count,
454 const unsigned long *mask, u8 *names)
455{
456 size_t visible = 0;
457 size_t index;
458
459 for_each_set_bit(index, mask, count) {
460 if (desc[index].name) {
461 if (names) {
462 strlcpy(names, desc[index].name,
463 ETH_GSTRING_LEN);
464 names += ETH_GSTRING_LEN;
465 }
466 ++visible;
467 }
468 }
469
470 return visible;
471}
472
473/**
474 * efx_nic_update_stats - Convert statistics DMA buffer to array of u64
475 * @desc: Array of &struct efx_hw_stat_desc describing the DMA buffer
476 * layout. DMA widths of 0, 16, 32 and 64 are supported; where
477 * the width is specified as 0 the corresponding element of
478 * @stats is not updated.
479 * @count: Length of the @desc array
480 * @mask: Bitmask of which elements of @desc are enabled
481 * @stats: Buffer to update with the converted statistics. The length
482 * of this array must be at least @count.
483 * @dma_buf: DMA buffer containing hardware statistics
484 * @accumulate: If set, the converted values will be added rather than
485 * directly stored to the corresponding elements of @stats
486 */
487void efx_nic_update_stats(const struct efx_hw_stat_desc *desc, size_t count,
488 const unsigned long *mask,
489 u64 *stats, const void *dma_buf, bool accumulate)
490{
491 size_t index;
492
493 for_each_set_bit(index, mask, count) {
494 if (desc[index].dma_width) {
495 const void *addr = dma_buf + desc[index].offset;
496 u64 val;
497
498 switch (desc[index].dma_width) {
499 case 16:
500 val = le16_to_cpup((__le16 *)addr);
501 break;
502 case 32:
503 val = le32_to_cpup((__le32 *)addr);
504 break;
505 case 64:
506 val = le64_to_cpup((__le64 *)addr);
507 break;
508 default:
509 WARN_ON(1);
510 val = 0;
511 break;
512 }
513
514 if (accumulate)
515 stats[index] += val;
516 else
517 stats[index] = val;
518 }
519 }
520}
521
522void efx_nic_fix_nodesc_drop_stat(struct efx_nic *efx, u64 *rx_nodesc_drops)
523{
524 /* if down, or this is the first update after coming up */
525 if (!(efx->net_dev->flags & IFF_UP) || !efx->rx_nodesc_drops_prev_state)
526 efx->rx_nodesc_drops_while_down +=
527 *rx_nodesc_drops - efx->rx_nodesc_drops_total;
528 efx->rx_nodesc_drops_total = *rx_nodesc_drops;
529 efx->rx_nodesc_drops_prev_state = !!(efx->net_dev->flags & IFF_UP);
530 *rx_nodesc_drops -= efx->rx_nodesc_drops_while_down;
531}