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1/* SPDX-License-Identifier: GPL-2.0-only */
2/*
3 *
4 * Copyright (C) 2009-2016 John Crispin <blogic@openwrt.org>
5 * Copyright (C) 2009-2016 Felix Fietkau <nbd@openwrt.org>
6 * Copyright (C) 2013-2016 Michael Lee <igvtee@gmail.com>
7 */
8
9#ifndef MTK_ETH_H
10#define MTK_ETH_H
11
12#include <linux/dma-mapping.h>
13#include <linux/netdevice.h>
14#include <linux/of_net.h>
15#include <linux/u64_stats_sync.h>
16#include <linux/refcount.h>
17#include <linux/phylink.h>
18
19#define MTK_QDMA_PAGE_SIZE 2048
20#define MTK_MAX_RX_LENGTH 1536
21#define MTK_TX_DMA_BUF_LEN 0x3fff
22#define MTK_DMA_SIZE 256
23#define MTK_NAPI_WEIGHT 64
24#define MTK_MAC_COUNT 2
25#define MTK_RX_ETH_HLEN (VLAN_ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN)
26#define MTK_RX_HLEN (NET_SKB_PAD + MTK_RX_ETH_HLEN + NET_IP_ALIGN)
27#define MTK_DMA_DUMMY_DESC 0xffffffff
28#define MTK_DEFAULT_MSG_ENABLE (NETIF_MSG_DRV | \
29 NETIF_MSG_PROBE | \
30 NETIF_MSG_LINK | \
31 NETIF_MSG_TIMER | \
32 NETIF_MSG_IFDOWN | \
33 NETIF_MSG_IFUP | \
34 NETIF_MSG_RX_ERR | \
35 NETIF_MSG_TX_ERR)
36#define MTK_HW_FEATURES (NETIF_F_IP_CSUM | \
37 NETIF_F_RXCSUM | \
38 NETIF_F_HW_VLAN_CTAG_TX | \
39 NETIF_F_HW_VLAN_CTAG_RX | \
40 NETIF_F_SG | NETIF_F_TSO | \
41 NETIF_F_TSO6 | \
42 NETIF_F_IPV6_CSUM)
43#define MTK_HW_FEATURES_MT7628 (NETIF_F_SG | NETIF_F_RXCSUM)
44#define NEXT_DESP_IDX(X, Y) (((X) + 1) & ((Y) - 1))
45
46#define MTK_MAX_RX_RING_NUM 4
47#define MTK_HW_LRO_DMA_SIZE 8
48
49#define MTK_MAX_LRO_RX_LENGTH (4096 * 3)
50#define MTK_MAX_LRO_IP_CNT 2
51#define MTK_HW_LRO_TIMER_UNIT 1 /* 20 us */
52#define MTK_HW_LRO_REFRESH_TIME 50000 /* 1 sec. */
53#define MTK_HW_LRO_AGG_TIME 10 /* 200us */
54#define MTK_HW_LRO_AGE_TIME 50 /* 1ms */
55#define MTK_HW_LRO_MAX_AGG_CNT 64
56#define MTK_HW_LRO_BW_THRE 3000
57#define MTK_HW_LRO_REPLACE_DELTA 1000
58#define MTK_HW_LRO_SDL_REMAIN_ROOM 1522
59
60/* Frame Engine Global Reset Register */
61#define MTK_RST_GL 0x04
62#define RST_GL_PSE BIT(0)
63
64/* Frame Engine Interrupt Status Register */
65#define MTK_INT_STATUS2 0x08
66#define MTK_GDM1_AF BIT(28)
67#define MTK_GDM2_AF BIT(29)
68
69/* PDMA HW LRO Alter Flow Timer Register */
70#define MTK_PDMA_LRO_ALT_REFRESH_TIMER 0x1c
71
72/* Frame Engine Interrupt Grouping Register */
73#define MTK_FE_INT_GRP 0x20
74
75/* CDMP Ingress Control Register */
76#define MTK_CDMQ_IG_CTRL 0x1400
77#define MTK_CDMQ_STAG_EN BIT(0)
78
79/* CDMP Exgress Control Register */
80#define MTK_CDMP_EG_CTRL 0x404
81
82/* GDM Exgress Control Register */
83#define MTK_GDMA_FWD_CFG(x) (0x500 + (x * 0x1000))
84#define MTK_GDMA_ICS_EN BIT(22)
85#define MTK_GDMA_TCS_EN BIT(21)
86#define MTK_GDMA_UCS_EN BIT(20)
87
88/* Unicast Filter MAC Address Register - Low */
89#define MTK_GDMA_MAC_ADRL(x) (0x508 + (x * 0x1000))
90
91/* Unicast Filter MAC Address Register - High */
92#define MTK_GDMA_MAC_ADRH(x) (0x50C + (x * 0x1000))
93
94/* PDMA RX Base Pointer Register */
95#define MTK_PRX_BASE_PTR0 0x900
96#define MTK_PRX_BASE_PTR_CFG(x) (MTK_PRX_BASE_PTR0 + (x * 0x10))
97
98/* PDMA RX Maximum Count Register */
99#define MTK_PRX_MAX_CNT0 0x904
100#define MTK_PRX_MAX_CNT_CFG(x) (MTK_PRX_MAX_CNT0 + (x * 0x10))
101
102/* PDMA RX CPU Pointer Register */
103#define MTK_PRX_CRX_IDX0 0x908
104#define MTK_PRX_CRX_IDX_CFG(x) (MTK_PRX_CRX_IDX0 + (x * 0x10))
105
106/* PDMA HW LRO Control Registers */
107#define MTK_PDMA_LRO_CTRL_DW0 0x980
108#define MTK_LRO_EN BIT(0)
109#define MTK_L3_CKS_UPD_EN BIT(7)
110#define MTK_LRO_ALT_PKT_CNT_MODE BIT(21)
111#define MTK_LRO_RING_RELINQUISH_REQ (0x7 << 26)
112#define MTK_LRO_RING_RELINQUISH_DONE (0x7 << 29)
113
114#define MTK_PDMA_LRO_CTRL_DW1 0x984
115#define MTK_PDMA_LRO_CTRL_DW2 0x988
116#define MTK_PDMA_LRO_CTRL_DW3 0x98c
117#define MTK_ADMA_MODE BIT(15)
118#define MTK_LRO_MIN_RXD_SDL (MTK_HW_LRO_SDL_REMAIN_ROOM << 16)
119
120/* PDMA Global Configuration Register */
121#define MTK_PDMA_GLO_CFG 0xa04
122#define MTK_MULTI_EN BIT(10)
123#define MTK_PDMA_SIZE_8DWORDS (1 << 4)
124
125/* PDMA Reset Index Register */
126#define MTK_PDMA_RST_IDX 0xa08
127#define MTK_PST_DRX_IDX0 BIT(16)
128#define MTK_PST_DRX_IDX_CFG(x) (MTK_PST_DRX_IDX0 << (x))
129
130/* PDMA Delay Interrupt Register */
131#define MTK_PDMA_DELAY_INT 0xa0c
132#define MTK_PDMA_DELAY_RX_EN BIT(15)
133#define MTK_PDMA_DELAY_RX_PINT 4
134#define MTK_PDMA_DELAY_RX_PINT_SHIFT 8
135#define MTK_PDMA_DELAY_RX_PTIME 4
136#define MTK_PDMA_DELAY_RX_DELAY \
137 (MTK_PDMA_DELAY_RX_EN | MTK_PDMA_DELAY_RX_PTIME | \
138 (MTK_PDMA_DELAY_RX_PINT << MTK_PDMA_DELAY_RX_PINT_SHIFT))
139
140/* PDMA Interrupt Status Register */
141#define MTK_PDMA_INT_STATUS 0xa20
142
143/* PDMA Interrupt Mask Register */
144#define MTK_PDMA_INT_MASK 0xa28
145
146/* PDMA HW LRO Alter Flow Delta Register */
147#define MTK_PDMA_LRO_ALT_SCORE_DELTA 0xa4c
148
149/* PDMA Interrupt grouping registers */
150#define MTK_PDMA_INT_GRP1 0xa50
151#define MTK_PDMA_INT_GRP2 0xa54
152
153/* PDMA HW LRO IP Setting Registers */
154#define MTK_LRO_RX_RING0_DIP_DW0 0xb04
155#define MTK_LRO_DIP_DW0_CFG(x) (MTK_LRO_RX_RING0_DIP_DW0 + (x * 0x40))
156#define MTK_RING_MYIP_VLD BIT(9)
157
158/* PDMA HW LRO Ring Control Registers */
159#define MTK_LRO_RX_RING0_CTRL_DW1 0xb28
160#define MTK_LRO_RX_RING0_CTRL_DW2 0xb2c
161#define MTK_LRO_RX_RING0_CTRL_DW3 0xb30
162#define MTK_LRO_CTRL_DW1_CFG(x) (MTK_LRO_RX_RING0_CTRL_DW1 + (x * 0x40))
163#define MTK_LRO_CTRL_DW2_CFG(x) (MTK_LRO_RX_RING0_CTRL_DW2 + (x * 0x40))
164#define MTK_LRO_CTRL_DW3_CFG(x) (MTK_LRO_RX_RING0_CTRL_DW3 + (x * 0x40))
165#define MTK_RING_AGE_TIME_L ((MTK_HW_LRO_AGE_TIME & 0x3ff) << 22)
166#define MTK_RING_AGE_TIME_H ((MTK_HW_LRO_AGE_TIME >> 10) & 0x3f)
167#define MTK_RING_AUTO_LERAN_MODE (3 << 6)
168#define MTK_RING_VLD BIT(8)
169#define MTK_RING_MAX_AGG_TIME ((MTK_HW_LRO_AGG_TIME & 0xffff) << 10)
170#define MTK_RING_MAX_AGG_CNT_L ((MTK_HW_LRO_MAX_AGG_CNT & 0x3f) << 26)
171#define MTK_RING_MAX_AGG_CNT_H ((MTK_HW_LRO_MAX_AGG_CNT >> 6) & 0x3)
172
173/* QDMA TX Queue Configuration Registers */
174#define MTK_QTX_CFG(x) (0x1800 + (x * 0x10))
175#define QDMA_RES_THRES 4
176
177/* QDMA TX Queue Scheduler Registers */
178#define MTK_QTX_SCH(x) (0x1804 + (x * 0x10))
179
180/* QDMA RX Base Pointer Register */
181#define MTK_QRX_BASE_PTR0 0x1900
182
183/* QDMA RX Maximum Count Register */
184#define MTK_QRX_MAX_CNT0 0x1904
185
186/* QDMA RX CPU Pointer Register */
187#define MTK_QRX_CRX_IDX0 0x1908
188
189/* QDMA RX DMA Pointer Register */
190#define MTK_QRX_DRX_IDX0 0x190C
191
192/* QDMA Global Configuration Register */
193#define MTK_QDMA_GLO_CFG 0x1A04
194#define MTK_RX_2B_OFFSET BIT(31)
195#define MTK_RX_BT_32DWORDS (3 << 11)
196#define MTK_NDP_CO_PRO BIT(10)
197#define MTK_TX_WB_DDONE BIT(6)
198#define MTK_DMA_SIZE_16DWORDS (2 << 4)
199#define MTK_RX_DMA_BUSY BIT(3)
200#define MTK_TX_DMA_BUSY BIT(1)
201#define MTK_RX_DMA_EN BIT(2)
202#define MTK_TX_DMA_EN BIT(0)
203#define MTK_DMA_BUSY_TIMEOUT HZ
204
205/* QDMA Reset Index Register */
206#define MTK_QDMA_RST_IDX 0x1A08
207
208/* QDMA Delay Interrupt Register */
209#define MTK_QDMA_DELAY_INT 0x1A0C
210
211/* QDMA Flow Control Register */
212#define MTK_QDMA_FC_THRES 0x1A10
213#define FC_THRES_DROP_MODE BIT(20)
214#define FC_THRES_DROP_EN (7 << 16)
215#define FC_THRES_MIN 0x4444
216
217/* QDMA Interrupt Status Register */
218#define MTK_QDMA_INT_STATUS 0x1A18
219#define MTK_RX_DONE_DLY BIT(30)
220#define MTK_RX_DONE_INT3 BIT(19)
221#define MTK_RX_DONE_INT2 BIT(18)
222#define MTK_RX_DONE_INT1 BIT(17)
223#define MTK_RX_DONE_INT0 BIT(16)
224#define MTK_TX_DONE_INT3 BIT(3)
225#define MTK_TX_DONE_INT2 BIT(2)
226#define MTK_TX_DONE_INT1 BIT(1)
227#define MTK_TX_DONE_INT0 BIT(0)
228#define MTK_RX_DONE_INT MTK_RX_DONE_DLY
229#define MTK_TX_DONE_INT (MTK_TX_DONE_INT0 | MTK_TX_DONE_INT1 | \
230 MTK_TX_DONE_INT2 | MTK_TX_DONE_INT3)
231
232/* QDMA Interrupt grouping registers */
233#define MTK_QDMA_INT_GRP1 0x1a20
234#define MTK_QDMA_INT_GRP2 0x1a24
235#define MTK_RLS_DONE_INT BIT(0)
236
237/* QDMA Interrupt Status Register */
238#define MTK_QDMA_INT_MASK 0x1A1C
239
240/* QDMA Interrupt Mask Register */
241#define MTK_QDMA_HRED2 0x1A44
242
243/* QDMA TX Forward CPU Pointer Register */
244#define MTK_QTX_CTX_PTR 0x1B00
245
246/* QDMA TX Forward DMA Pointer Register */
247#define MTK_QTX_DTX_PTR 0x1B04
248
249/* QDMA TX Release CPU Pointer Register */
250#define MTK_QTX_CRX_PTR 0x1B10
251
252/* QDMA TX Release DMA Pointer Register */
253#define MTK_QTX_DRX_PTR 0x1B14
254
255/* QDMA FQ Head Pointer Register */
256#define MTK_QDMA_FQ_HEAD 0x1B20
257
258/* QDMA FQ Head Pointer Register */
259#define MTK_QDMA_FQ_TAIL 0x1B24
260
261/* QDMA FQ Free Page Counter Register */
262#define MTK_QDMA_FQ_CNT 0x1B28
263
264/* QDMA FQ Free Page Buffer Length Register */
265#define MTK_QDMA_FQ_BLEN 0x1B2C
266
267/* GMA1 Received Good Byte Count Register */
268#define MTK_GDM1_TX_GBCNT 0x2400
269#define MTK_STAT_OFFSET 0x40
270
271/* QDMA descriptor txd4 */
272#define TX_DMA_CHKSUM (0x7 << 29)
273#define TX_DMA_TSO BIT(28)
274#define TX_DMA_FPORT_SHIFT 25
275#define TX_DMA_FPORT_MASK 0x7
276#define TX_DMA_INS_VLAN BIT(16)
277
278/* QDMA descriptor txd3 */
279#define TX_DMA_OWNER_CPU BIT(31)
280#define TX_DMA_LS0 BIT(30)
281#define TX_DMA_PLEN0(_x) (((_x) & MTK_TX_DMA_BUF_LEN) << 16)
282#define TX_DMA_PLEN1(_x) ((_x) & MTK_TX_DMA_BUF_LEN)
283#define TX_DMA_SWC BIT(14)
284#define TX_DMA_SDL(_x) (((_x) & 0x3fff) << 16)
285
286/* PDMA on MT7628 */
287#define TX_DMA_DONE BIT(31)
288#define TX_DMA_LS1 BIT(14)
289#define TX_DMA_DESP2_DEF (TX_DMA_LS0 | TX_DMA_DONE)
290
291/* QDMA descriptor rxd2 */
292#define RX_DMA_DONE BIT(31)
293#define RX_DMA_LSO BIT(30)
294#define RX_DMA_PLEN0(_x) (((_x) & 0x3fff) << 16)
295#define RX_DMA_GET_PLEN0(_x) (((_x) >> 16) & 0x3fff)
296
297/* QDMA descriptor rxd3 */
298#define RX_DMA_VID(_x) ((_x) & 0xfff)
299
300/* QDMA descriptor rxd4 */
301#define RX_DMA_L4_VALID BIT(24)
302#define RX_DMA_L4_VALID_PDMA BIT(30) /* when PDMA is used */
303#define RX_DMA_FPORT_SHIFT 19
304#define RX_DMA_FPORT_MASK 0x7
305
306/* PHY Indirect Access Control registers */
307#define MTK_PHY_IAC 0x10004
308#define PHY_IAC_ACCESS BIT(31)
309#define PHY_IAC_READ BIT(19)
310#define PHY_IAC_WRITE BIT(18)
311#define PHY_IAC_START BIT(16)
312#define PHY_IAC_ADDR_SHIFT 20
313#define PHY_IAC_REG_SHIFT 25
314#define PHY_IAC_TIMEOUT HZ
315
316#define MTK_MAC_MISC 0x1000c
317#define MTK_MUX_TO_ESW BIT(0)
318
319/* Mac control registers */
320#define MTK_MAC_MCR(x) (0x10100 + (x * 0x100))
321#define MAC_MCR_MAX_RX_1536 BIT(24)
322#define MAC_MCR_IPG_CFG (BIT(18) | BIT(16))
323#define MAC_MCR_FORCE_MODE BIT(15)
324#define MAC_MCR_TX_EN BIT(14)
325#define MAC_MCR_RX_EN BIT(13)
326#define MAC_MCR_BACKOFF_EN BIT(9)
327#define MAC_MCR_BACKPR_EN BIT(8)
328#define MAC_MCR_FORCE_RX_FC BIT(5)
329#define MAC_MCR_FORCE_TX_FC BIT(4)
330#define MAC_MCR_SPEED_1000 BIT(3)
331#define MAC_MCR_SPEED_100 BIT(2)
332#define MAC_MCR_FORCE_DPX BIT(1)
333#define MAC_MCR_FORCE_LINK BIT(0)
334#define MAC_MCR_FORCE_LINK_DOWN (MAC_MCR_FORCE_MODE)
335
336/* Mac status registers */
337#define MTK_MAC_MSR(x) (0x10108 + (x * 0x100))
338#define MAC_MSR_EEE1G BIT(7)
339#define MAC_MSR_EEE100M BIT(6)
340#define MAC_MSR_RX_FC BIT(5)
341#define MAC_MSR_TX_FC BIT(4)
342#define MAC_MSR_SPEED_1000 BIT(3)
343#define MAC_MSR_SPEED_100 BIT(2)
344#define MAC_MSR_SPEED_MASK (MAC_MSR_SPEED_1000 | MAC_MSR_SPEED_100)
345#define MAC_MSR_DPX BIT(1)
346#define MAC_MSR_LINK BIT(0)
347
348/* TRGMII RXC control register */
349#define TRGMII_RCK_CTRL 0x10300
350#define DQSI0(x) ((x << 0) & GENMASK(6, 0))
351#define DQSI1(x) ((x << 8) & GENMASK(14, 8))
352#define RXCTL_DMWTLAT(x) ((x << 16) & GENMASK(18, 16))
353#define RXC_DQSISEL BIT(30)
354#define RCK_CTRL_RGMII_1000 (RXC_DQSISEL | RXCTL_DMWTLAT(2) | DQSI1(16))
355#define RCK_CTRL_RGMII_10_100 RXCTL_DMWTLAT(2)
356
357/* TRGMII RXC control register */
358#define TRGMII_TCK_CTRL 0x10340
359#define TXCTL_DMWTLAT(x) ((x << 16) & GENMASK(18, 16))
360#define TXC_INV BIT(30)
361#define TCK_CTRL_RGMII_1000 TXCTL_DMWTLAT(2)
362#define TCK_CTRL_RGMII_10_100 (TXC_INV | TXCTL_DMWTLAT(2))
363
364/* TRGMII Interface mode register */
365#define INTF_MODE 0x10390
366#define TRGMII_INTF_DIS BIT(0)
367#define TRGMII_MODE BIT(1)
368#define TRGMII_CENTRAL_ALIGNED BIT(2)
369#define INTF_MODE_RGMII_1000 (TRGMII_MODE | TRGMII_CENTRAL_ALIGNED)
370#define INTF_MODE_RGMII_10_100 0
371
372/* GPIO port control registers for GMAC 2*/
373#define GPIO_OD33_CTRL8 0x4c0
374#define GPIO_BIAS_CTRL 0xed0
375#define GPIO_DRV_SEL10 0xf00
376
377/* ethernet subsystem chip id register */
378#define ETHSYS_CHIPID0_3 0x0
379#define ETHSYS_CHIPID4_7 0x4
380#define MT7623_ETH 7623
381#define MT7622_ETH 7622
382#define MT7621_ETH 7621
383
384/* ethernet system control register */
385#define ETHSYS_SYSCFG 0x10
386#define SYSCFG_DRAM_TYPE_DDR2 BIT(4)
387
388/* ethernet subsystem config register */
389#define ETHSYS_SYSCFG0 0x14
390#define SYSCFG0_GE_MASK 0x3
391#define SYSCFG0_GE_MODE(x, y) (x << (12 + (y * 2)))
392#define SYSCFG0_SGMII_MASK GENMASK(9, 8)
393#define SYSCFG0_SGMII_GMAC1 ((2 << 8) & SYSCFG0_SGMII_MASK)
394#define SYSCFG0_SGMII_GMAC2 ((3 << 8) & SYSCFG0_SGMII_MASK)
395#define SYSCFG0_SGMII_GMAC1_V2 BIT(9)
396#define SYSCFG0_SGMII_GMAC2_V2 BIT(8)
397
398
399/* ethernet subsystem clock register */
400#define ETHSYS_CLKCFG0 0x2c
401#define ETHSYS_TRGMII_CLK_SEL362_5 BIT(11)
402#define ETHSYS_TRGMII_MT7621_MASK (BIT(5) | BIT(6))
403#define ETHSYS_TRGMII_MT7621_APLL BIT(6)
404#define ETHSYS_TRGMII_MT7621_DDR_PLL BIT(5)
405
406/* ethernet reset control register */
407#define ETHSYS_RSTCTRL 0x34
408#define RSTCTRL_FE BIT(6)
409#define RSTCTRL_PPE BIT(31)
410
411/* SGMII subsystem config registers */
412/* Register to auto-negotiation restart */
413#define SGMSYS_PCS_CONTROL_1 0x0
414#define SGMII_AN_RESTART BIT(9)
415#define SGMII_ISOLATE BIT(10)
416#define SGMII_AN_ENABLE BIT(12)
417#define SGMII_LINK_STATYS BIT(18)
418#define SGMII_AN_ABILITY BIT(19)
419#define SGMII_AN_COMPLETE BIT(21)
420#define SGMII_PCS_FAULT BIT(23)
421#define SGMII_AN_EXPANSION_CLR BIT(30)
422
423/* Register to programmable link timer, the unit in 2 * 8ns */
424#define SGMSYS_PCS_LINK_TIMER 0x18
425#define SGMII_LINK_TIMER_DEFAULT (0x186a0 & GENMASK(19, 0))
426
427/* Register to control remote fault */
428#define SGMSYS_SGMII_MODE 0x20
429#define SGMII_IF_MODE_BIT0 BIT(0)
430#define SGMII_SPEED_DUPLEX_AN BIT(1)
431#define SGMII_SPEED_10 0x0
432#define SGMII_SPEED_100 BIT(2)
433#define SGMII_SPEED_1000 BIT(3)
434#define SGMII_DUPLEX_FULL BIT(4)
435#define SGMII_IF_MODE_BIT5 BIT(5)
436#define SGMII_REMOTE_FAULT_DIS BIT(8)
437#define SGMII_CODE_SYNC_SET_VAL BIT(9)
438#define SGMII_CODE_SYNC_SET_EN BIT(10)
439#define SGMII_SEND_AN_ERROR_EN BIT(11)
440#define SGMII_IF_MODE_MASK GENMASK(5, 1)
441
442/* Register to set SGMII speed, ANA RG_ Control Signals III*/
443#define SGMSYS_ANA_RG_CS3 0x2028
444#define RG_PHY_SPEED_MASK (BIT(2) | BIT(3))
445#define RG_PHY_SPEED_1_25G 0x0
446#define RG_PHY_SPEED_3_125G BIT(2)
447
448/* Register to power up QPHY */
449#define SGMSYS_QPHY_PWR_STATE_CTRL 0xe8
450#define SGMII_PHYA_PWD BIT(4)
451
452/* Infrasys subsystem config registers */
453#define INFRA_MISC2 0x70c
454#define CO_QPHY_SEL BIT(0)
455#define GEPHY_MAC_SEL BIT(1)
456
457/* MT7628/88 specific stuff */
458#define MT7628_PDMA_OFFSET 0x0800
459#define MT7628_SDM_OFFSET 0x0c00
460
461#define MT7628_TX_BASE_PTR0 (MT7628_PDMA_OFFSET + 0x00)
462#define MT7628_TX_MAX_CNT0 (MT7628_PDMA_OFFSET + 0x04)
463#define MT7628_TX_CTX_IDX0 (MT7628_PDMA_OFFSET + 0x08)
464#define MT7628_TX_DTX_IDX0 (MT7628_PDMA_OFFSET + 0x0c)
465#define MT7628_PST_DTX_IDX0 BIT(0)
466
467#define MT7628_SDM_MAC_ADRL (MT7628_SDM_OFFSET + 0x0c)
468#define MT7628_SDM_MAC_ADRH (MT7628_SDM_OFFSET + 0x10)
469
470struct mtk_rx_dma {
471 unsigned int rxd1;
472 unsigned int rxd2;
473 unsigned int rxd3;
474 unsigned int rxd4;
475} __packed __aligned(4);
476
477struct mtk_tx_dma {
478 unsigned int txd1;
479 unsigned int txd2;
480 unsigned int txd3;
481 unsigned int txd4;
482} __packed __aligned(4);
483
484struct mtk_eth;
485struct mtk_mac;
486
487/* struct mtk_hw_stats - the structure that holds the traffic statistics.
488 * @stats_lock: make sure that stats operations are atomic
489 * @reg_offset: the status register offset of the SoC
490 * @syncp: the refcount
491 *
492 * All of the supported SoCs have hardware counters for traffic statistics.
493 * Whenever the status IRQ triggers we can read the latest stats from these
494 * counters and store them in this struct.
495 */
496struct mtk_hw_stats {
497 u64 tx_bytes;
498 u64 tx_packets;
499 u64 tx_skip;
500 u64 tx_collisions;
501 u64 rx_bytes;
502 u64 rx_packets;
503 u64 rx_overflow;
504 u64 rx_fcs_errors;
505 u64 rx_short_errors;
506 u64 rx_long_errors;
507 u64 rx_checksum_errors;
508 u64 rx_flow_control_packets;
509
510 spinlock_t stats_lock;
511 u32 reg_offset;
512 struct u64_stats_sync syncp;
513};
514
515enum mtk_tx_flags {
516 /* PDMA descriptor can point at 1-2 segments. This enum allows us to
517 * track how memory was allocated so that it can be freed properly.
518 */
519 MTK_TX_FLAGS_SINGLE0 = 0x01,
520 MTK_TX_FLAGS_PAGE0 = 0x02,
521
522 /* MTK_TX_FLAGS_FPORTx allows tracking which port the transmitted
523 * SKB out instead of looking up through hardware TX descriptor.
524 */
525 MTK_TX_FLAGS_FPORT0 = 0x04,
526 MTK_TX_FLAGS_FPORT1 = 0x08,
527};
528
529/* This enum allows us to identify how the clock is defined on the array of the
530 * clock in the order
531 */
532enum mtk_clks_map {
533 MTK_CLK_ETHIF,
534 MTK_CLK_SGMIITOP,
535 MTK_CLK_ESW,
536 MTK_CLK_GP0,
537 MTK_CLK_GP1,
538 MTK_CLK_GP2,
539 MTK_CLK_FE,
540 MTK_CLK_TRGPLL,
541 MTK_CLK_SGMII_TX_250M,
542 MTK_CLK_SGMII_RX_250M,
543 MTK_CLK_SGMII_CDR_REF,
544 MTK_CLK_SGMII_CDR_FB,
545 MTK_CLK_SGMII2_TX_250M,
546 MTK_CLK_SGMII2_RX_250M,
547 MTK_CLK_SGMII2_CDR_REF,
548 MTK_CLK_SGMII2_CDR_FB,
549 MTK_CLK_SGMII_CK,
550 MTK_CLK_ETH2PLL,
551 MTK_CLK_MAX
552};
553
554#define MT7623_CLKS_BITMAP (BIT(MTK_CLK_ETHIF) | BIT(MTK_CLK_ESW) | \
555 BIT(MTK_CLK_GP1) | BIT(MTK_CLK_GP2) | \
556 BIT(MTK_CLK_TRGPLL))
557#define MT7622_CLKS_BITMAP (BIT(MTK_CLK_ETHIF) | BIT(MTK_CLK_ESW) | \
558 BIT(MTK_CLK_GP0) | BIT(MTK_CLK_GP1) | \
559 BIT(MTK_CLK_GP2) | \
560 BIT(MTK_CLK_SGMII_TX_250M) | \
561 BIT(MTK_CLK_SGMII_RX_250M) | \
562 BIT(MTK_CLK_SGMII_CDR_REF) | \
563 BIT(MTK_CLK_SGMII_CDR_FB) | \
564 BIT(MTK_CLK_SGMII_CK) | \
565 BIT(MTK_CLK_ETH2PLL))
566#define MT7621_CLKS_BITMAP (0)
567#define MT7628_CLKS_BITMAP (0)
568#define MT7629_CLKS_BITMAP (BIT(MTK_CLK_ETHIF) | BIT(MTK_CLK_ESW) | \
569 BIT(MTK_CLK_GP0) | BIT(MTK_CLK_GP1) | \
570 BIT(MTK_CLK_GP2) | BIT(MTK_CLK_FE) | \
571 BIT(MTK_CLK_SGMII_TX_250M) | \
572 BIT(MTK_CLK_SGMII_RX_250M) | \
573 BIT(MTK_CLK_SGMII_CDR_REF) | \
574 BIT(MTK_CLK_SGMII_CDR_FB) | \
575 BIT(MTK_CLK_SGMII2_TX_250M) | \
576 BIT(MTK_CLK_SGMII2_RX_250M) | \
577 BIT(MTK_CLK_SGMII2_CDR_REF) | \
578 BIT(MTK_CLK_SGMII2_CDR_FB) | \
579 BIT(MTK_CLK_SGMII_CK) | \
580 BIT(MTK_CLK_ETH2PLL) | BIT(MTK_CLK_SGMIITOP))
581
582enum mtk_dev_state {
583 MTK_HW_INIT,
584 MTK_RESETTING
585};
586
587/* struct mtk_tx_buf - This struct holds the pointers to the memory pointed at
588 * by the TX descriptor s
589 * @skb: The SKB pointer of the packet being sent
590 * @dma_addr0: The base addr of the first segment
591 * @dma_len0: The length of the first segment
592 * @dma_addr1: The base addr of the second segment
593 * @dma_len1: The length of the second segment
594 */
595struct mtk_tx_buf {
596 struct sk_buff *skb;
597 u32 flags;
598 DEFINE_DMA_UNMAP_ADDR(dma_addr0);
599 DEFINE_DMA_UNMAP_LEN(dma_len0);
600 DEFINE_DMA_UNMAP_ADDR(dma_addr1);
601 DEFINE_DMA_UNMAP_LEN(dma_len1);
602};
603
604/* struct mtk_tx_ring - This struct holds info describing a TX ring
605 * @dma: The descriptor ring
606 * @buf: The memory pointed at by the ring
607 * @phys: The physical addr of tx_buf
608 * @next_free: Pointer to the next free descriptor
609 * @last_free: Pointer to the last free descriptor
610 * @thresh: The threshold of minimum amount of free descriptors
611 * @free_count: QDMA uses a linked list. Track how many free descriptors
612 * are present
613 */
614struct mtk_tx_ring {
615 struct mtk_tx_dma *dma;
616 struct mtk_tx_buf *buf;
617 dma_addr_t phys;
618 struct mtk_tx_dma *next_free;
619 struct mtk_tx_dma *last_free;
620 u16 thresh;
621 atomic_t free_count;
622 int dma_size;
623 struct mtk_tx_dma *dma_pdma; /* For MT7628/88 PDMA handling */
624 dma_addr_t phys_pdma;
625 int cpu_idx;
626};
627
628/* PDMA rx ring mode */
629enum mtk_rx_flags {
630 MTK_RX_FLAGS_NORMAL = 0,
631 MTK_RX_FLAGS_HWLRO,
632 MTK_RX_FLAGS_QDMA,
633};
634
635/* struct mtk_rx_ring - This struct holds info describing a RX ring
636 * @dma: The descriptor ring
637 * @data: The memory pointed at by the ring
638 * @phys: The physical addr of rx_buf
639 * @frag_size: How big can each fragment be
640 * @buf_size: The size of each packet buffer
641 * @calc_idx: The current head of ring
642 */
643struct mtk_rx_ring {
644 struct mtk_rx_dma *dma;
645 u8 **data;
646 dma_addr_t phys;
647 u16 frag_size;
648 u16 buf_size;
649 u16 dma_size;
650 bool calc_idx_update;
651 u16 calc_idx;
652 u32 crx_idx_reg;
653};
654
655enum mkt_eth_capabilities {
656 MTK_RGMII_BIT = 0,
657 MTK_TRGMII_BIT,
658 MTK_SGMII_BIT,
659 MTK_ESW_BIT,
660 MTK_GEPHY_BIT,
661 MTK_MUX_BIT,
662 MTK_INFRA_BIT,
663 MTK_SHARED_SGMII_BIT,
664 MTK_HWLRO_BIT,
665 MTK_SHARED_INT_BIT,
666 MTK_TRGMII_MT7621_CLK_BIT,
667 MTK_QDMA_BIT,
668 MTK_SOC_MT7628_BIT,
669
670 /* MUX BITS*/
671 MTK_ETH_MUX_GDM1_TO_GMAC1_ESW_BIT,
672 MTK_ETH_MUX_GMAC2_GMAC0_TO_GEPHY_BIT,
673 MTK_ETH_MUX_U3_GMAC2_TO_QPHY_BIT,
674 MTK_ETH_MUX_GMAC1_GMAC2_TO_SGMII_RGMII_BIT,
675 MTK_ETH_MUX_GMAC12_TO_GEPHY_SGMII_BIT,
676
677 /* PATH BITS */
678 MTK_ETH_PATH_GMAC1_RGMII_BIT,
679 MTK_ETH_PATH_GMAC1_TRGMII_BIT,
680 MTK_ETH_PATH_GMAC1_SGMII_BIT,
681 MTK_ETH_PATH_GMAC2_RGMII_BIT,
682 MTK_ETH_PATH_GMAC2_SGMII_BIT,
683 MTK_ETH_PATH_GMAC2_GEPHY_BIT,
684 MTK_ETH_PATH_GDM1_ESW_BIT,
685};
686
687/* Supported hardware group on SoCs */
688#define MTK_RGMII BIT(MTK_RGMII_BIT)
689#define MTK_TRGMII BIT(MTK_TRGMII_BIT)
690#define MTK_SGMII BIT(MTK_SGMII_BIT)
691#define MTK_ESW BIT(MTK_ESW_BIT)
692#define MTK_GEPHY BIT(MTK_GEPHY_BIT)
693#define MTK_MUX BIT(MTK_MUX_BIT)
694#define MTK_INFRA BIT(MTK_INFRA_BIT)
695#define MTK_SHARED_SGMII BIT(MTK_SHARED_SGMII_BIT)
696#define MTK_HWLRO BIT(MTK_HWLRO_BIT)
697#define MTK_SHARED_INT BIT(MTK_SHARED_INT_BIT)
698#define MTK_TRGMII_MT7621_CLK BIT(MTK_TRGMII_MT7621_CLK_BIT)
699#define MTK_QDMA BIT(MTK_QDMA_BIT)
700#define MTK_SOC_MT7628 BIT(MTK_SOC_MT7628_BIT)
701
702#define MTK_ETH_MUX_GDM1_TO_GMAC1_ESW \
703 BIT(MTK_ETH_MUX_GDM1_TO_GMAC1_ESW_BIT)
704#define MTK_ETH_MUX_GMAC2_GMAC0_TO_GEPHY \
705 BIT(MTK_ETH_MUX_GMAC2_GMAC0_TO_GEPHY_BIT)
706#define MTK_ETH_MUX_U3_GMAC2_TO_QPHY \
707 BIT(MTK_ETH_MUX_U3_GMAC2_TO_QPHY_BIT)
708#define MTK_ETH_MUX_GMAC1_GMAC2_TO_SGMII_RGMII \
709 BIT(MTK_ETH_MUX_GMAC1_GMAC2_TO_SGMII_RGMII_BIT)
710#define MTK_ETH_MUX_GMAC12_TO_GEPHY_SGMII \
711 BIT(MTK_ETH_MUX_GMAC12_TO_GEPHY_SGMII_BIT)
712
713/* Supported path present on SoCs */
714#define MTK_ETH_PATH_GMAC1_RGMII BIT(MTK_ETH_PATH_GMAC1_RGMII_BIT)
715#define MTK_ETH_PATH_GMAC1_TRGMII BIT(MTK_ETH_PATH_GMAC1_TRGMII_BIT)
716#define MTK_ETH_PATH_GMAC1_SGMII BIT(MTK_ETH_PATH_GMAC1_SGMII_BIT)
717#define MTK_ETH_PATH_GMAC2_RGMII BIT(MTK_ETH_PATH_GMAC2_RGMII_BIT)
718#define MTK_ETH_PATH_GMAC2_SGMII BIT(MTK_ETH_PATH_GMAC2_SGMII_BIT)
719#define MTK_ETH_PATH_GMAC2_GEPHY BIT(MTK_ETH_PATH_GMAC2_GEPHY_BIT)
720#define MTK_ETH_PATH_GDM1_ESW BIT(MTK_ETH_PATH_GDM1_ESW_BIT)
721
722#define MTK_GMAC1_RGMII (MTK_ETH_PATH_GMAC1_RGMII | MTK_RGMII)
723#define MTK_GMAC1_TRGMII (MTK_ETH_PATH_GMAC1_TRGMII | MTK_TRGMII)
724#define MTK_GMAC1_SGMII (MTK_ETH_PATH_GMAC1_SGMII | MTK_SGMII)
725#define MTK_GMAC2_RGMII (MTK_ETH_PATH_GMAC2_RGMII | MTK_RGMII)
726#define MTK_GMAC2_SGMII (MTK_ETH_PATH_GMAC2_SGMII | MTK_SGMII)
727#define MTK_GMAC2_GEPHY (MTK_ETH_PATH_GMAC2_GEPHY | MTK_GEPHY)
728#define MTK_GDM1_ESW (MTK_ETH_PATH_GDM1_ESW | MTK_ESW)
729
730/* MUXes present on SoCs */
731/* 0: GDM1 -> GMAC1, 1: GDM1 -> ESW */
732#define MTK_MUX_GDM1_TO_GMAC1_ESW (MTK_ETH_MUX_GDM1_TO_GMAC1_ESW | MTK_MUX)
733
734/* 0: GMAC2 -> GEPHY, 1: GMAC0 -> GePHY */
735#define MTK_MUX_GMAC2_GMAC0_TO_GEPHY \
736 (MTK_ETH_MUX_GMAC2_GMAC0_TO_GEPHY | MTK_MUX | MTK_INFRA)
737
738/* 0: U3 -> QPHY, 1: GMAC2 -> QPHY */
739#define MTK_MUX_U3_GMAC2_TO_QPHY \
740 (MTK_ETH_MUX_U3_GMAC2_TO_QPHY | MTK_MUX | MTK_INFRA)
741
742/* 2: GMAC1 -> SGMII, 3: GMAC2 -> SGMII */
743#define MTK_MUX_GMAC1_GMAC2_TO_SGMII_RGMII \
744 (MTK_ETH_MUX_GMAC1_GMAC2_TO_SGMII_RGMII | MTK_MUX | \
745 MTK_SHARED_SGMII)
746
747/* 0: GMACx -> GEPHY, 1: GMACx -> SGMII where x is 1 or 2 */
748#define MTK_MUX_GMAC12_TO_GEPHY_SGMII \
749 (MTK_ETH_MUX_GMAC12_TO_GEPHY_SGMII | MTK_MUX)
750
751#define MTK_HAS_CAPS(caps, _x) (((caps) & (_x)) == (_x))
752
753#define MT7621_CAPS (MTK_GMAC1_RGMII | MTK_GMAC1_TRGMII | \
754 MTK_GMAC2_RGMII | MTK_SHARED_INT | \
755 MTK_TRGMII_MT7621_CLK | MTK_QDMA)
756
757#define MT7622_CAPS (MTK_GMAC1_RGMII | MTK_GMAC1_SGMII | MTK_GMAC2_RGMII | \
758 MTK_GMAC2_SGMII | MTK_GDM1_ESW | \
759 MTK_MUX_GDM1_TO_GMAC1_ESW | \
760 MTK_MUX_GMAC1_GMAC2_TO_SGMII_RGMII | MTK_QDMA)
761
762#define MT7623_CAPS (MTK_GMAC1_RGMII | MTK_GMAC1_TRGMII | MTK_GMAC2_RGMII | \
763 MTK_QDMA)
764
765#define MT7628_CAPS (MTK_SHARED_INT | MTK_SOC_MT7628)
766
767#define MT7629_CAPS (MTK_GMAC1_SGMII | MTK_GMAC2_SGMII | MTK_GMAC2_GEPHY | \
768 MTK_GDM1_ESW | MTK_MUX_GDM1_TO_GMAC1_ESW | \
769 MTK_MUX_GMAC2_GMAC0_TO_GEPHY | \
770 MTK_MUX_U3_GMAC2_TO_QPHY | \
771 MTK_MUX_GMAC12_TO_GEPHY_SGMII | MTK_QDMA)
772
773/* struct mtk_eth_data - This is the structure holding all differences
774 * among various plaforms
775 * @ana_rgc3: The offset for register ANA_RGC3 related to
776 * sgmiisys syscon
777 * @caps Flags shown the extra capability for the SoC
778 * @hw_features Flags shown HW features
779 * @required_clks Flags shown the bitmap for required clocks on
780 * the target SoC
781 * @required_pctl A bool value to show whether the SoC requires
782 * the extra setup for those pins used by GMAC.
783 */
784struct mtk_soc_data {
785 u32 ana_rgc3;
786 u32 caps;
787 u32 required_clks;
788 bool required_pctl;
789 netdev_features_t hw_features;
790};
791
792/* currently no SoC has more than 2 macs */
793#define MTK_MAX_DEVS 2
794
795#define MTK_SGMII_PHYSPEED_AN BIT(31)
796#define MTK_SGMII_PHYSPEED_MASK GENMASK(2, 0)
797#define MTK_SGMII_PHYSPEED_1000 BIT(0)
798#define MTK_SGMII_PHYSPEED_2500 BIT(1)
799#define MTK_HAS_FLAGS(flags, _x) (((flags) & (_x)) == (_x))
800
801/* struct mtk_sgmii - This is the structure holding sgmii regmap and its
802 * characteristics
803 * @regmap: The register map pointing at the range used to setup
804 * SGMII modes
805 * @flags: The enum refers to which mode the sgmii wants to run on
806 * @ana_rgc3: The offset refers to register ANA_RGC3 related to regmap
807 */
808
809struct mtk_sgmii {
810 struct regmap *regmap[MTK_MAX_DEVS];
811 u32 flags[MTK_MAX_DEVS];
812 u32 ana_rgc3;
813};
814
815/* struct mtk_eth - This is the main datasructure for holding the state
816 * of the driver
817 * @dev: The device pointer
818 * @base: The mapped register i/o base
819 * @page_lock: Make sure that register operations are atomic
820 * @tx_irq__lock: Make sure that IRQ register operations are atomic
821 * @rx_irq__lock: Make sure that IRQ register operations are atomic
822 * @dummy_dev: we run 2 netdevs on 1 physical DMA ring and need a
823 * dummy for NAPI to work
824 * @netdev: The netdev instances
825 * @mac: Each netdev is linked to a physical MAC
826 * @irq: The IRQ that we are using
827 * @msg_enable: Ethtool msg level
828 * @ethsys: The register map pointing at the range used to setup
829 * MII modes
830 * @infra: The register map pointing at the range used to setup
831 * SGMII and GePHY path
832 * @pctl: The register map pointing at the range used to setup
833 * GMAC port drive/slew values
834 * @dma_refcnt: track how many netdevs are using the DMA engine
835 * @tx_ring: Pointer to the memory holding info about the TX ring
836 * @rx_ring: Pointer to the memory holding info about the RX ring
837 * @rx_ring_qdma: Pointer to the memory holding info about the QDMA RX ring
838 * @tx_napi: The TX NAPI struct
839 * @rx_napi: The RX NAPI struct
840 * @scratch_ring: Newer SoCs need memory for a second HW managed TX ring
841 * @phy_scratch_ring: physical address of scratch_ring
842 * @scratch_head: The scratch memory that scratch_ring points to.
843 * @clks: clock array for all clocks required
844 * @mii_bus: If there is a bus we need to create an instance for it
845 * @pending_work: The workqueue used to reset the dma ring
846 * @state: Initialization and runtime state of the device
847 * @soc: Holding specific data among vaious SoCs
848 */
849
850struct mtk_eth {
851 struct device *dev;
852 void __iomem *base;
853 spinlock_t page_lock;
854 spinlock_t tx_irq_lock;
855 spinlock_t rx_irq_lock;
856 struct net_device dummy_dev;
857 struct net_device *netdev[MTK_MAX_DEVS];
858 struct mtk_mac *mac[MTK_MAX_DEVS];
859 int irq[3];
860 u32 msg_enable;
861 unsigned long sysclk;
862 struct regmap *ethsys;
863 struct regmap *infra;
864 struct mtk_sgmii *sgmii;
865 struct regmap *pctl;
866 bool hwlro;
867 refcount_t dma_refcnt;
868 struct mtk_tx_ring tx_ring;
869 struct mtk_rx_ring rx_ring[MTK_MAX_RX_RING_NUM];
870 struct mtk_rx_ring rx_ring_qdma;
871 struct napi_struct tx_napi;
872 struct napi_struct rx_napi;
873 struct mtk_tx_dma *scratch_ring;
874 dma_addr_t phy_scratch_ring;
875 void *scratch_head;
876 struct clk *clks[MTK_CLK_MAX];
877
878 struct mii_bus *mii_bus;
879 struct work_struct pending_work;
880 unsigned long state;
881
882 const struct mtk_soc_data *soc;
883
884 u32 tx_int_mask_reg;
885 u32 tx_int_status_reg;
886 u32 rx_dma_l4_valid;
887 int ip_align;
888};
889
890/* struct mtk_mac - the structure that holds the info about the MACs of the
891 * SoC
892 * @id: The number of the MAC
893 * @interface: Interface mode kept for detecting change in hw settings
894 * @of_node: Our devicetree node
895 * @hw: Backpointer to our main datastruture
896 * @hw_stats: Packet statistics counter
897 */
898struct mtk_mac {
899 int id;
900 phy_interface_t interface;
901 unsigned int mode;
902 int speed;
903 struct device_node *of_node;
904 struct phylink *phylink;
905 struct phylink_config phylink_config;
906 struct mtk_eth *hw;
907 struct mtk_hw_stats *hw_stats;
908 __be32 hwlro_ip[MTK_MAX_LRO_IP_CNT];
909 int hwlro_ip_cnt;
910};
911
912/* the struct describing the SoC. these are declared in the soc_xyz.c files */
913extern const struct of_device_id of_mtk_match[];
914
915/* read the hardware status register */
916void mtk_stats_update_mac(struct mtk_mac *mac);
917
918void mtk_w32(struct mtk_eth *eth, u32 val, unsigned reg);
919u32 mtk_r32(struct mtk_eth *eth, unsigned reg);
920
921int mtk_sgmii_init(struct mtk_sgmii *ss, struct device_node *np,
922 u32 ana_rgc3);
923int mtk_sgmii_setup_mode_an(struct mtk_sgmii *ss, int id);
924int mtk_sgmii_setup_mode_force(struct mtk_sgmii *ss, int id,
925 const struct phylink_link_state *state);
926void mtk_sgmii_restart_an(struct mtk_eth *eth, int mac_id);
927
928int mtk_gmac_sgmii_path_setup(struct mtk_eth *eth, int mac_id);
929int mtk_gmac_gephy_path_setup(struct mtk_eth *eth, int mac_id);
930int mtk_gmac_rgmii_path_setup(struct mtk_eth *eth, int mac_id);
931
932#endif /* MTK_ETH_H */