1/* SPDX-License-Identifier: GPL-2.0-or-later */
  2/*
  3 * drivers/net/dsa/mv88e6060.h - Marvell 88e6060 switch chip support
  4 * Copyright (c) 2015 Neil Armstrong
  5 *
  6 * Based on mv88e6xxx.h
  7 * Copyright (c) 2008 Marvell Semiconductor
  8 */
  9
 10#ifndef __MV88E6060_H
 11#define __MV88E6060_H
 12
 13#define MV88E6060_PORTS	6
 14
 15#define REG_PORT(p)		(0x8 + (p))
 16#define PORT_STATUS		0x00
 17#define PORT_STATUS_PAUSE_EN	BIT(15)
 18#define PORT_STATUS_MY_PAUSE	BIT(14)
 19#define PORT_STATUS_FC		(PORT_STATUS_MY_PAUSE | PORT_STATUS_PAUSE_EN)
 20#define PORT_STATUS_RESOLVED	BIT(13)
 21#define PORT_STATUS_LINK	BIT(12)
 22#define PORT_STATUS_PORTMODE	BIT(11)
 23#define PORT_STATUS_PHYMODE	BIT(10)
 24#define PORT_STATUS_DUPLEX	BIT(9)
 25#define PORT_STATUS_SPEED	BIT(8)
 26#define PORT_SWITCH_ID		0x03
 27#define PORT_SWITCH_ID_6060	0x0600
 28#define PORT_SWITCH_ID_6060_MASK	0xfff0
 29#define PORT_SWITCH_ID_6060_R1	0x0601
 30#define PORT_SWITCH_ID_6060_R2	0x0602
 31#define PORT_CONTROL		0x04
 32#define PORT_CONTROL_FORCE_FLOW_CTRL	BIT(15)
 33#define PORT_CONTROL_TRAILER	BIT(14)
 34#define PORT_CONTROL_HEADER	BIT(11)
 35#define PORT_CONTROL_INGRESS_MODE	BIT(8)
 36#define PORT_CONTROL_VLAN_TUNNEL	BIT(7)
 37#define PORT_CONTROL_STATE_MASK	0x03
 38#define PORT_CONTROL_STATE_DISABLED	0x00
 39#define PORT_CONTROL_STATE_BLOCKING	0x01
 40#define PORT_CONTROL_STATE_LEARNING	0x02
 41#define PORT_CONTROL_STATE_FORWARDING	0x03
 42#define PORT_VLAN_MAP		0x06
 43#define PORT_VLAN_MAP_DBNUM_SHIFT	12
 44#define PORT_VLAN_MAP_TABLE_MASK	0x1f
 45#define PORT_ASSOC_VECTOR	0x0b
 46#define PORT_ASSOC_VECTOR_MONITOR	BIT(15)
 47#define PORT_ASSOC_VECTOR_PAV_MASK	0x1f
 48#define PORT_RX_CNTR		0x10
 49#define PORT_TX_CNTR		0x11
 50
 51#define REG_GLOBAL		0x0f
 52#define GLOBAL_STATUS		0x00
 53#define GLOBAL_STATUS_SW_MODE_MASK	(0x3 << 12)
 54#define GLOBAL_STATUS_SW_MODE_0	(0x0 << 12)
 55#define GLOBAL_STATUS_SW_MODE_1	(0x1 << 12)
 56#define GLOBAL_STATUS_SW_MODE_2	(0x2 << 12)
 57#define GLOBAL_STATUS_SW_MODE_3	(0x3 << 12)
 58#define GLOBAL_STATUS_INIT_READY	BIT(11)
 59#define GLOBAL_STATUS_ATU_FULL		BIT(3)
 60#define GLOBAL_STATUS_ATU_DONE		BIT(2)
 61#define GLOBAL_STATUS_PHY_INT	BIT(1)
 62#define GLOBAL_STATUS_EEINT	BIT(0)
 63#define GLOBAL_MAC_01		0x01
 64#define GLOBAL_MAC_01_DIFF_ADDR	BIT(8)
 65#define GLOBAL_MAC_23		0x02
 66#define GLOBAL_MAC_45		0x03
 67#define GLOBAL_CONTROL		0x04
 68#define GLOBAL_CONTROL_DISCARD_EXCESS	BIT(13)
 69#define GLOBAL_CONTROL_MAX_FRAME_1536	BIT(10)
 70#define GLOBAL_CONTROL_RELOAD_EEPROM	BIT(9)
 71#define GLOBAL_CONTROL_CTRMODE		BIT(8)
 72#define GLOBAL_CONTROL_ATU_FULL_EN	BIT(3)
 73#define GLOBAL_CONTROL_ATU_DONE_EN	BIT(2)
 74#define GLOBAL_CONTROL_PHYINT_EN	BIT(1)
 75#define GLOBAL_CONTROL_EEPROM_DONE_EN	BIT(0)
 76#define GLOBAL_ATU_CONTROL	0x0a
 77#define GLOBAL_ATU_CONTROL_SWRESET	BIT(15)
 78#define GLOBAL_ATU_CONTROL_LEARNDIS	BIT(14)
 79#define GLOBAL_ATU_CONTROL_ATUSIZE_256	(0x0 << 12)
 80#define GLOBAL_ATU_CONTROL_ATUSIZE_512	(0x1 << 12)
 81#define GLOBAL_ATU_CONTROL_ATUSIZE_1024	(0x2 << 12)
 82#define GLOBAL_ATU_CONTROL_ATE_AGE_SHIFT	4
 83#define GLOBAL_ATU_CONTROL_ATE_AGE_MASK	(0xff << 4)
 84#define GLOBAL_ATU_CONTROL_ATE_AGE_5MIN	(0x13 << 4)
 85#define GLOBAL_ATU_OP		0x0b
 86#define GLOBAL_ATU_OP_BUSY	BIT(15)
 87#define GLOBAL_ATU_OP_NOP		(0 << 12)
 88#define GLOBAL_ATU_OP_FLUSH_ALL	((1 << 12) | GLOBAL_ATU_OP_BUSY)
 89#define GLOBAL_ATU_OP_FLUSH_UNLOCKED	((2 << 12) | GLOBAL_ATU_OP_BUSY)
 90#define GLOBAL_ATU_OP_LOAD_DB		((3 << 12) | GLOBAL_ATU_OP_BUSY)
 91#define GLOBAL_ATU_OP_GET_NEXT_DB	((4 << 12) | GLOBAL_ATU_OP_BUSY)
 92#define GLOBAL_ATU_OP_FLUSH_DB		((5 << 12) | GLOBAL_ATU_OP_BUSY)
 93#define GLOBAL_ATU_OP_FLUSH_UNLOCKED_DB ((6 << 12) | GLOBAL_ATU_OP_BUSY)
 94#define GLOBAL_ATU_DATA		0x0c
 95#define GLOBAL_ATU_DATA_PORT_VECTOR_MASK	0x3f0
 96#define GLOBAL_ATU_DATA_PORT_VECTOR_SHIFT	4
 97#define GLOBAL_ATU_DATA_STATE_MASK		0x0f
 98#define GLOBAL_ATU_DATA_STATE_UNUSED		0x00
 99#define GLOBAL_ATU_DATA_STATE_UC_STATIC		0x0e
100#define GLOBAL_ATU_DATA_STATE_UC_LOCKED		0x0f
101#define GLOBAL_ATU_DATA_STATE_MC_STATIC		0x07
102#define GLOBAL_ATU_DATA_STATE_MC_LOCKED		0x0e
103#define GLOBAL_ATU_MAC_01	0x0d
104#define GLOBAL_ATU_MAC_23	0x0e
105#define GLOBAL_ATU_MAC_45	0x0f
106
107struct mv88e6060_priv {
108	/* MDIO bus and address on bus to use. When in single chip
109	 * mode, address is 0, and the switch uses multiple addresses
110	 * on the bus.  When in multi-chip mode, the switch uses a
111	 * single address which contains two registers used for
112	 * indirect access to more registers.
113	 */
114	struct mii_bus *bus;
115	int sw_addr;
116	struct dsa_switch *ds;
117};
118
119#endif