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1// SPDX-License-Identifier: GPL-2.0+
2// Copyright 2017 IBM Corp.
3#include <linux/pci.h>
4#include <asm/pnv-ocxl.h>
5#include <misc/ocxl-config.h>
6#include "ocxl_internal.h"
7
8#define EXTRACT_BIT(val, bit) (!!(val & BIT(bit)))
9#define EXTRACT_BITS(val, s, e) ((val & GENMASK(e, s)) >> s)
10
11#define OCXL_DVSEC_AFU_IDX_MASK GENMASK(5, 0)
12#define OCXL_DVSEC_ACTAG_MASK GENMASK(11, 0)
13#define OCXL_DVSEC_PASID_MASK GENMASK(19, 0)
14#define OCXL_DVSEC_PASID_LOG_MASK GENMASK(4, 0)
15
16#define OCXL_DVSEC_TEMPL_VERSION 0x0
17#define OCXL_DVSEC_TEMPL_NAME 0x4
18#define OCXL_DVSEC_TEMPL_AFU_VERSION 0x1C
19#define OCXL_DVSEC_TEMPL_MMIO_GLOBAL 0x20
20#define OCXL_DVSEC_TEMPL_MMIO_GLOBAL_SZ 0x28
21#define OCXL_DVSEC_TEMPL_MMIO_PP 0x30
22#define OCXL_DVSEC_TEMPL_MMIO_PP_SZ 0x38
23#define OCXL_DVSEC_TEMPL_ALL_MEM_SZ 0x3C
24#define OCXL_DVSEC_TEMPL_LPC_MEM_START 0x40
25#define OCXL_DVSEC_TEMPL_WWID 0x48
26#define OCXL_DVSEC_TEMPL_LPC_MEM_SZ 0x58
27
28#define OCXL_MAX_AFU_PER_FUNCTION 64
29#define OCXL_TEMPL_LEN_1_0 0x58
30#define OCXL_TEMPL_LEN_1_1 0x60
31#define OCXL_TEMPL_NAME_LEN 24
32#define OCXL_CFG_TIMEOUT 3
33
34static int find_dvsec(struct pci_dev *dev, int dvsec_id)
35{
36 int vsec = 0;
37 u16 vendor, id;
38
39 while ((vsec = pci_find_next_ext_capability(dev, vsec,
40 OCXL_EXT_CAP_ID_DVSEC))) {
41 pci_read_config_word(dev, vsec + OCXL_DVSEC_VENDOR_OFFSET,
42 &vendor);
43 pci_read_config_word(dev, vsec + OCXL_DVSEC_ID_OFFSET, &id);
44 if (vendor == PCI_VENDOR_ID_IBM && id == dvsec_id)
45 return vsec;
46 }
47 return 0;
48}
49
50static int find_dvsec_afu_ctrl(struct pci_dev *dev, u8 afu_idx)
51{
52 int vsec = 0;
53 u16 vendor, id;
54 u8 idx;
55
56 while ((vsec = pci_find_next_ext_capability(dev, vsec,
57 OCXL_EXT_CAP_ID_DVSEC))) {
58 pci_read_config_word(dev, vsec + OCXL_DVSEC_VENDOR_OFFSET,
59 &vendor);
60 pci_read_config_word(dev, vsec + OCXL_DVSEC_ID_OFFSET, &id);
61
62 if (vendor == PCI_VENDOR_ID_IBM &&
63 id == OCXL_DVSEC_AFU_CTRL_ID) {
64 pci_read_config_byte(dev,
65 vsec + OCXL_DVSEC_AFU_CTRL_AFU_IDX,
66 &idx);
67 if (idx == afu_idx)
68 return vsec;
69 }
70 }
71 return 0;
72}
73
74static void read_pasid(struct pci_dev *dev, struct ocxl_fn_config *fn)
75{
76 u16 val;
77 int pos;
78
79 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_PASID);
80 if (!pos) {
81 /*
82 * PASID capability is not mandatory, but there
83 * shouldn't be any AFU
84 */
85 dev_dbg(&dev->dev, "Function doesn't require any PASID\n");
86 fn->max_pasid_log = -1;
87 goto out;
88 }
89 pci_read_config_word(dev, pos + PCI_PASID_CAP, &val);
90 fn->max_pasid_log = EXTRACT_BITS(val, 8, 12);
91
92out:
93 dev_dbg(&dev->dev, "PASID capability:\n");
94 dev_dbg(&dev->dev, " Max PASID log = %d\n", fn->max_pasid_log);
95}
96
97static int read_dvsec_tl(struct pci_dev *dev, struct ocxl_fn_config *fn)
98{
99 int pos;
100
101 pos = find_dvsec(dev, OCXL_DVSEC_TL_ID);
102 if (!pos && PCI_FUNC(dev->devfn) == 0) {
103 dev_err(&dev->dev, "Can't find TL DVSEC\n");
104 return -ENODEV;
105 }
106 if (pos && PCI_FUNC(dev->devfn) != 0) {
107 dev_err(&dev->dev, "TL DVSEC is only allowed on function 0\n");
108 return -ENODEV;
109 }
110 fn->dvsec_tl_pos = pos;
111 return 0;
112}
113
114static int read_dvsec_function(struct pci_dev *dev, struct ocxl_fn_config *fn)
115{
116 int pos, afu_present;
117 u32 val;
118
119 pos = find_dvsec(dev, OCXL_DVSEC_FUNC_ID);
120 if (!pos) {
121 dev_err(&dev->dev, "Can't find function DVSEC\n");
122 return -ENODEV;
123 }
124 fn->dvsec_function_pos = pos;
125
126 pci_read_config_dword(dev, pos + OCXL_DVSEC_FUNC_OFF_INDEX, &val);
127 afu_present = EXTRACT_BIT(val, 31);
128 if (!afu_present) {
129 fn->max_afu_index = -1;
130 dev_dbg(&dev->dev, "Function doesn't define any AFU\n");
131 goto out;
132 }
133 fn->max_afu_index = EXTRACT_BITS(val, 24, 29);
134
135out:
136 dev_dbg(&dev->dev, "Function DVSEC:\n");
137 dev_dbg(&dev->dev, " Max AFU index = %d\n", fn->max_afu_index);
138 return 0;
139}
140
141static int read_dvsec_afu_info(struct pci_dev *dev, struct ocxl_fn_config *fn)
142{
143 int pos;
144
145 if (fn->max_afu_index < 0) {
146 fn->dvsec_afu_info_pos = -1;
147 return 0;
148 }
149
150 pos = find_dvsec(dev, OCXL_DVSEC_AFU_INFO_ID);
151 if (!pos) {
152 dev_err(&dev->dev, "Can't find AFU information DVSEC\n");
153 return -ENODEV;
154 }
155 fn->dvsec_afu_info_pos = pos;
156 return 0;
157}
158
159static int read_dvsec_vendor(struct pci_dev *dev)
160{
161 int pos;
162 u32 cfg, tlx, dlx;
163
164 /*
165 * vendor specific DVSEC is optional
166 *
167 * It's currently only used on function 0 to specify the
168 * version of some logic blocks. Some older images may not
169 * even have it so we ignore any errors
170 */
171 if (PCI_FUNC(dev->devfn) != 0)
172 return 0;
173
174 pos = find_dvsec(dev, OCXL_DVSEC_VENDOR_ID);
175 if (!pos)
176 return 0;
177
178 pci_read_config_dword(dev, pos + OCXL_DVSEC_VENDOR_CFG_VERS, &cfg);
179 pci_read_config_dword(dev, pos + OCXL_DVSEC_VENDOR_TLX_VERS, &tlx);
180 pci_read_config_dword(dev, pos + OCXL_DVSEC_VENDOR_DLX_VERS, &dlx);
181
182 dev_dbg(&dev->dev, "Vendor specific DVSEC:\n");
183 dev_dbg(&dev->dev, " CFG version = 0x%x\n", cfg);
184 dev_dbg(&dev->dev, " TLX version = 0x%x\n", tlx);
185 dev_dbg(&dev->dev, " DLX version = 0x%x\n", dlx);
186 return 0;
187}
188
189static int validate_function(struct pci_dev *dev, struct ocxl_fn_config *fn)
190{
191 if (fn->max_pasid_log == -1 && fn->max_afu_index >= 0) {
192 dev_err(&dev->dev,
193 "AFUs are defined but no PASIDs are requested\n");
194 return -EINVAL;
195 }
196
197 if (fn->max_afu_index > OCXL_MAX_AFU_PER_FUNCTION) {
198 dev_err(&dev->dev,
199 "Max AFU index out of architectural limit (%d vs %d)\n",
200 fn->max_afu_index, OCXL_MAX_AFU_PER_FUNCTION);
201 return -EINVAL;
202 }
203 return 0;
204}
205
206int ocxl_config_read_function(struct pci_dev *dev, struct ocxl_fn_config *fn)
207{
208 int rc;
209
210 read_pasid(dev, fn);
211
212 rc = read_dvsec_tl(dev, fn);
213 if (rc) {
214 dev_err(&dev->dev,
215 "Invalid Transaction Layer DVSEC configuration: %d\n",
216 rc);
217 return -ENODEV;
218 }
219
220 rc = read_dvsec_function(dev, fn);
221 if (rc) {
222 dev_err(&dev->dev,
223 "Invalid Function DVSEC configuration: %d\n", rc);
224 return -ENODEV;
225 }
226
227 rc = read_dvsec_afu_info(dev, fn);
228 if (rc) {
229 dev_err(&dev->dev, "Invalid AFU configuration: %d\n", rc);
230 return -ENODEV;
231 }
232
233 rc = read_dvsec_vendor(dev);
234 if (rc) {
235 dev_err(&dev->dev,
236 "Invalid vendor specific DVSEC configuration: %d\n",
237 rc);
238 return -ENODEV;
239 }
240
241 rc = validate_function(dev, fn);
242 return rc;
243}
244EXPORT_SYMBOL_GPL(ocxl_config_read_function);
245
246static int read_afu_info(struct pci_dev *dev, struct ocxl_fn_config *fn,
247 int offset, u32 *data)
248{
249 u32 val;
250 unsigned long timeout = jiffies + (HZ * OCXL_CFG_TIMEOUT);
251 int pos = fn->dvsec_afu_info_pos;
252
253 /* Protect 'data valid' bit */
254 if (EXTRACT_BIT(offset, 31)) {
255 dev_err(&dev->dev, "Invalid offset in AFU info DVSEC\n");
256 return -EINVAL;
257 }
258
259 pci_write_config_dword(dev, pos + OCXL_DVSEC_AFU_INFO_OFF, offset);
260 pci_read_config_dword(dev, pos + OCXL_DVSEC_AFU_INFO_OFF, &val);
261 while (!EXTRACT_BIT(val, 31)) {
262 if (time_after_eq(jiffies, timeout)) {
263 dev_err(&dev->dev,
264 "Timeout while reading AFU info DVSEC (offset=%d)\n",
265 offset);
266 return -EBUSY;
267 }
268 cpu_relax();
269 pci_read_config_dword(dev, pos + OCXL_DVSEC_AFU_INFO_OFF, &val);
270 }
271 pci_read_config_dword(dev, pos + OCXL_DVSEC_AFU_INFO_DATA, data);
272 return 0;
273}
274
275/**
276 * Read the template version from the AFU
277 * dev: the device for the AFU
278 * fn: the AFU offsets
279 * len: outputs the template length
280 * version: outputs the major<<8,minor version
281 *
282 * Returns 0 on success, negative on failure
283 */
284static int read_template_version(struct pci_dev *dev, struct ocxl_fn_config *fn,
285 u16 *len, u16 *version)
286{
287 u32 val32;
288 u8 major, minor;
289 int rc;
290
291 rc = read_afu_info(dev, fn, OCXL_DVSEC_TEMPL_VERSION, &val32);
292 if (rc)
293 return rc;
294
295 *len = EXTRACT_BITS(val32, 16, 31);
296 major = EXTRACT_BITS(val32, 8, 15);
297 minor = EXTRACT_BITS(val32, 0, 7);
298 *version = (major << 8) + minor;
299 return 0;
300}
301
302int ocxl_config_check_afu_index(struct pci_dev *dev,
303 struct ocxl_fn_config *fn, int afu_idx)
304{
305 int rc;
306 u16 templ_version;
307 u16 len, expected_len;
308
309 pci_write_config_byte(dev,
310 fn->dvsec_afu_info_pos + OCXL_DVSEC_AFU_INFO_AFU_IDX,
311 afu_idx);
312
313 rc = read_template_version(dev, fn, &len, &templ_version);
314 if (rc)
315 return rc;
316
317 /* AFU index map can have holes, in which case we read all 0's */
318 if (!templ_version && !len)
319 return 0;
320
321 dev_dbg(&dev->dev, "AFU descriptor template version %d.%d\n",
322 templ_version >> 8, templ_version & 0xFF);
323
324 switch (templ_version) {
325 case 0x0005: // v0.5 was used prior to the spec approval
326 case 0x0100:
327 expected_len = OCXL_TEMPL_LEN_1_0;
328 break;
329 case 0x0101:
330 expected_len = OCXL_TEMPL_LEN_1_1;
331 break;
332 default:
333 dev_warn(&dev->dev, "Unknown AFU template version %#x\n",
334 templ_version);
335 expected_len = len;
336 }
337 if (len != expected_len)
338 dev_warn(&dev->dev,
339 "Unexpected template length %#x in AFU information, expected %#x for version %#x\n",
340 len, expected_len, templ_version);
341 return 1;
342}
343
344static int read_afu_name(struct pci_dev *dev, struct ocxl_fn_config *fn,
345 struct ocxl_afu_config *afu)
346{
347 int i, rc;
348 u32 val, *ptr;
349
350 BUILD_BUG_ON(OCXL_AFU_NAME_SZ < OCXL_TEMPL_NAME_LEN);
351 for (i = 0; i < OCXL_TEMPL_NAME_LEN; i += 4) {
352 rc = read_afu_info(dev, fn, OCXL_DVSEC_TEMPL_NAME + i, &val);
353 if (rc)
354 return rc;
355 ptr = (u32 *) &afu->name[i];
356 *ptr = le32_to_cpu((__force __le32) val);
357 }
358 afu->name[OCXL_AFU_NAME_SZ - 1] = '\0'; /* play safe */
359 return 0;
360}
361
362static int read_afu_mmio(struct pci_dev *dev, struct ocxl_fn_config *fn,
363 struct ocxl_afu_config *afu)
364{
365 int rc;
366 u32 val;
367
368 /*
369 * Global MMIO
370 */
371 rc = read_afu_info(dev, fn, OCXL_DVSEC_TEMPL_MMIO_GLOBAL, &val);
372 if (rc)
373 return rc;
374 afu->global_mmio_bar = EXTRACT_BITS(val, 0, 2);
375 afu->global_mmio_offset = EXTRACT_BITS(val, 16, 31) << 16;
376
377 rc = read_afu_info(dev, fn, OCXL_DVSEC_TEMPL_MMIO_GLOBAL + 4, &val);
378 if (rc)
379 return rc;
380 afu->global_mmio_offset += (u64) val << 32;
381
382 rc = read_afu_info(dev, fn, OCXL_DVSEC_TEMPL_MMIO_GLOBAL_SZ, &val);
383 if (rc)
384 return rc;
385 afu->global_mmio_size = val;
386
387 /*
388 * Per-process MMIO
389 */
390 rc = read_afu_info(dev, fn, OCXL_DVSEC_TEMPL_MMIO_PP, &val);
391 if (rc)
392 return rc;
393 afu->pp_mmio_bar = EXTRACT_BITS(val, 0, 2);
394 afu->pp_mmio_offset = EXTRACT_BITS(val, 16, 31) << 16;
395
396 rc = read_afu_info(dev, fn, OCXL_DVSEC_TEMPL_MMIO_PP + 4, &val);
397 if (rc)
398 return rc;
399 afu->pp_mmio_offset += (u64) val << 32;
400
401 rc = read_afu_info(dev, fn, OCXL_DVSEC_TEMPL_MMIO_PP_SZ, &val);
402 if (rc)
403 return rc;
404 afu->pp_mmio_stride = val;
405
406 return 0;
407}
408
409static int read_afu_control(struct pci_dev *dev, struct ocxl_afu_config *afu)
410{
411 int pos;
412 u8 val8;
413 u16 val16;
414
415 pos = find_dvsec_afu_ctrl(dev, afu->idx);
416 if (!pos) {
417 dev_err(&dev->dev, "Can't find AFU control DVSEC for AFU %d\n",
418 afu->idx);
419 return -ENODEV;
420 }
421 afu->dvsec_afu_control_pos = pos;
422
423 pci_read_config_byte(dev, pos + OCXL_DVSEC_AFU_CTRL_PASID_SUP, &val8);
424 afu->pasid_supported_log = EXTRACT_BITS(val8, 0, 4);
425
426 pci_read_config_word(dev, pos + OCXL_DVSEC_AFU_CTRL_ACTAG_SUP, &val16);
427 afu->actag_supported = EXTRACT_BITS(val16, 0, 11);
428 return 0;
429}
430
431static bool char_allowed(int c)
432{
433 /*
434 * Permitted Characters : Alphanumeric, hyphen, underscore, comma
435 */
436 if ((c >= 0x30 && c <= 0x39) /* digits */ ||
437 (c >= 0x41 && c <= 0x5A) /* upper case */ ||
438 (c >= 0x61 && c <= 0x7A) /* lower case */ ||
439 c == 0 /* NULL */ ||
440 c == 0x2D /* - */ ||
441 c == 0x5F /* _ */ ||
442 c == 0x2C /* , */)
443 return true;
444 return false;
445}
446
447static int validate_afu(struct pci_dev *dev, struct ocxl_afu_config *afu)
448{
449 int i;
450
451 if (!afu->name[0]) {
452 dev_err(&dev->dev, "Empty AFU name\n");
453 return -EINVAL;
454 }
455 for (i = 0; i < OCXL_TEMPL_NAME_LEN; i++) {
456 if (!char_allowed(afu->name[i])) {
457 dev_err(&dev->dev,
458 "Invalid character in AFU name\n");
459 return -EINVAL;
460 }
461 }
462
463 if (afu->global_mmio_bar != 0 &&
464 afu->global_mmio_bar != 2 &&
465 afu->global_mmio_bar != 4) {
466 dev_err(&dev->dev, "Invalid global MMIO bar number\n");
467 return -EINVAL;
468 }
469 if (afu->pp_mmio_bar != 0 &&
470 afu->pp_mmio_bar != 2 &&
471 afu->pp_mmio_bar != 4) {
472 dev_err(&dev->dev, "Invalid per-process MMIO bar number\n");
473 return -EINVAL;
474 }
475 return 0;
476}
477
478/**
479 * Populate AFU metadata regarding LPC memory
480 * dev: the device for the AFU
481 * fn: the AFU offsets
482 * afu: the AFU struct to populate the LPC metadata into
483 *
484 * Returns 0 on success, negative on failure
485 */
486static int read_afu_lpc_memory_info(struct pci_dev *dev,
487 struct ocxl_fn_config *fn,
488 struct ocxl_afu_config *afu)
489{
490 int rc;
491 u32 val32;
492 u16 templ_version;
493 u16 templ_len;
494 u64 total_mem_size = 0;
495 u64 lpc_mem_size = 0;
496
497 afu->lpc_mem_offset = 0;
498 afu->lpc_mem_size = 0;
499 afu->special_purpose_mem_offset = 0;
500 afu->special_purpose_mem_size = 0;
501 /*
502 * For AFUs following template v1.0, the LPC memory covers the
503 * total memory. Its size is a power of 2.
504 *
505 * For AFUs with template >= v1.01, the total memory size is
506 * still a power of 2, but it is split in 2 parts:
507 * - the LPC memory, whose size can now be anything
508 * - the remainder memory is a special purpose memory, whose
509 * definition is AFU-dependent. It is not accessible through
510 * the usual commands for LPC memory
511 */
512 rc = read_afu_info(dev, fn, OCXL_DVSEC_TEMPL_ALL_MEM_SZ, &val32);
513 if (rc)
514 return rc;
515
516 val32 = EXTRACT_BITS(val32, 0, 7);
517 if (!val32)
518 return 0; /* No LPC memory */
519
520 /*
521 * The configuration space spec allows for a memory size of up
522 * to 2^255 bytes.
523 *
524 * Current generation hardware uses 56-bit physical addresses,
525 * but we won't be able to get near close to that, as we won't
526 * have a hole big enough in the memory map. Let it pass in
527 * the driver for now. We'll get an error from the firmware
528 * when trying to configure something too big.
529 */
530 total_mem_size = 1ull << val32;
531
532 rc = read_afu_info(dev, fn, OCXL_DVSEC_TEMPL_LPC_MEM_START, &val32);
533 if (rc)
534 return rc;
535
536 afu->lpc_mem_offset = val32;
537
538 rc = read_afu_info(dev, fn, OCXL_DVSEC_TEMPL_LPC_MEM_START + 4, &val32);
539 if (rc)
540 return rc;
541
542 afu->lpc_mem_offset |= (u64) val32 << 32;
543
544 rc = read_template_version(dev, fn, &templ_len, &templ_version);
545 if (rc)
546 return rc;
547
548 if (templ_version >= 0x0101) {
549 rc = read_afu_info(dev, fn,
550 OCXL_DVSEC_TEMPL_LPC_MEM_SZ, &val32);
551 if (rc)
552 return rc;
553 lpc_mem_size = val32;
554
555 rc = read_afu_info(dev, fn,
556 OCXL_DVSEC_TEMPL_LPC_MEM_SZ + 4, &val32);
557 if (rc)
558 return rc;
559 lpc_mem_size |= (u64) val32 << 32;
560 } else {
561 lpc_mem_size = total_mem_size;
562 }
563 afu->lpc_mem_size = lpc_mem_size;
564
565 if (lpc_mem_size < total_mem_size) {
566 afu->special_purpose_mem_offset =
567 afu->lpc_mem_offset + lpc_mem_size;
568 afu->special_purpose_mem_size =
569 total_mem_size - lpc_mem_size;
570 }
571 return 0;
572}
573
574int ocxl_config_read_afu(struct pci_dev *dev, struct ocxl_fn_config *fn,
575 struct ocxl_afu_config *afu, u8 afu_idx)
576{
577 int rc;
578 u32 val32;
579
580 /*
581 * First, we need to write the AFU idx for the AFU we want to
582 * access.
583 */
584 WARN_ON((afu_idx & OCXL_DVSEC_AFU_IDX_MASK) != afu_idx);
585 afu->idx = afu_idx;
586 pci_write_config_byte(dev,
587 fn->dvsec_afu_info_pos + OCXL_DVSEC_AFU_INFO_AFU_IDX,
588 afu->idx);
589
590 rc = read_afu_name(dev, fn, afu);
591 if (rc)
592 return rc;
593
594 rc = read_afu_info(dev, fn, OCXL_DVSEC_TEMPL_AFU_VERSION, &val32);
595 if (rc)
596 return rc;
597 afu->version_major = EXTRACT_BITS(val32, 24, 31);
598 afu->version_minor = EXTRACT_BITS(val32, 16, 23);
599 afu->afuc_type = EXTRACT_BITS(val32, 14, 15);
600 afu->afum_type = EXTRACT_BITS(val32, 12, 13);
601 afu->profile = EXTRACT_BITS(val32, 0, 7);
602
603 rc = read_afu_mmio(dev, fn, afu);
604 if (rc)
605 return rc;
606
607 rc = read_afu_lpc_memory_info(dev, fn, afu);
608 if (rc)
609 return rc;
610
611 rc = read_afu_control(dev, afu);
612 if (rc)
613 return rc;
614
615 dev_dbg(&dev->dev, "AFU configuration:\n");
616 dev_dbg(&dev->dev, " name = %s\n", afu->name);
617 dev_dbg(&dev->dev, " version = %d.%d\n", afu->version_major,
618 afu->version_minor);
619 dev_dbg(&dev->dev, " global mmio bar = %hhu\n", afu->global_mmio_bar);
620 dev_dbg(&dev->dev, " global mmio offset = %#llx\n",
621 afu->global_mmio_offset);
622 dev_dbg(&dev->dev, " global mmio size = %#x\n", afu->global_mmio_size);
623 dev_dbg(&dev->dev, " pp mmio bar = %hhu\n", afu->pp_mmio_bar);
624 dev_dbg(&dev->dev, " pp mmio offset = %#llx\n", afu->pp_mmio_offset);
625 dev_dbg(&dev->dev, " pp mmio stride = %#x\n", afu->pp_mmio_stride);
626 dev_dbg(&dev->dev, " lpc_mem offset = %#llx\n", afu->lpc_mem_offset);
627 dev_dbg(&dev->dev, " lpc_mem size = %#llx\n", afu->lpc_mem_size);
628 dev_dbg(&dev->dev, " special purpose mem offset = %#llx\n",
629 afu->special_purpose_mem_offset);
630 dev_dbg(&dev->dev, " special purpose mem size = %#llx\n",
631 afu->special_purpose_mem_size);
632 dev_dbg(&dev->dev, " pasid supported (log) = %u\n",
633 afu->pasid_supported_log);
634 dev_dbg(&dev->dev, " actag supported = %u\n",
635 afu->actag_supported);
636
637 rc = validate_afu(dev, afu);
638 return rc;
639}
640EXPORT_SYMBOL_GPL(ocxl_config_read_afu);
641
642int ocxl_config_get_actag_info(struct pci_dev *dev, u16 *base, u16 *enabled,
643 u16 *supported)
644{
645 int rc;
646
647 /*
648 * This is really a simple wrapper for the kernel API, to
649 * avoid an external driver using ocxl as a library to call
650 * platform-dependent code
651 */
652 rc = pnv_ocxl_get_actag(dev, base, enabled, supported);
653 if (rc) {
654 dev_err(&dev->dev, "Can't get actag for device: %d\n", rc);
655 return rc;
656 }
657 return 0;
658}
659EXPORT_SYMBOL_GPL(ocxl_config_get_actag_info);
660
661void ocxl_config_set_afu_actag(struct pci_dev *dev, int pos, int actag_base,
662 int actag_count)
663{
664 u16 val;
665
666 val = actag_count & OCXL_DVSEC_ACTAG_MASK;
667 pci_write_config_byte(dev, pos + OCXL_DVSEC_AFU_CTRL_ACTAG_EN, val);
668
669 val = actag_base & OCXL_DVSEC_ACTAG_MASK;
670 pci_write_config_dword(dev, pos + OCXL_DVSEC_AFU_CTRL_ACTAG_BASE, val);
671}
672EXPORT_SYMBOL_GPL(ocxl_config_set_afu_actag);
673
674int ocxl_config_get_pasid_info(struct pci_dev *dev, int *count)
675{
676 return pnv_ocxl_get_pasid_count(dev, count);
677}
678
679void ocxl_config_set_afu_pasid(struct pci_dev *dev, int pos, int pasid_base,
680 u32 pasid_count_log)
681{
682 u8 val8;
683 u32 val32;
684
685 val8 = pasid_count_log & OCXL_DVSEC_PASID_LOG_MASK;
686 pci_write_config_byte(dev, pos + OCXL_DVSEC_AFU_CTRL_PASID_EN, val8);
687
688 pci_read_config_dword(dev, pos + OCXL_DVSEC_AFU_CTRL_PASID_BASE,
689 &val32);
690 val32 &= ~OCXL_DVSEC_PASID_MASK;
691 val32 |= pasid_base & OCXL_DVSEC_PASID_MASK;
692 pci_write_config_dword(dev, pos + OCXL_DVSEC_AFU_CTRL_PASID_BASE,
693 val32);
694}
695EXPORT_SYMBOL_GPL(ocxl_config_set_afu_pasid);
696
697void ocxl_config_set_afu_state(struct pci_dev *dev, int pos, int enable)
698{
699 u8 val;
700
701 pci_read_config_byte(dev, pos + OCXL_DVSEC_AFU_CTRL_ENABLE, &val);
702 if (enable)
703 val |= 1;
704 else
705 val &= 0xFE;
706 pci_write_config_byte(dev, pos + OCXL_DVSEC_AFU_CTRL_ENABLE, val);
707}
708EXPORT_SYMBOL_GPL(ocxl_config_set_afu_state);
709
710int ocxl_config_set_TL(struct pci_dev *dev, int tl_dvsec)
711{
712 u32 val;
713 __be32 *be32ptr;
714 u8 timers;
715 int i, rc;
716 long recv_cap;
717 char *recv_rate;
718
719 /*
720 * Skip on function != 0, as the TL can only be defined on 0
721 */
722 if (PCI_FUNC(dev->devfn) != 0)
723 return 0;
724
725 recv_rate = kzalloc(PNV_OCXL_TL_RATE_BUF_SIZE, GFP_KERNEL);
726 if (!recv_rate)
727 return -ENOMEM;
728 /*
729 * The spec defines 64 templates for messages in the
730 * Transaction Layer (TL).
731 *
732 * The host and device each support a subset, so we need to
733 * configure the transmitters on each side to send only
734 * templates the receiver understands, at a rate the receiver
735 * can process. Per the spec, template 0 must be supported by
736 * everybody. That's the template which has been used by the
737 * host and device so far.
738 *
739 * The sending rate limit must be set before the template is
740 * enabled.
741 */
742
743 /*
744 * Device -> host
745 */
746 rc = pnv_ocxl_get_tl_cap(dev, &recv_cap, recv_rate,
747 PNV_OCXL_TL_RATE_BUF_SIZE);
748 if (rc)
749 goto out;
750
751 for (i = 0; i < PNV_OCXL_TL_RATE_BUF_SIZE; i += 4) {
752 be32ptr = (__be32 *) &recv_rate[i];
753 pci_write_config_dword(dev,
754 tl_dvsec + OCXL_DVSEC_TL_SEND_RATE + i,
755 be32_to_cpu(*be32ptr));
756 }
757 val = recv_cap >> 32;
758 pci_write_config_dword(dev, tl_dvsec + OCXL_DVSEC_TL_SEND_CAP, val);
759 val = recv_cap & GENMASK(31, 0);
760 pci_write_config_dword(dev, tl_dvsec + OCXL_DVSEC_TL_SEND_CAP + 4, val);
761
762 /*
763 * Host -> device
764 */
765 for (i = 0; i < PNV_OCXL_TL_RATE_BUF_SIZE; i += 4) {
766 pci_read_config_dword(dev,
767 tl_dvsec + OCXL_DVSEC_TL_RECV_RATE + i,
768 &val);
769 be32ptr = (__be32 *) &recv_rate[i];
770 *be32ptr = cpu_to_be32(val);
771 }
772 pci_read_config_dword(dev, tl_dvsec + OCXL_DVSEC_TL_RECV_CAP, &val);
773 recv_cap = (long) val << 32;
774 pci_read_config_dword(dev, tl_dvsec + OCXL_DVSEC_TL_RECV_CAP + 4, &val);
775 recv_cap |= val;
776
777 rc = pnv_ocxl_set_tl_conf(dev, recv_cap, __pa(recv_rate),
778 PNV_OCXL_TL_RATE_BUF_SIZE);
779 if (rc)
780 goto out;
781
782 /*
783 * Opencapi commands needing to be retried are classified per
784 * the TL in 2 groups: short and long commands.
785 *
786 * The short back off timer it not used for now. It will be
787 * for opencapi 4.0.
788 *
789 * The long back off timer is typically used when an AFU hits
790 * a page fault but the NPU is already processing one. So the
791 * AFU needs to wait before it can resubmit. Having a value
792 * too low doesn't break anything, but can generate extra
793 * traffic on the link.
794 * We set it to 1.6 us for now. It's shorter than, but in the
795 * same order of magnitude as the time spent to process a page
796 * fault.
797 */
798 timers = 0x2 << 4; /* long timer = 1.6 us */
799 pci_write_config_byte(dev, tl_dvsec + OCXL_DVSEC_TL_BACKOFF_TIMERS,
800 timers);
801
802 rc = 0;
803out:
804 kfree(recv_rate);
805 return rc;
806}
807EXPORT_SYMBOL_GPL(ocxl_config_set_TL);
808
809int ocxl_config_terminate_pasid(struct pci_dev *dev, int afu_control, int pasid)
810{
811 u32 val;
812 unsigned long timeout;
813
814 pci_read_config_dword(dev, afu_control + OCXL_DVSEC_AFU_CTRL_TERM_PASID,
815 &val);
816 if (EXTRACT_BIT(val, 20)) {
817 dev_err(&dev->dev,
818 "Can't terminate PASID %#x, previous termination didn't complete\n",
819 pasid);
820 return -EBUSY;
821 }
822
823 val &= ~OCXL_DVSEC_PASID_MASK;
824 val |= pasid & OCXL_DVSEC_PASID_MASK;
825 val |= BIT(20);
826 pci_write_config_dword(dev,
827 afu_control + OCXL_DVSEC_AFU_CTRL_TERM_PASID,
828 val);
829
830 timeout = jiffies + (HZ * OCXL_CFG_TIMEOUT);
831 pci_read_config_dword(dev, afu_control + OCXL_DVSEC_AFU_CTRL_TERM_PASID,
832 &val);
833 while (EXTRACT_BIT(val, 20)) {
834 if (time_after_eq(jiffies, timeout)) {
835 dev_err(&dev->dev,
836 "Timeout while waiting for AFU to terminate PASID %#x\n",
837 pasid);
838 return -EBUSY;
839 }
840 cpu_relax();
841 pci_read_config_dword(dev,
842 afu_control + OCXL_DVSEC_AFU_CTRL_TERM_PASID,
843 &val);
844 }
845 return 0;
846}
847EXPORT_SYMBOL_GPL(ocxl_config_terminate_pasid);
848
849void ocxl_config_set_actag(struct pci_dev *dev, int func_dvsec, u32 tag_first,
850 u32 tag_count)
851{
852 u32 val;
853
854 val = (tag_first & OCXL_DVSEC_ACTAG_MASK) << 16;
855 val |= tag_count & OCXL_DVSEC_ACTAG_MASK;
856 pci_write_config_dword(dev, func_dvsec + OCXL_DVSEC_FUNC_OFF_ACTAG,
857 val);
858}
859EXPORT_SYMBOL_GPL(ocxl_config_set_actag);