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1/*
2 * at24.c - handle most I2C EEPROMs
3 *
4 * Copyright (C) 2005-2007 David Brownell
5 * Copyright (C) 2008 Wolfram Sang, Pengutronix
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 */
12#include <linux/kernel.h>
13#include <linux/init.h>
14#include <linux/module.h>
15#include <linux/slab.h>
16#include <linux/delay.h>
17#include <linux/mutex.h>
18#include <linux/sysfs.h>
19#include <linux/mod_devicetable.h>
20#include <linux/log2.h>
21#include <linux/bitops.h>
22#include <linux/jiffies.h>
23#include <linux/of.h>
24#include <linux/i2c.h>
25#include <linux/i2c/at24.h>
26
27/*
28 * I2C EEPROMs from most vendors are inexpensive and mostly interchangeable.
29 * Differences between different vendor product lines (like Atmel AT24C or
30 * MicroChip 24LC, etc) won't much matter for typical read/write access.
31 * There are also I2C RAM chips, likewise interchangeable. One example
32 * would be the PCF8570, which acts like a 24c02 EEPROM (256 bytes).
33 *
34 * However, misconfiguration can lose data. "Set 16-bit memory address"
35 * to a part with 8-bit addressing will overwrite data. Writing with too
36 * big a page size also loses data. And it's not safe to assume that the
37 * conventional addresses 0x50..0x57 only hold eeproms; a PCF8563 RTC
38 * uses 0x51, for just one example.
39 *
40 * Accordingly, explicit board-specific configuration data should be used
41 * in almost all cases. (One partial exception is an SMBus used to access
42 * "SPD" data for DRAM sticks. Those only use 24c02 EEPROMs.)
43 *
44 * So this driver uses "new style" I2C driver binding, expecting to be
45 * told what devices exist. That may be in arch/X/mach-Y/board-Z.c or
46 * similar kernel-resident tables; or, configuration data coming from
47 * a bootloader.
48 *
49 * Other than binding model, current differences from "eeprom" driver are
50 * that this one handles write access and isn't restricted to 24c02 devices.
51 * It also handles larger devices (32 kbit and up) with two-byte addresses,
52 * which won't work on pure SMBus systems.
53 */
54
55struct at24_data {
56 struct at24_platform_data chip;
57 struct memory_accessor macc;
58 int use_smbus;
59
60 /*
61 * Lock protects against activities from other Linux tasks,
62 * but not from changes by other I2C masters.
63 */
64 struct mutex lock;
65 struct bin_attribute bin;
66
67 u8 *writebuf;
68 unsigned write_max;
69 unsigned num_addresses;
70
71 /*
72 * Some chips tie up multiple I2C addresses; dummy devices reserve
73 * them for us, and we'll use them with SMBus calls.
74 */
75 struct i2c_client *client[];
76};
77
78/*
79 * This parameter is to help this driver avoid blocking other drivers out
80 * of I2C for potentially troublesome amounts of time. With a 100 kHz I2C
81 * clock, one 256 byte read takes about 1/43 second which is excessive;
82 * but the 1/170 second it takes at 400 kHz may be quite reasonable; and
83 * at 1 MHz (Fm+) a 1/430 second delay could easily be invisible.
84 *
85 * This value is forced to be a power of two so that writes align on pages.
86 */
87static unsigned io_limit = 128;
88module_param(io_limit, uint, 0);
89MODULE_PARM_DESC(io_limit, "Maximum bytes per I/O (default 128)");
90
91/*
92 * Specs often allow 5 msec for a page write, sometimes 20 msec;
93 * it's important to recover from write timeouts.
94 */
95static unsigned write_timeout = 25;
96module_param(write_timeout, uint, 0);
97MODULE_PARM_DESC(write_timeout, "Time (in ms) to try writes (default 25)");
98
99#define AT24_SIZE_BYTELEN 5
100#define AT24_SIZE_FLAGS 8
101
102#define AT24_BITMASK(x) (BIT(x) - 1)
103
104/* create non-zero magic value for given eeprom parameters */
105#define AT24_DEVICE_MAGIC(_len, _flags) \
106 ((1 << AT24_SIZE_FLAGS | (_flags)) \
107 << AT24_SIZE_BYTELEN | ilog2(_len))
108
109static const struct i2c_device_id at24_ids[] = {
110 /* needs 8 addresses as A0-A2 are ignored */
111 { "24c00", AT24_DEVICE_MAGIC(128 / 8, AT24_FLAG_TAKE8ADDR) },
112 /* old variants can't be handled with this generic entry! */
113 { "24c01", AT24_DEVICE_MAGIC(1024 / 8, 0) },
114 { "24c02", AT24_DEVICE_MAGIC(2048 / 8, 0) },
115 /* spd is a 24c02 in memory DIMMs */
116 { "spd", AT24_DEVICE_MAGIC(2048 / 8,
117 AT24_FLAG_READONLY | AT24_FLAG_IRUGO) },
118 { "24c04", AT24_DEVICE_MAGIC(4096 / 8, 0) },
119 /* 24rf08 quirk is handled at i2c-core */
120 { "24c08", AT24_DEVICE_MAGIC(8192 / 8, 0) },
121 { "24c16", AT24_DEVICE_MAGIC(16384 / 8, 0) },
122 { "24c32", AT24_DEVICE_MAGIC(32768 / 8, AT24_FLAG_ADDR16) },
123 { "24c64", AT24_DEVICE_MAGIC(65536 / 8, AT24_FLAG_ADDR16) },
124 { "24c128", AT24_DEVICE_MAGIC(131072 / 8, AT24_FLAG_ADDR16) },
125 { "24c256", AT24_DEVICE_MAGIC(262144 / 8, AT24_FLAG_ADDR16) },
126 { "24c512", AT24_DEVICE_MAGIC(524288 / 8, AT24_FLAG_ADDR16) },
127 { "24c1024", AT24_DEVICE_MAGIC(1048576 / 8, AT24_FLAG_ADDR16) },
128 { "at24", 0 },
129 { /* END OF LIST */ }
130};
131MODULE_DEVICE_TABLE(i2c, at24_ids);
132
133/*-------------------------------------------------------------------------*/
134
135/*
136 * This routine supports chips which consume multiple I2C addresses. It
137 * computes the addressing information to be used for a given r/w request.
138 * Assumes that sanity checks for offset happened at sysfs-layer.
139 */
140static struct i2c_client *at24_translate_offset(struct at24_data *at24,
141 unsigned *offset)
142{
143 unsigned i;
144
145 if (at24->chip.flags & AT24_FLAG_ADDR16) {
146 i = *offset >> 16;
147 *offset &= 0xffff;
148 } else {
149 i = *offset >> 8;
150 *offset &= 0xff;
151 }
152
153 return at24->client[i];
154}
155
156static ssize_t at24_eeprom_read(struct at24_data *at24, char *buf,
157 unsigned offset, size_t count)
158{
159 struct i2c_msg msg[2];
160 u8 msgbuf[2];
161 struct i2c_client *client;
162 unsigned long timeout, read_time;
163 int status, i;
164
165 memset(msg, 0, sizeof(msg));
166
167 /*
168 * REVISIT some multi-address chips don't rollover page reads to
169 * the next slave address, so we may need to truncate the count.
170 * Those chips might need another quirk flag.
171 *
172 * If the real hardware used four adjacent 24c02 chips and that
173 * were misconfigured as one 24c08, that would be a similar effect:
174 * one "eeprom" file not four, but larger reads would fail when
175 * they crossed certain pages.
176 */
177
178 /*
179 * Slave address and byte offset derive from the offset. Always
180 * set the byte address; on a multi-master board, another master
181 * may have changed the chip's "current" address pointer.
182 */
183 client = at24_translate_offset(at24, &offset);
184
185 if (count > io_limit)
186 count = io_limit;
187
188 switch (at24->use_smbus) {
189 case I2C_SMBUS_I2C_BLOCK_DATA:
190 /* Smaller eeproms can work given some SMBus extension calls */
191 if (count > I2C_SMBUS_BLOCK_MAX)
192 count = I2C_SMBUS_BLOCK_MAX;
193 break;
194 case I2C_SMBUS_WORD_DATA:
195 count = 2;
196 break;
197 case I2C_SMBUS_BYTE_DATA:
198 count = 1;
199 break;
200 default:
201 /*
202 * When we have a better choice than SMBus calls, use a
203 * combined I2C message. Write address; then read up to
204 * io_limit data bytes. Note that read page rollover helps us
205 * here (unlike writes). msgbuf is u8 and will cast to our
206 * needs.
207 */
208 i = 0;
209 if (at24->chip.flags & AT24_FLAG_ADDR16)
210 msgbuf[i++] = offset >> 8;
211 msgbuf[i++] = offset;
212
213 msg[0].addr = client->addr;
214 msg[0].buf = msgbuf;
215 msg[0].len = i;
216
217 msg[1].addr = client->addr;
218 msg[1].flags = I2C_M_RD;
219 msg[1].buf = buf;
220 msg[1].len = count;
221 }
222
223 /*
224 * Reads fail if the previous write didn't complete yet. We may
225 * loop a few times until this one succeeds, waiting at least
226 * long enough for one entire page write to work.
227 */
228 timeout = jiffies + msecs_to_jiffies(write_timeout);
229 do {
230 read_time = jiffies;
231 switch (at24->use_smbus) {
232 case I2C_SMBUS_I2C_BLOCK_DATA:
233 status = i2c_smbus_read_i2c_block_data(client, offset,
234 count, buf);
235 break;
236 case I2C_SMBUS_WORD_DATA:
237 status = i2c_smbus_read_word_data(client, offset);
238 if (status >= 0) {
239 buf[0] = status & 0xff;
240 buf[1] = status >> 8;
241 status = count;
242 }
243 break;
244 case I2C_SMBUS_BYTE_DATA:
245 status = i2c_smbus_read_byte_data(client, offset);
246 if (status >= 0) {
247 buf[0] = status;
248 status = count;
249 }
250 break;
251 default:
252 status = i2c_transfer(client->adapter, msg, 2);
253 if (status == 2)
254 status = count;
255 }
256 dev_dbg(&client->dev, "read %zu@%d --> %d (%ld)\n",
257 count, offset, status, jiffies);
258
259 if (status == count)
260 return count;
261
262 /* REVISIT: at HZ=100, this is sloooow */
263 msleep(1);
264 } while (time_before(read_time, timeout));
265
266 return -ETIMEDOUT;
267}
268
269static ssize_t at24_read(struct at24_data *at24,
270 char *buf, loff_t off, size_t count)
271{
272 ssize_t retval = 0;
273
274 if (unlikely(!count))
275 return count;
276
277 /*
278 * Read data from chip, protecting against concurrent updates
279 * from this host, but not from other I2C masters.
280 */
281 mutex_lock(&at24->lock);
282
283 while (count) {
284 ssize_t status;
285
286 status = at24_eeprom_read(at24, buf, off, count);
287 if (status <= 0) {
288 if (retval == 0)
289 retval = status;
290 break;
291 }
292 buf += status;
293 off += status;
294 count -= status;
295 retval += status;
296 }
297
298 mutex_unlock(&at24->lock);
299
300 return retval;
301}
302
303static ssize_t at24_bin_read(struct file *filp, struct kobject *kobj,
304 struct bin_attribute *attr,
305 char *buf, loff_t off, size_t count)
306{
307 struct at24_data *at24;
308
309 at24 = dev_get_drvdata(container_of(kobj, struct device, kobj));
310 return at24_read(at24, buf, off, count);
311}
312
313
314/*
315 * Note that if the hardware write-protect pin is pulled high, the whole
316 * chip is normally write protected. But there are plenty of product
317 * variants here, including OTP fuses and partial chip protect.
318 *
319 * We only use page mode writes; the alternative is sloooow. This routine
320 * writes at most one page.
321 */
322static ssize_t at24_eeprom_write(struct at24_data *at24, const char *buf,
323 unsigned offset, size_t count)
324{
325 struct i2c_client *client;
326 struct i2c_msg msg;
327 ssize_t status;
328 unsigned long timeout, write_time;
329 unsigned next_page;
330
331 /* Get corresponding I2C address and adjust offset */
332 client = at24_translate_offset(at24, &offset);
333
334 /* write_max is at most a page */
335 if (count > at24->write_max)
336 count = at24->write_max;
337
338 /* Never roll over backwards, to the start of this page */
339 next_page = roundup(offset + 1, at24->chip.page_size);
340 if (offset + count > next_page)
341 count = next_page - offset;
342
343 /* If we'll use I2C calls for I/O, set up the message */
344 if (!at24->use_smbus) {
345 int i = 0;
346
347 msg.addr = client->addr;
348 msg.flags = 0;
349
350 /* msg.buf is u8 and casts will mask the values */
351 msg.buf = at24->writebuf;
352 if (at24->chip.flags & AT24_FLAG_ADDR16)
353 msg.buf[i++] = offset >> 8;
354
355 msg.buf[i++] = offset;
356 memcpy(&msg.buf[i], buf, count);
357 msg.len = i + count;
358 }
359
360 /*
361 * Writes fail if the previous one didn't complete yet. We may
362 * loop a few times until this one succeeds, waiting at least
363 * long enough for one entire page write to work.
364 */
365 timeout = jiffies + msecs_to_jiffies(write_timeout);
366 do {
367 write_time = jiffies;
368 if (at24->use_smbus) {
369 status = i2c_smbus_write_i2c_block_data(client,
370 offset, count, buf);
371 if (status == 0)
372 status = count;
373 } else {
374 status = i2c_transfer(client->adapter, &msg, 1);
375 if (status == 1)
376 status = count;
377 }
378 dev_dbg(&client->dev, "write %zu@%d --> %zd (%ld)\n",
379 count, offset, status, jiffies);
380
381 if (status == count)
382 return count;
383
384 /* REVISIT: at HZ=100, this is sloooow */
385 msleep(1);
386 } while (time_before(write_time, timeout));
387
388 return -ETIMEDOUT;
389}
390
391static ssize_t at24_write(struct at24_data *at24, const char *buf, loff_t off,
392 size_t count)
393{
394 ssize_t retval = 0;
395
396 if (unlikely(!count))
397 return count;
398
399 /*
400 * Write data to chip, protecting against concurrent updates
401 * from this host, but not from other I2C masters.
402 */
403 mutex_lock(&at24->lock);
404
405 while (count) {
406 ssize_t status;
407
408 status = at24_eeprom_write(at24, buf, off, count);
409 if (status <= 0) {
410 if (retval == 0)
411 retval = status;
412 break;
413 }
414 buf += status;
415 off += status;
416 count -= status;
417 retval += status;
418 }
419
420 mutex_unlock(&at24->lock);
421
422 return retval;
423}
424
425static ssize_t at24_bin_write(struct file *filp, struct kobject *kobj,
426 struct bin_attribute *attr,
427 char *buf, loff_t off, size_t count)
428{
429 struct at24_data *at24;
430
431 at24 = dev_get_drvdata(container_of(kobj, struct device, kobj));
432 return at24_write(at24, buf, off, count);
433}
434
435/*-------------------------------------------------------------------------*/
436
437/*
438 * This lets other kernel code access the eeprom data. For example, it
439 * might hold a board's Ethernet address, or board-specific calibration
440 * data generated on the manufacturing floor.
441 */
442
443static ssize_t at24_macc_read(struct memory_accessor *macc, char *buf,
444 off_t offset, size_t count)
445{
446 struct at24_data *at24 = container_of(macc, struct at24_data, macc);
447
448 return at24_read(at24, buf, offset, count);
449}
450
451static ssize_t at24_macc_write(struct memory_accessor *macc, const char *buf,
452 off_t offset, size_t count)
453{
454 struct at24_data *at24 = container_of(macc, struct at24_data, macc);
455
456 return at24_write(at24, buf, offset, count);
457}
458
459/*-------------------------------------------------------------------------*/
460
461#ifdef CONFIG_OF
462static void at24_get_ofdata(struct i2c_client *client,
463 struct at24_platform_data *chip)
464{
465 const __be32 *val;
466 struct device_node *node = client->dev.of_node;
467
468 if (node) {
469 if (of_get_property(node, "read-only", NULL))
470 chip->flags |= AT24_FLAG_READONLY;
471 val = of_get_property(node, "pagesize", NULL);
472 if (val)
473 chip->page_size = be32_to_cpup(val);
474 }
475}
476#else
477static void at24_get_ofdata(struct i2c_client *client,
478 struct at24_platform_data *chip)
479{ }
480#endif /* CONFIG_OF */
481
482static int at24_probe(struct i2c_client *client, const struct i2c_device_id *id)
483{
484 struct at24_platform_data chip;
485 bool writable;
486 int use_smbus = 0;
487 struct at24_data *at24;
488 int err;
489 unsigned i, num_addresses;
490 kernel_ulong_t magic;
491
492 if (client->dev.platform_data) {
493 chip = *(struct at24_platform_data *)client->dev.platform_data;
494 } else {
495 if (!id->driver_data) {
496 err = -ENODEV;
497 goto err_out;
498 }
499 magic = id->driver_data;
500 chip.byte_len = BIT(magic & AT24_BITMASK(AT24_SIZE_BYTELEN));
501 magic >>= AT24_SIZE_BYTELEN;
502 chip.flags = magic & AT24_BITMASK(AT24_SIZE_FLAGS);
503 /*
504 * This is slow, but we can't know all eeproms, so we better
505 * play safe. Specifying custom eeprom-types via platform_data
506 * is recommended anyhow.
507 */
508 chip.page_size = 1;
509
510 /* update chipdata if OF is present */
511 at24_get_ofdata(client, &chip);
512
513 chip.setup = NULL;
514 chip.context = NULL;
515 }
516
517 if (!is_power_of_2(chip.byte_len))
518 dev_warn(&client->dev,
519 "byte_len looks suspicious (no power of 2)!\n");
520 if (!chip.page_size) {
521 dev_err(&client->dev, "page_size must not be 0!\n");
522 err = -EINVAL;
523 goto err_out;
524 }
525 if (!is_power_of_2(chip.page_size))
526 dev_warn(&client->dev,
527 "page_size looks suspicious (no power of 2)!\n");
528
529 /* Use I2C operations unless we're stuck with SMBus extensions. */
530 if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C)) {
531 if (chip.flags & AT24_FLAG_ADDR16) {
532 err = -EPFNOSUPPORT;
533 goto err_out;
534 }
535 if (i2c_check_functionality(client->adapter,
536 I2C_FUNC_SMBUS_READ_I2C_BLOCK)) {
537 use_smbus = I2C_SMBUS_I2C_BLOCK_DATA;
538 } else if (i2c_check_functionality(client->adapter,
539 I2C_FUNC_SMBUS_READ_WORD_DATA)) {
540 use_smbus = I2C_SMBUS_WORD_DATA;
541 } else if (i2c_check_functionality(client->adapter,
542 I2C_FUNC_SMBUS_READ_BYTE_DATA)) {
543 use_smbus = I2C_SMBUS_BYTE_DATA;
544 } else {
545 err = -EPFNOSUPPORT;
546 goto err_out;
547 }
548 }
549
550 if (chip.flags & AT24_FLAG_TAKE8ADDR)
551 num_addresses = 8;
552 else
553 num_addresses = DIV_ROUND_UP(chip.byte_len,
554 (chip.flags & AT24_FLAG_ADDR16) ? 65536 : 256);
555
556 at24 = kzalloc(sizeof(struct at24_data) +
557 num_addresses * sizeof(struct i2c_client *), GFP_KERNEL);
558 if (!at24) {
559 err = -ENOMEM;
560 goto err_out;
561 }
562
563 mutex_init(&at24->lock);
564 at24->use_smbus = use_smbus;
565 at24->chip = chip;
566 at24->num_addresses = num_addresses;
567
568 /*
569 * Export the EEPROM bytes through sysfs, since that's convenient.
570 * By default, only root should see the data (maybe passwords etc)
571 */
572 sysfs_bin_attr_init(&at24->bin);
573 at24->bin.attr.name = "eeprom";
574 at24->bin.attr.mode = chip.flags & AT24_FLAG_IRUGO ? S_IRUGO : S_IRUSR;
575 at24->bin.read = at24_bin_read;
576 at24->bin.size = chip.byte_len;
577
578 at24->macc.read = at24_macc_read;
579
580 writable = !(chip.flags & AT24_FLAG_READONLY);
581 if (writable) {
582 if (!use_smbus || i2c_check_functionality(client->adapter,
583 I2C_FUNC_SMBUS_WRITE_I2C_BLOCK)) {
584
585 unsigned write_max = chip.page_size;
586
587 at24->macc.write = at24_macc_write;
588
589 at24->bin.write = at24_bin_write;
590 at24->bin.attr.mode |= S_IWUSR;
591
592 if (write_max > io_limit)
593 write_max = io_limit;
594 if (use_smbus && write_max > I2C_SMBUS_BLOCK_MAX)
595 write_max = I2C_SMBUS_BLOCK_MAX;
596 at24->write_max = write_max;
597
598 /* buffer (data + address at the beginning) */
599 at24->writebuf = kmalloc(write_max + 2, GFP_KERNEL);
600 if (!at24->writebuf) {
601 err = -ENOMEM;
602 goto err_struct;
603 }
604 } else {
605 dev_warn(&client->dev,
606 "cannot write due to controller restrictions.");
607 }
608 }
609
610 at24->client[0] = client;
611
612 /* use dummy devices for multiple-address chips */
613 for (i = 1; i < num_addresses; i++) {
614 at24->client[i] = i2c_new_dummy(client->adapter,
615 client->addr + i);
616 if (!at24->client[i]) {
617 dev_err(&client->dev, "address 0x%02x unavailable\n",
618 client->addr + i);
619 err = -EADDRINUSE;
620 goto err_clients;
621 }
622 }
623
624 err = sysfs_create_bin_file(&client->dev.kobj, &at24->bin);
625 if (err)
626 goto err_clients;
627
628 i2c_set_clientdata(client, at24);
629
630 dev_info(&client->dev, "%zu byte %s EEPROM, %s, %u bytes/write\n",
631 at24->bin.size, client->name,
632 writable ? "writable" : "read-only", at24->write_max);
633 if (use_smbus == I2C_SMBUS_WORD_DATA ||
634 use_smbus == I2C_SMBUS_BYTE_DATA) {
635 dev_notice(&client->dev, "Falling back to %s reads, "
636 "performance will suffer\n", use_smbus ==
637 I2C_SMBUS_WORD_DATA ? "word" : "byte");
638 }
639
640 /* export data to kernel code */
641 if (chip.setup)
642 chip.setup(&at24->macc, chip.context);
643
644 return 0;
645
646err_clients:
647 for (i = 1; i < num_addresses; i++)
648 if (at24->client[i])
649 i2c_unregister_device(at24->client[i]);
650
651 kfree(at24->writebuf);
652err_struct:
653 kfree(at24);
654err_out:
655 dev_dbg(&client->dev, "probe error %d\n", err);
656 return err;
657}
658
659static int __devexit at24_remove(struct i2c_client *client)
660{
661 struct at24_data *at24;
662 int i;
663
664 at24 = i2c_get_clientdata(client);
665 sysfs_remove_bin_file(&client->dev.kobj, &at24->bin);
666
667 for (i = 1; i < at24->num_addresses; i++)
668 i2c_unregister_device(at24->client[i]);
669
670 kfree(at24->writebuf);
671 kfree(at24);
672 return 0;
673}
674
675/*-------------------------------------------------------------------------*/
676
677static struct i2c_driver at24_driver = {
678 .driver = {
679 .name = "at24",
680 .owner = THIS_MODULE,
681 },
682 .probe = at24_probe,
683 .remove = __devexit_p(at24_remove),
684 .id_table = at24_ids,
685};
686
687static int __init at24_init(void)
688{
689 if (!io_limit) {
690 pr_err("at24: io_limit must not be 0!\n");
691 return -EINVAL;
692 }
693
694 io_limit = rounddown_pow_of_two(io_limit);
695 return i2c_add_driver(&at24_driver);
696}
697module_init(at24_init);
698
699static void __exit at24_exit(void)
700{
701 i2c_del_driver(&at24_driver);
702}
703module_exit(at24_exit);
704
705MODULE_DESCRIPTION("Driver for most I2C EEPROMs");
706MODULE_AUTHOR("David Brownell and Wolfram Sang");
707MODULE_LICENSE("GPL");
1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * at24.c - handle most I2C EEPROMs
4 *
5 * Copyright (C) 2005-2007 David Brownell
6 * Copyright (C) 2008 Wolfram Sang, Pengutronix
7 */
8
9#include <linux/kernel.h>
10#include <linux/init.h>
11#include <linux/module.h>
12#include <linux/of_device.h>
13#include <linux/slab.h>
14#include <linux/delay.h>
15#include <linux/mutex.h>
16#include <linux/mod_devicetable.h>
17#include <linux/bitops.h>
18#include <linux/jiffies.h>
19#include <linux/property.h>
20#include <linux/acpi.h>
21#include <linux/i2c.h>
22#include <linux/nvmem-provider.h>
23#include <linux/regmap.h>
24#include <linux/pm_runtime.h>
25#include <linux/gpio/consumer.h>
26
27/* Address pointer is 16 bit. */
28#define AT24_FLAG_ADDR16 BIT(7)
29/* sysfs-entry will be read-only. */
30#define AT24_FLAG_READONLY BIT(6)
31/* sysfs-entry will be world-readable. */
32#define AT24_FLAG_IRUGO BIT(5)
33/* Take always 8 addresses (24c00). */
34#define AT24_FLAG_TAKE8ADDR BIT(4)
35/* Factory-programmed serial number. */
36#define AT24_FLAG_SERIAL BIT(3)
37/* Factory-programmed mac address. */
38#define AT24_FLAG_MAC BIT(2)
39/* Does not auto-rollover reads to the next slave address. */
40#define AT24_FLAG_NO_RDROL BIT(1)
41
42/*
43 * I2C EEPROMs from most vendors are inexpensive and mostly interchangeable.
44 * Differences between different vendor product lines (like Atmel AT24C or
45 * MicroChip 24LC, etc) won't much matter for typical read/write access.
46 * There are also I2C RAM chips, likewise interchangeable. One example
47 * would be the PCF8570, which acts like a 24c02 EEPROM (256 bytes).
48 *
49 * However, misconfiguration can lose data. "Set 16-bit memory address"
50 * to a part with 8-bit addressing will overwrite data. Writing with too
51 * big a page size also loses data. And it's not safe to assume that the
52 * conventional addresses 0x50..0x57 only hold eeproms; a PCF8563 RTC
53 * uses 0x51, for just one example.
54 *
55 * Accordingly, explicit board-specific configuration data should be used
56 * in almost all cases. (One partial exception is an SMBus used to access
57 * "SPD" data for DRAM sticks. Those only use 24c02 EEPROMs.)
58 *
59 * So this driver uses "new style" I2C driver binding, expecting to be
60 * told what devices exist. That may be in arch/X/mach-Y/board-Z.c or
61 * similar kernel-resident tables; or, configuration data coming from
62 * a bootloader.
63 *
64 * Other than binding model, current differences from "eeprom" driver are
65 * that this one handles write access and isn't restricted to 24c02 devices.
66 * It also handles larger devices (32 kbit and up) with two-byte addresses,
67 * which won't work on pure SMBus systems.
68 */
69
70struct at24_client {
71 struct i2c_client *client;
72 struct regmap *regmap;
73};
74
75struct at24_data {
76 /*
77 * Lock protects against activities from other Linux tasks,
78 * but not from changes by other I2C masters.
79 */
80 struct mutex lock;
81
82 unsigned int write_max;
83 unsigned int num_addresses;
84 unsigned int offset_adj;
85
86 u32 byte_len;
87 u16 page_size;
88 u8 flags;
89
90 struct nvmem_device *nvmem;
91
92 struct gpio_desc *wp_gpio;
93
94 /*
95 * Some chips tie up multiple I2C addresses; dummy devices reserve
96 * them for us, and we'll use them with SMBus calls.
97 */
98 struct at24_client client[];
99};
100
101/*
102 * This parameter is to help this driver avoid blocking other drivers out
103 * of I2C for potentially troublesome amounts of time. With a 100 kHz I2C
104 * clock, one 256 byte read takes about 1/43 second which is excessive;
105 * but the 1/170 second it takes at 400 kHz may be quite reasonable; and
106 * at 1 MHz (Fm+) a 1/430 second delay could easily be invisible.
107 *
108 * This value is forced to be a power of two so that writes align on pages.
109 */
110static unsigned int at24_io_limit = 128;
111module_param_named(io_limit, at24_io_limit, uint, 0);
112MODULE_PARM_DESC(at24_io_limit, "Maximum bytes per I/O (default 128)");
113
114/*
115 * Specs often allow 5 msec for a page write, sometimes 20 msec;
116 * it's important to recover from write timeouts.
117 */
118static unsigned int at24_write_timeout = 25;
119module_param_named(write_timeout, at24_write_timeout, uint, 0);
120MODULE_PARM_DESC(at24_write_timeout, "Time (in ms) to try writes (default 25)");
121
122struct at24_chip_data {
123 u32 byte_len;
124 u8 flags;
125};
126
127#define AT24_CHIP_DATA(_name, _len, _flags) \
128 static const struct at24_chip_data _name = { \
129 .byte_len = _len, .flags = _flags, \
130 }
131
132/* needs 8 addresses as A0-A2 are ignored */
133AT24_CHIP_DATA(at24_data_24c00, 128 / 8, AT24_FLAG_TAKE8ADDR);
134/* old variants can't be handled with this generic entry! */
135AT24_CHIP_DATA(at24_data_24c01, 1024 / 8, 0);
136AT24_CHIP_DATA(at24_data_24cs01, 16,
137 AT24_FLAG_SERIAL | AT24_FLAG_READONLY);
138AT24_CHIP_DATA(at24_data_24c02, 2048 / 8, 0);
139AT24_CHIP_DATA(at24_data_24cs02, 16,
140 AT24_FLAG_SERIAL | AT24_FLAG_READONLY);
141AT24_CHIP_DATA(at24_data_24mac402, 48 / 8,
142 AT24_FLAG_MAC | AT24_FLAG_READONLY);
143AT24_CHIP_DATA(at24_data_24mac602, 64 / 8,
144 AT24_FLAG_MAC | AT24_FLAG_READONLY);
145/* spd is a 24c02 in memory DIMMs */
146AT24_CHIP_DATA(at24_data_spd, 2048 / 8,
147 AT24_FLAG_READONLY | AT24_FLAG_IRUGO);
148AT24_CHIP_DATA(at24_data_24c04, 4096 / 8, 0);
149AT24_CHIP_DATA(at24_data_24cs04, 16,
150 AT24_FLAG_SERIAL | AT24_FLAG_READONLY);
151/* 24rf08 quirk is handled at i2c-core */
152AT24_CHIP_DATA(at24_data_24c08, 8192 / 8, 0);
153AT24_CHIP_DATA(at24_data_24cs08, 16,
154 AT24_FLAG_SERIAL | AT24_FLAG_READONLY);
155AT24_CHIP_DATA(at24_data_24c16, 16384 / 8, 0);
156AT24_CHIP_DATA(at24_data_24cs16, 16,
157 AT24_FLAG_SERIAL | AT24_FLAG_READONLY);
158AT24_CHIP_DATA(at24_data_24c32, 32768 / 8, AT24_FLAG_ADDR16);
159AT24_CHIP_DATA(at24_data_24cs32, 16,
160 AT24_FLAG_ADDR16 | AT24_FLAG_SERIAL | AT24_FLAG_READONLY);
161AT24_CHIP_DATA(at24_data_24c64, 65536 / 8, AT24_FLAG_ADDR16);
162AT24_CHIP_DATA(at24_data_24cs64, 16,
163 AT24_FLAG_ADDR16 | AT24_FLAG_SERIAL | AT24_FLAG_READONLY);
164AT24_CHIP_DATA(at24_data_24c128, 131072 / 8, AT24_FLAG_ADDR16);
165AT24_CHIP_DATA(at24_data_24c256, 262144 / 8, AT24_FLAG_ADDR16);
166AT24_CHIP_DATA(at24_data_24c512, 524288 / 8, AT24_FLAG_ADDR16);
167AT24_CHIP_DATA(at24_data_24c1024, 1048576 / 8, AT24_FLAG_ADDR16);
168AT24_CHIP_DATA(at24_data_24c2048, 2097152 / 8, AT24_FLAG_ADDR16);
169/* identical to 24c08 ? */
170AT24_CHIP_DATA(at24_data_INT3499, 8192 / 8, 0);
171
172static const struct i2c_device_id at24_ids[] = {
173 { "24c00", (kernel_ulong_t)&at24_data_24c00 },
174 { "24c01", (kernel_ulong_t)&at24_data_24c01 },
175 { "24cs01", (kernel_ulong_t)&at24_data_24cs01 },
176 { "24c02", (kernel_ulong_t)&at24_data_24c02 },
177 { "24cs02", (kernel_ulong_t)&at24_data_24cs02 },
178 { "24mac402", (kernel_ulong_t)&at24_data_24mac402 },
179 { "24mac602", (kernel_ulong_t)&at24_data_24mac602 },
180 { "spd", (kernel_ulong_t)&at24_data_spd },
181 { "24c04", (kernel_ulong_t)&at24_data_24c04 },
182 { "24cs04", (kernel_ulong_t)&at24_data_24cs04 },
183 { "24c08", (kernel_ulong_t)&at24_data_24c08 },
184 { "24cs08", (kernel_ulong_t)&at24_data_24cs08 },
185 { "24c16", (kernel_ulong_t)&at24_data_24c16 },
186 { "24cs16", (kernel_ulong_t)&at24_data_24cs16 },
187 { "24c32", (kernel_ulong_t)&at24_data_24c32 },
188 { "24cs32", (kernel_ulong_t)&at24_data_24cs32 },
189 { "24c64", (kernel_ulong_t)&at24_data_24c64 },
190 { "24cs64", (kernel_ulong_t)&at24_data_24cs64 },
191 { "24c128", (kernel_ulong_t)&at24_data_24c128 },
192 { "24c256", (kernel_ulong_t)&at24_data_24c256 },
193 { "24c512", (kernel_ulong_t)&at24_data_24c512 },
194 { "24c1024", (kernel_ulong_t)&at24_data_24c1024 },
195 { "24c2048", (kernel_ulong_t)&at24_data_24c2048 },
196 { "at24", 0 },
197 { /* END OF LIST */ }
198};
199MODULE_DEVICE_TABLE(i2c, at24_ids);
200
201static const struct of_device_id at24_of_match[] = {
202 { .compatible = "atmel,24c00", .data = &at24_data_24c00 },
203 { .compatible = "atmel,24c01", .data = &at24_data_24c01 },
204 { .compatible = "atmel,24cs01", .data = &at24_data_24cs01 },
205 { .compatible = "atmel,24c02", .data = &at24_data_24c02 },
206 { .compatible = "atmel,24cs02", .data = &at24_data_24cs02 },
207 { .compatible = "atmel,24mac402", .data = &at24_data_24mac402 },
208 { .compatible = "atmel,24mac602", .data = &at24_data_24mac602 },
209 { .compatible = "atmel,spd", .data = &at24_data_spd },
210 { .compatible = "atmel,24c04", .data = &at24_data_24c04 },
211 { .compatible = "atmel,24cs04", .data = &at24_data_24cs04 },
212 { .compatible = "atmel,24c08", .data = &at24_data_24c08 },
213 { .compatible = "atmel,24cs08", .data = &at24_data_24cs08 },
214 { .compatible = "atmel,24c16", .data = &at24_data_24c16 },
215 { .compatible = "atmel,24cs16", .data = &at24_data_24cs16 },
216 { .compatible = "atmel,24c32", .data = &at24_data_24c32 },
217 { .compatible = "atmel,24cs32", .data = &at24_data_24cs32 },
218 { .compatible = "atmel,24c64", .data = &at24_data_24c64 },
219 { .compatible = "atmel,24cs64", .data = &at24_data_24cs64 },
220 { .compatible = "atmel,24c128", .data = &at24_data_24c128 },
221 { .compatible = "atmel,24c256", .data = &at24_data_24c256 },
222 { .compatible = "atmel,24c512", .data = &at24_data_24c512 },
223 { .compatible = "atmel,24c1024", .data = &at24_data_24c1024 },
224 { .compatible = "atmel,24c2048", .data = &at24_data_24c2048 },
225 { /* END OF LIST */ },
226};
227MODULE_DEVICE_TABLE(of, at24_of_match);
228
229static const struct acpi_device_id at24_acpi_ids[] = {
230 { "INT3499", (kernel_ulong_t)&at24_data_INT3499 },
231 { /* END OF LIST */ }
232};
233MODULE_DEVICE_TABLE(acpi, at24_acpi_ids);
234
235/*
236 * This routine supports chips which consume multiple I2C addresses. It
237 * computes the addressing information to be used for a given r/w request.
238 * Assumes that sanity checks for offset happened at sysfs-layer.
239 *
240 * Slave address and byte offset derive from the offset. Always
241 * set the byte address; on a multi-master board, another master
242 * may have changed the chip's "current" address pointer.
243 */
244static struct at24_client *at24_translate_offset(struct at24_data *at24,
245 unsigned int *offset)
246{
247 unsigned int i;
248
249 if (at24->flags & AT24_FLAG_ADDR16) {
250 i = *offset >> 16;
251 *offset &= 0xffff;
252 } else {
253 i = *offset >> 8;
254 *offset &= 0xff;
255 }
256
257 return &at24->client[i];
258}
259
260static struct device *at24_base_client_dev(struct at24_data *at24)
261{
262 return &at24->client[0].client->dev;
263}
264
265static size_t at24_adjust_read_count(struct at24_data *at24,
266 unsigned int offset, size_t count)
267{
268 unsigned int bits;
269 size_t remainder;
270
271 /*
272 * In case of multi-address chips that don't rollover reads to
273 * the next slave address: truncate the count to the slave boundary,
274 * so that the read never straddles slaves.
275 */
276 if (at24->flags & AT24_FLAG_NO_RDROL) {
277 bits = (at24->flags & AT24_FLAG_ADDR16) ? 16 : 8;
278 remainder = BIT(bits) - offset;
279 if (count > remainder)
280 count = remainder;
281 }
282
283 if (count > at24_io_limit)
284 count = at24_io_limit;
285
286 return count;
287}
288
289static ssize_t at24_regmap_read(struct at24_data *at24, char *buf,
290 unsigned int offset, size_t count)
291{
292 unsigned long timeout, read_time;
293 struct at24_client *at24_client;
294 struct i2c_client *client;
295 struct regmap *regmap;
296 int ret;
297
298 at24_client = at24_translate_offset(at24, &offset);
299 regmap = at24_client->regmap;
300 client = at24_client->client;
301 count = at24_adjust_read_count(at24, offset, count);
302
303 /* adjust offset for mac and serial read ops */
304 offset += at24->offset_adj;
305
306 timeout = jiffies + msecs_to_jiffies(at24_write_timeout);
307 do {
308 /*
309 * The timestamp shall be taken before the actual operation
310 * to avoid a premature timeout in case of high CPU load.
311 */
312 read_time = jiffies;
313
314 ret = regmap_bulk_read(regmap, offset, buf, count);
315 dev_dbg(&client->dev, "read %zu@%d --> %d (%ld)\n",
316 count, offset, ret, jiffies);
317 if (!ret)
318 return count;
319
320 usleep_range(1000, 1500);
321 } while (time_before(read_time, timeout));
322
323 return -ETIMEDOUT;
324}
325
326/*
327 * Note that if the hardware write-protect pin is pulled high, the whole
328 * chip is normally write protected. But there are plenty of product
329 * variants here, including OTP fuses and partial chip protect.
330 *
331 * We only use page mode writes; the alternative is sloooow. These routines
332 * write at most one page.
333 */
334
335static size_t at24_adjust_write_count(struct at24_data *at24,
336 unsigned int offset, size_t count)
337{
338 unsigned int next_page;
339
340 /* write_max is at most a page */
341 if (count > at24->write_max)
342 count = at24->write_max;
343
344 /* Never roll over backwards, to the start of this page */
345 next_page = roundup(offset + 1, at24->page_size);
346 if (offset + count > next_page)
347 count = next_page - offset;
348
349 return count;
350}
351
352static ssize_t at24_regmap_write(struct at24_data *at24, const char *buf,
353 unsigned int offset, size_t count)
354{
355 unsigned long timeout, write_time;
356 struct at24_client *at24_client;
357 struct i2c_client *client;
358 struct regmap *regmap;
359 int ret;
360
361 at24_client = at24_translate_offset(at24, &offset);
362 regmap = at24_client->regmap;
363 client = at24_client->client;
364 count = at24_adjust_write_count(at24, offset, count);
365 timeout = jiffies + msecs_to_jiffies(at24_write_timeout);
366
367 do {
368 /*
369 * The timestamp shall be taken before the actual operation
370 * to avoid a premature timeout in case of high CPU load.
371 */
372 write_time = jiffies;
373
374 ret = regmap_bulk_write(regmap, offset, buf, count);
375 dev_dbg(&client->dev, "write %zu@%d --> %d (%ld)\n",
376 count, offset, ret, jiffies);
377 if (!ret)
378 return count;
379
380 usleep_range(1000, 1500);
381 } while (time_before(write_time, timeout));
382
383 return -ETIMEDOUT;
384}
385
386static int at24_read(void *priv, unsigned int off, void *val, size_t count)
387{
388 struct at24_data *at24;
389 struct device *dev;
390 char *buf = val;
391 int ret;
392
393 at24 = priv;
394 dev = at24_base_client_dev(at24);
395
396 if (unlikely(!count))
397 return count;
398
399 if (off + count > at24->byte_len)
400 return -EINVAL;
401
402 ret = pm_runtime_get_sync(dev);
403 if (ret < 0) {
404 pm_runtime_put_noidle(dev);
405 return ret;
406 }
407
408 /*
409 * Read data from chip, protecting against concurrent updates
410 * from this host, but not from other I2C masters.
411 */
412 mutex_lock(&at24->lock);
413
414 while (count) {
415 ret = at24_regmap_read(at24, buf, off, count);
416 if (ret < 0) {
417 mutex_unlock(&at24->lock);
418 pm_runtime_put(dev);
419 return ret;
420 }
421 buf += ret;
422 off += ret;
423 count -= ret;
424 }
425
426 mutex_unlock(&at24->lock);
427
428 pm_runtime_put(dev);
429
430 return 0;
431}
432
433static int at24_write(void *priv, unsigned int off, void *val, size_t count)
434{
435 struct at24_data *at24;
436 struct device *dev;
437 char *buf = val;
438 int ret;
439
440 at24 = priv;
441 dev = at24_base_client_dev(at24);
442
443 if (unlikely(!count))
444 return -EINVAL;
445
446 if (off + count > at24->byte_len)
447 return -EINVAL;
448
449 ret = pm_runtime_get_sync(dev);
450 if (ret < 0) {
451 pm_runtime_put_noidle(dev);
452 return ret;
453 }
454
455 /*
456 * Write data to chip, protecting against concurrent updates
457 * from this host, but not from other I2C masters.
458 */
459 mutex_lock(&at24->lock);
460 gpiod_set_value_cansleep(at24->wp_gpio, 0);
461
462 while (count) {
463 ret = at24_regmap_write(at24, buf, off, count);
464 if (ret < 0) {
465 gpiod_set_value_cansleep(at24->wp_gpio, 1);
466 mutex_unlock(&at24->lock);
467 pm_runtime_put(dev);
468 return ret;
469 }
470 buf += ret;
471 off += ret;
472 count -= ret;
473 }
474
475 gpiod_set_value_cansleep(at24->wp_gpio, 1);
476 mutex_unlock(&at24->lock);
477
478 pm_runtime_put(dev);
479
480 return 0;
481}
482
483static const struct at24_chip_data *at24_get_chip_data(struct device *dev)
484{
485 struct device_node *of_node = dev->of_node;
486 const struct at24_chip_data *cdata;
487 const struct i2c_device_id *id;
488
489 id = i2c_match_id(at24_ids, to_i2c_client(dev));
490
491 /*
492 * The I2C core allows OF nodes compatibles to match against the
493 * I2C device ID table as a fallback, so check not only if an OF
494 * node is present but also if it matches an OF device ID entry.
495 */
496 if (of_node && of_match_device(at24_of_match, dev))
497 cdata = of_device_get_match_data(dev);
498 else if (id)
499 cdata = (void *)id->driver_data;
500 else
501 cdata = acpi_device_get_match_data(dev);
502
503 if (!cdata)
504 return ERR_PTR(-ENODEV);
505
506 return cdata;
507}
508
509static int at24_make_dummy_client(struct at24_data *at24, unsigned int index,
510 struct regmap_config *regmap_config)
511{
512 struct i2c_client *base_client, *dummy_client;
513 struct regmap *regmap;
514 struct device *dev;
515
516 base_client = at24->client[0].client;
517 dev = &base_client->dev;
518
519 dummy_client = devm_i2c_new_dummy_device(dev, base_client->adapter,
520 base_client->addr + index);
521 if (IS_ERR(dummy_client))
522 return PTR_ERR(dummy_client);
523
524 regmap = devm_regmap_init_i2c(dummy_client, regmap_config);
525 if (IS_ERR(regmap))
526 return PTR_ERR(regmap);
527
528 at24->client[index].client = dummy_client;
529 at24->client[index].regmap = regmap;
530
531 return 0;
532}
533
534static unsigned int at24_get_offset_adj(u8 flags, unsigned int byte_len)
535{
536 if (flags & AT24_FLAG_MAC) {
537 /* EUI-48 starts from 0x9a, EUI-64 from 0x98 */
538 return 0xa0 - byte_len;
539 } else if (flags & AT24_FLAG_SERIAL && flags & AT24_FLAG_ADDR16) {
540 /*
541 * For 16 bit address pointers, the word address must contain
542 * a '10' sequence in bits 11 and 10 regardless of the
543 * intended position of the address pointer.
544 */
545 return 0x0800;
546 } else if (flags & AT24_FLAG_SERIAL) {
547 /*
548 * Otherwise the word address must begin with a '10' sequence,
549 * regardless of the intended address.
550 */
551 return 0x0080;
552 } else {
553 return 0;
554 }
555}
556
557static int at24_probe(struct i2c_client *client)
558{
559 struct regmap_config regmap_config = { };
560 struct nvmem_config nvmem_config = { };
561 u32 byte_len, page_size, flags, addrw;
562 const struct at24_chip_data *cdata;
563 struct device *dev = &client->dev;
564 bool i2c_fn_i2c, i2c_fn_block;
565 unsigned int i, num_addresses;
566 struct at24_data *at24;
567 struct regmap *regmap;
568 bool writable;
569 u8 test_byte;
570 int err;
571
572 i2c_fn_i2c = i2c_check_functionality(client->adapter, I2C_FUNC_I2C);
573 i2c_fn_block = i2c_check_functionality(client->adapter,
574 I2C_FUNC_SMBUS_WRITE_I2C_BLOCK);
575
576 cdata = at24_get_chip_data(dev);
577 if (IS_ERR(cdata))
578 return PTR_ERR(cdata);
579
580 err = device_property_read_u32(dev, "pagesize", &page_size);
581 if (err)
582 /*
583 * This is slow, but we can't know all eeproms, so we better
584 * play safe. Specifying custom eeprom-types via device tree
585 * or properties is recommended anyhow.
586 */
587 page_size = 1;
588
589 flags = cdata->flags;
590 if (device_property_present(dev, "read-only"))
591 flags |= AT24_FLAG_READONLY;
592 if (device_property_present(dev, "no-read-rollover"))
593 flags |= AT24_FLAG_NO_RDROL;
594
595 err = device_property_read_u32(dev, "address-width", &addrw);
596 if (!err) {
597 switch (addrw) {
598 case 8:
599 if (flags & AT24_FLAG_ADDR16)
600 dev_warn(dev,
601 "Override address width to be 8, while default is 16\n");
602 flags &= ~AT24_FLAG_ADDR16;
603 break;
604 case 16:
605 flags |= AT24_FLAG_ADDR16;
606 break;
607 default:
608 dev_warn(dev, "Bad \"address-width\" property: %u\n",
609 addrw);
610 }
611 }
612
613 err = device_property_read_u32(dev, "size", &byte_len);
614 if (err)
615 byte_len = cdata->byte_len;
616
617 if (!i2c_fn_i2c && !i2c_fn_block)
618 page_size = 1;
619
620 if (!page_size) {
621 dev_err(dev, "page_size must not be 0!\n");
622 return -EINVAL;
623 }
624
625 if (!is_power_of_2(page_size))
626 dev_warn(dev, "page_size looks suspicious (no power of 2)!\n");
627
628 err = device_property_read_u32(dev, "num-addresses", &num_addresses);
629 if (err) {
630 if (flags & AT24_FLAG_TAKE8ADDR)
631 num_addresses = 8;
632 else
633 num_addresses = DIV_ROUND_UP(byte_len,
634 (flags & AT24_FLAG_ADDR16) ? 65536 : 256);
635 }
636
637 if ((flags & AT24_FLAG_SERIAL) && (flags & AT24_FLAG_MAC)) {
638 dev_err(dev,
639 "invalid device data - cannot have both AT24_FLAG_SERIAL & AT24_FLAG_MAC.");
640 return -EINVAL;
641 }
642
643 regmap_config.val_bits = 8;
644 regmap_config.reg_bits = (flags & AT24_FLAG_ADDR16) ? 16 : 8;
645 regmap_config.disable_locking = true;
646
647 regmap = devm_regmap_init_i2c(client, ®map_config);
648 if (IS_ERR(regmap))
649 return PTR_ERR(regmap);
650
651 at24 = devm_kzalloc(dev, struct_size(at24, client, num_addresses),
652 GFP_KERNEL);
653 if (!at24)
654 return -ENOMEM;
655
656 mutex_init(&at24->lock);
657 at24->byte_len = byte_len;
658 at24->page_size = page_size;
659 at24->flags = flags;
660 at24->num_addresses = num_addresses;
661 at24->offset_adj = at24_get_offset_adj(flags, byte_len);
662 at24->client[0].client = client;
663 at24->client[0].regmap = regmap;
664
665 at24->wp_gpio = devm_gpiod_get_optional(dev, "wp", GPIOD_OUT_HIGH);
666 if (IS_ERR(at24->wp_gpio))
667 return PTR_ERR(at24->wp_gpio);
668
669 writable = !(flags & AT24_FLAG_READONLY);
670 if (writable) {
671 at24->write_max = min_t(unsigned int,
672 page_size, at24_io_limit);
673 if (!i2c_fn_i2c && at24->write_max > I2C_SMBUS_BLOCK_MAX)
674 at24->write_max = I2C_SMBUS_BLOCK_MAX;
675 }
676
677 /* use dummy devices for multiple-address chips */
678 for (i = 1; i < num_addresses; i++) {
679 err = at24_make_dummy_client(at24, i, ®map_config);
680 if (err)
681 return err;
682 }
683
684 nvmem_config.name = dev_name(dev);
685 nvmem_config.dev = dev;
686 nvmem_config.read_only = !writable;
687 nvmem_config.root_only = !(flags & AT24_FLAG_IRUGO);
688 nvmem_config.owner = THIS_MODULE;
689 nvmem_config.compat = true;
690 nvmem_config.base_dev = dev;
691 nvmem_config.reg_read = at24_read;
692 nvmem_config.reg_write = at24_write;
693 nvmem_config.priv = at24;
694 nvmem_config.stride = 1;
695 nvmem_config.word_size = 1;
696 nvmem_config.size = byte_len;
697
698 at24->nvmem = devm_nvmem_register(dev, &nvmem_config);
699 if (IS_ERR(at24->nvmem))
700 return PTR_ERR(at24->nvmem);
701
702 i2c_set_clientdata(client, at24);
703
704 /* enable runtime pm */
705 pm_runtime_set_active(dev);
706 pm_runtime_enable(dev);
707
708 /*
709 * Perform a one-byte test read to verify that the
710 * chip is functional.
711 */
712 err = at24_read(at24, 0, &test_byte, 1);
713 pm_runtime_idle(dev);
714 if (err) {
715 pm_runtime_disable(dev);
716 return -ENODEV;
717 }
718
719 dev_info(dev, "%u byte %s EEPROM, %s, %u bytes/write\n",
720 byte_len, client->name,
721 writable ? "writable" : "read-only", at24->write_max);
722
723 return 0;
724}
725
726static int at24_remove(struct i2c_client *client)
727{
728 pm_runtime_disable(&client->dev);
729 pm_runtime_set_suspended(&client->dev);
730
731 return 0;
732}
733
734static struct i2c_driver at24_driver = {
735 .driver = {
736 .name = "at24",
737 .of_match_table = at24_of_match,
738 .acpi_match_table = ACPI_PTR(at24_acpi_ids),
739 },
740 .probe_new = at24_probe,
741 .remove = at24_remove,
742 .id_table = at24_ids,
743};
744
745static int __init at24_init(void)
746{
747 if (!at24_io_limit) {
748 pr_err("at24: at24_io_limit must not be 0!\n");
749 return -EINVAL;
750 }
751
752 at24_io_limit = rounddown_pow_of_two(at24_io_limit);
753 return i2c_add_driver(&at24_driver);
754}
755module_init(at24_init);
756
757static void __exit at24_exit(void)
758{
759 i2c_del_driver(&at24_driver);
760}
761module_exit(at24_exit);
762
763MODULE_DESCRIPTION("Driver for most I2C EEPROMs");
764MODULE_AUTHOR("David Brownell and Wolfram Sang");
765MODULE_LICENSE("GPL");