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1/* SPDX-License-Identifier: GPL-2.0-only */
2/*
3 * Copyright © 2014-2015 Broadcom
4 */
5
6#ifndef VC4_REGS_H
7#define VC4_REGS_H
8
9#include <linux/bitops.h>
10
11#define VC4_MASK(high, low) ((u32)GENMASK(high, low))
12/* Using the GNU statement expression extension */
13#define VC4_SET_FIELD(value, field) \
14 ({ \
15 uint32_t fieldval = (value) << field##_SHIFT; \
16 WARN_ON((fieldval & ~field##_MASK) != 0); \
17 fieldval & field##_MASK; \
18 })
19
20#define VC4_GET_FIELD(word, field) (((word) & field##_MASK) >> \
21 field##_SHIFT)
22
23#define V3D_IDENT0 0x00000
24# define V3D_EXPECTED_IDENT0 \
25 ((2 << 24) | \
26 ('V' << 0) | \
27 ('3' << 8) | \
28 ('D' << 16))
29
30#define V3D_IDENT1 0x00004
31/* Multiples of 1kb */
32# define V3D_IDENT1_VPM_SIZE_MASK VC4_MASK(31, 28)
33# define V3D_IDENT1_VPM_SIZE_SHIFT 28
34# define V3D_IDENT1_NSEM_MASK VC4_MASK(23, 16)
35# define V3D_IDENT1_NSEM_SHIFT 16
36# define V3D_IDENT1_TUPS_MASK VC4_MASK(15, 12)
37# define V3D_IDENT1_TUPS_SHIFT 12
38# define V3D_IDENT1_QUPS_MASK VC4_MASK(11, 8)
39# define V3D_IDENT1_QUPS_SHIFT 8
40# define V3D_IDENT1_NSLC_MASK VC4_MASK(7, 4)
41# define V3D_IDENT1_NSLC_SHIFT 4
42# define V3D_IDENT1_REV_MASK VC4_MASK(3, 0)
43# define V3D_IDENT1_REV_SHIFT 0
44
45#define V3D_IDENT2 0x00008
46#define V3D_SCRATCH 0x00010
47#define V3D_L2CACTL 0x00020
48# define V3D_L2CACTL_L2CCLR BIT(2)
49# define V3D_L2CACTL_L2CDIS BIT(1)
50# define V3D_L2CACTL_L2CENA BIT(0)
51
52#define V3D_SLCACTL 0x00024
53# define V3D_SLCACTL_T1CC_MASK VC4_MASK(27, 24)
54# define V3D_SLCACTL_T1CC_SHIFT 24
55# define V3D_SLCACTL_T0CC_MASK VC4_MASK(19, 16)
56# define V3D_SLCACTL_T0CC_SHIFT 16
57# define V3D_SLCACTL_UCC_MASK VC4_MASK(11, 8)
58# define V3D_SLCACTL_UCC_SHIFT 8
59# define V3D_SLCACTL_ICC_MASK VC4_MASK(3, 0)
60# define V3D_SLCACTL_ICC_SHIFT 0
61
62#define V3D_INTCTL 0x00030
63#define V3D_INTENA 0x00034
64#define V3D_INTDIS 0x00038
65# define V3D_INT_SPILLUSE BIT(3)
66# define V3D_INT_OUTOMEM BIT(2)
67# define V3D_INT_FLDONE BIT(1)
68# define V3D_INT_FRDONE BIT(0)
69
70#define V3D_CT0CS 0x00100
71#define V3D_CT1CS 0x00104
72#define V3D_CTNCS(n) (V3D_CT0CS + 4 * n)
73# define V3D_CTRSTA BIT(15)
74# define V3D_CTSEMA BIT(12)
75# define V3D_CTRTSD BIT(8)
76# define V3D_CTRUN BIT(5)
77# define V3D_CTSUBS BIT(4)
78# define V3D_CTERR BIT(3)
79# define V3D_CTMODE BIT(0)
80
81#define V3D_CT0EA 0x00108
82#define V3D_CT1EA 0x0010c
83#define V3D_CTNEA(n) (V3D_CT0EA + 4 * (n))
84#define V3D_CT0CA 0x00110
85#define V3D_CT1CA 0x00114
86#define V3D_CTNCA(n) (V3D_CT0CA + 4 * (n))
87#define V3D_CT00RA0 0x00118
88#define V3D_CT01RA0 0x0011c
89#define V3D_CTNRA0(n) (V3D_CT00RA0 + 4 * (n))
90#define V3D_CT0LC 0x00120
91#define V3D_CT1LC 0x00124
92#define V3D_CTNLC(n) (V3D_CT0LC + 4 * (n))
93#define V3D_CT0PC 0x00128
94#define V3D_CT1PC 0x0012c
95#define V3D_CTNPC(n) (V3D_CT0PC + 4 * (n))
96
97#define V3D_PCS 0x00130
98# define V3D_BMOOM BIT(8)
99# define V3D_RMBUSY BIT(3)
100# define V3D_RMACTIVE BIT(2)
101# define V3D_BMBUSY BIT(1)
102# define V3D_BMACTIVE BIT(0)
103
104#define V3D_BFC 0x00134
105#define V3D_RFC 0x00138
106#define V3D_BPCA 0x00300
107#define V3D_BPCS 0x00304
108#define V3D_BPOA 0x00308
109#define V3D_BPOS 0x0030c
110#define V3D_BXCF 0x00310
111#define V3D_SQRSV0 0x00410
112#define V3D_SQRSV1 0x00414
113#define V3D_SQCNTL 0x00418
114#define V3D_SRQPC 0x00430
115#define V3D_SRQUA 0x00434
116#define V3D_SRQUL 0x00438
117#define V3D_SRQCS 0x0043c
118#define V3D_VPACNTL 0x00500
119#define V3D_VPMBASE 0x00504
120#define V3D_PCTRC 0x00670
121#define V3D_PCTRE 0x00674
122# define V3D_PCTRE_EN BIT(31)
123#define V3D_PCTR(x) (0x00680 + ((x) * 8))
124#define V3D_PCTRS(x) (0x00684 + ((x) * 8))
125#define V3D_DBGE 0x00f00
126#define V3D_FDBGO 0x00f04
127#define V3D_FDBGB 0x00f08
128#define V3D_FDBGR 0x00f0c
129#define V3D_FDBGS 0x00f10
130#define V3D_ERRSTAT 0x00f20
131
132#define PV_CONTROL 0x00
133# define PV_CONTROL_FORMAT_MASK VC4_MASK(23, 21)
134# define PV_CONTROL_FORMAT_SHIFT 21
135# define PV_CONTROL_FORMAT_24 0
136# define PV_CONTROL_FORMAT_DSIV_16 1
137# define PV_CONTROL_FORMAT_DSIC_16 2
138# define PV_CONTROL_FORMAT_DSIV_18 3
139# define PV_CONTROL_FORMAT_DSIV_24 4
140
141# define PV_CONTROL_FIFO_LEVEL_MASK VC4_MASK(20, 15)
142# define PV_CONTROL_FIFO_LEVEL_SHIFT 15
143# define PV_CONTROL_CLR_AT_START BIT(14)
144# define PV_CONTROL_TRIGGER_UNDERFLOW BIT(13)
145# define PV_CONTROL_WAIT_HSTART BIT(12)
146# define PV_CONTROL_PIXEL_REP_MASK VC4_MASK(5, 4)
147# define PV_CONTROL_PIXEL_REP_SHIFT 4
148# define PV_CONTROL_CLK_SELECT_DSI 0
149# define PV_CONTROL_CLK_SELECT_DPI_SMI_HDMI 1
150# define PV_CONTROL_CLK_SELECT_VEC 2
151# define PV_CONTROL_CLK_SELECT_MASK VC4_MASK(3, 2)
152# define PV_CONTROL_CLK_SELECT_SHIFT 2
153# define PV_CONTROL_FIFO_CLR BIT(1)
154# define PV_CONTROL_EN BIT(0)
155
156#define PV_V_CONTROL 0x04
157# define PV_VCONTROL_ODD_DELAY_MASK VC4_MASK(22, 6)
158# define PV_VCONTROL_ODD_DELAY_SHIFT 6
159# define PV_VCONTROL_ODD_FIRST BIT(5)
160# define PV_VCONTROL_INTERLACE BIT(4)
161# define PV_VCONTROL_DSI BIT(3)
162# define PV_VCONTROL_COMMAND BIT(2)
163# define PV_VCONTROL_CONTINUOUS BIT(1)
164# define PV_VCONTROL_VIDEN BIT(0)
165
166#define PV_VSYNCD_EVEN 0x08
167
168#define PV_HORZA 0x0c
169# define PV_HORZA_HBP_MASK VC4_MASK(31, 16)
170# define PV_HORZA_HBP_SHIFT 16
171# define PV_HORZA_HSYNC_MASK VC4_MASK(15, 0)
172# define PV_HORZA_HSYNC_SHIFT 0
173
174#define PV_HORZB 0x10
175# define PV_HORZB_HFP_MASK VC4_MASK(31, 16)
176# define PV_HORZB_HFP_SHIFT 16
177# define PV_HORZB_HACTIVE_MASK VC4_MASK(15, 0)
178# define PV_HORZB_HACTIVE_SHIFT 0
179
180#define PV_VERTA 0x14
181# define PV_VERTA_VBP_MASK VC4_MASK(31, 16)
182# define PV_VERTA_VBP_SHIFT 16
183# define PV_VERTA_VSYNC_MASK VC4_MASK(15, 0)
184# define PV_VERTA_VSYNC_SHIFT 0
185
186#define PV_VERTB 0x18
187# define PV_VERTB_VFP_MASK VC4_MASK(31, 16)
188# define PV_VERTB_VFP_SHIFT 16
189# define PV_VERTB_VACTIVE_MASK VC4_MASK(15, 0)
190# define PV_VERTB_VACTIVE_SHIFT 0
191
192#define PV_VERTA_EVEN 0x1c
193#define PV_VERTB_EVEN 0x20
194
195#define PV_INTEN 0x24
196#define PV_INTSTAT 0x28
197# define PV_INT_VID_IDLE BIT(9)
198# define PV_INT_VFP_END BIT(8)
199# define PV_INT_VFP_START BIT(7)
200# define PV_INT_VACT_START BIT(6)
201# define PV_INT_VBP_START BIT(5)
202# define PV_INT_VSYNC_START BIT(4)
203# define PV_INT_HFP_START BIT(3)
204# define PV_INT_HACT_START BIT(2)
205# define PV_INT_HBP_START BIT(1)
206# define PV_INT_HSYNC_START BIT(0)
207
208#define PV_STAT 0x2c
209
210#define PV_HACT_ACT 0x30
211
212#define SCALER_CHANNELS_COUNT 3
213
214#define SCALER_DISPCTRL 0x00000000
215/* Global register for clock gating the HVS */
216# define SCALER_DISPCTRL_ENABLE BIT(31)
217# define SCALER_DISPCTRL_DSP3_MUX_MASK VC4_MASK(19, 18)
218# define SCALER_DISPCTRL_DSP3_MUX_SHIFT 18
219
220/* Enables Display 0 short line and underrun contribution to
221 * SCALER_DISPSTAT_IRQDISP0. Note that short frame contributions are
222 * always enabled.
223 */
224# define SCALER_DISPCTRL_DSPEISLUR(x) BIT(13 + (x))
225/* Enables Display 0 end-of-line-N contribution to
226 * SCALER_DISPSTAT_IRQDISP0
227 */
228# define SCALER_DISPCTRL_DSPEIEOLN(x) BIT(8 + ((x) * 2))
229/* Enables Display 0 EOF contribution to SCALER_DISPSTAT_IRQDISP0 */
230# define SCALER_DISPCTRL_DSPEIEOF(x) BIT(7 + ((x) * 2))
231
232# define SCALER_DISPCTRL_SLVRDEIRQ BIT(6)
233# define SCALER_DISPCTRL_SLVWREIRQ BIT(5)
234# define SCALER_DISPCTRL_DMAEIRQ BIT(4)
235/* Enables interrupt generation on the enabled EOF/EOLN/EISLUR
236 * bits and short frames..
237 */
238# define SCALER_DISPCTRL_DISPEIRQ(x) BIT(1 + (x))
239/* Enables interrupt generation on scaler profiler interrupt. */
240# define SCALER_DISPCTRL_SCLEIRQ BIT(0)
241
242#define SCALER_DISPSTAT 0x00000004
243# define SCALER_DISPSTAT_RESP_MASK VC4_MASK(15, 14)
244# define SCALER_DISPSTAT_RESP_SHIFT 14
245# define SCALER_DISPSTAT_RESP_OKAY 0
246# define SCALER_DISPSTAT_RESP_EXOKAY 1
247# define SCALER_DISPSTAT_RESP_SLVERR 2
248# define SCALER_DISPSTAT_RESP_DECERR 3
249
250# define SCALER_DISPSTAT_COBLOW(x) BIT(13 + ((x) * 8))
251/* Set when the DISPEOLN line is done compositing. */
252# define SCALER_DISPSTAT_EOLN(x) BIT(12 + ((x) * 8))
253/* Set when VSTART is seen but there are still pixels in the current
254 * output line.
255 */
256# define SCALER_DISPSTAT_ESFRAME(x) BIT(11 + ((x) * 8))
257/* Set when HSTART is seen but there are still pixels in the current
258 * output line.
259 */
260# define SCALER_DISPSTAT_ESLINE(x) BIT(10 + ((x) * 8))
261/* Set when the the downstream tries to read from the display FIFO
262 * while it's empty.
263 */
264# define SCALER_DISPSTAT_EUFLOW(x) BIT(9 + ((x) * 8))
265/* Set when the display mode changes from RUN to EOF */
266# define SCALER_DISPSTAT_EOF(x) BIT(8 + ((x) * 8))
267
268# define SCALER_DISPSTAT_IRQMASK(x) VC4_MASK(13 + ((x) * 8), \
269 8 + ((x) * 8))
270
271/* Set on AXI invalid DMA ID error. */
272# define SCALER_DISPSTAT_DMA_ERROR BIT(7)
273/* Set on AXI slave read decode error */
274# define SCALER_DISPSTAT_IRQSLVRD BIT(6)
275/* Set on AXI slave write decode error */
276# define SCALER_DISPSTAT_IRQSLVWR BIT(5)
277/* Set when SCALER_DISPSTAT_DMA_ERROR is set, or
278 * SCALER_DISPSTAT_RESP_ERROR is not SCALER_DISPSTAT_RESP_OKAY.
279 */
280# define SCALER_DISPSTAT_IRQDMA BIT(4)
281/* Set when any of the EOF/EOLN/ESFRAME/ESLINE bits are set and their
282 * corresponding interrupt bit is enabled in DISPCTRL.
283 */
284# define SCALER_DISPSTAT_IRQDISP(x) BIT(1 + (x))
285/* On read, the profiler interrupt. On write, clear *all* interrupt bits. */
286# define SCALER_DISPSTAT_IRQSCL BIT(0)
287
288#define SCALER_DISPID 0x00000008
289#define SCALER_DISPECTRL 0x0000000c
290#define SCALER_DISPPROF 0x00000010
291#define SCALER_DISPDITHER 0x00000014
292#define SCALER_DISPEOLN 0x00000018
293#define SCALER_DISPLIST0 0x00000020
294#define SCALER_DISPLIST1 0x00000024
295#define SCALER_DISPLIST2 0x00000028
296#define SCALER_DISPLSTAT 0x0000002c
297#define SCALER_DISPLISTX(x) (SCALER_DISPLIST0 + \
298 (x) * (SCALER_DISPLIST1 - \
299 SCALER_DISPLIST0))
300
301#define SCALER_DISPLACT0 0x00000030
302#define SCALER_DISPLACT1 0x00000034
303#define SCALER_DISPLACT2 0x00000038
304#define SCALER_DISPLACTX(x) (SCALER_DISPLACT0 + \
305 (x) * (SCALER_DISPLACT1 - \
306 SCALER_DISPLACT0))
307
308#define SCALER_DISPCTRL0 0x00000040
309# define SCALER_DISPCTRLX_ENABLE BIT(31)
310# define SCALER_DISPCTRLX_RESET BIT(30)
311/* Generates a single frame when VSTART is seen and stops at the last
312 * pixel read from the FIFO.
313 */
314# define SCALER_DISPCTRLX_ONESHOT BIT(29)
315/* Processes a single context in the dlist and then task switch,
316 * instead of an entire line.
317 */
318# define SCALER_DISPCTRLX_ONECTX BIT(28)
319/* Set to have DISPSLAVE return 2 16bpp pixels and no status data. */
320# define SCALER_DISPCTRLX_FIFO32 BIT(27)
321/* Turns on output to the DISPSLAVE register instead of the normal
322 * FIFO.
323 */
324# define SCALER_DISPCTRLX_FIFOREG BIT(26)
325
326# define SCALER_DISPCTRLX_WIDTH_MASK VC4_MASK(23, 12)
327# define SCALER_DISPCTRLX_WIDTH_SHIFT 12
328# define SCALER_DISPCTRLX_HEIGHT_MASK VC4_MASK(11, 0)
329# define SCALER_DISPCTRLX_HEIGHT_SHIFT 0
330
331#define SCALER_DISPBKGND0 0x00000044
332# define SCALER_DISPBKGND_AUTOHS BIT(31)
333# define SCALER_DISPBKGND_INTERLACE BIT(30)
334# define SCALER_DISPBKGND_GAMMA BIT(29)
335# define SCALER_DISPBKGND_TESTMODE_MASK VC4_MASK(28, 25)
336# define SCALER_DISPBKGND_TESTMODE_SHIFT 25
337/* Enables filling the scaler line with the RGB value in the low 24
338 * bits before compositing. Costs cycles, so should be skipped if
339 * opaque display planes will cover everything.
340 */
341# define SCALER_DISPBKGND_FILL BIT(24)
342
343#define SCALER_DISPSTAT0 0x00000048
344# define SCALER_DISPSTATX_MODE_MASK VC4_MASK(31, 30)
345# define SCALER_DISPSTATX_MODE_SHIFT 30
346# define SCALER_DISPSTATX_MODE_DISABLED 0
347# define SCALER_DISPSTATX_MODE_INIT 1
348# define SCALER_DISPSTATX_MODE_RUN 2
349# define SCALER_DISPSTATX_MODE_EOF 3
350# define SCALER_DISPSTATX_FULL BIT(29)
351# define SCALER_DISPSTATX_EMPTY BIT(28)
352# define SCALER_DISPSTATX_FRAME_COUNT_MASK VC4_MASK(17, 12)
353# define SCALER_DISPSTATX_FRAME_COUNT_SHIFT 12
354# define SCALER_DISPSTATX_LINE_MASK VC4_MASK(11, 0)
355# define SCALER_DISPSTATX_LINE_SHIFT 0
356
357#define SCALER_DISPBASE0 0x0000004c
358/* Last pixel in the COB (display FIFO memory) allocated to this HVS
359 * channel. Must be 4-pixel aligned (and thus 4 pixels less than the
360 * next COB base).
361 */
362# define SCALER_DISPBASEX_TOP_MASK VC4_MASK(31, 16)
363# define SCALER_DISPBASEX_TOP_SHIFT 16
364/* First pixel in the COB (display FIFO memory) allocated to this HVS
365 * channel. Must be 4-pixel aligned.
366 */
367# define SCALER_DISPBASEX_BASE_MASK VC4_MASK(15, 0)
368# define SCALER_DISPBASEX_BASE_SHIFT 0
369
370#define SCALER_DISPCTRL1 0x00000050
371#define SCALER_DISPBKGND1 0x00000054
372#define SCALER_DISPBKGNDX(x) (SCALER_DISPBKGND0 + \
373 (x) * (SCALER_DISPBKGND1 - \
374 SCALER_DISPBKGND0))
375#define SCALER_DISPSTAT1 0x00000058
376#define SCALER_DISPSTATX(x) (SCALER_DISPSTAT0 + \
377 (x) * (SCALER_DISPSTAT1 - \
378 SCALER_DISPSTAT0))
379#define SCALER_DISPBASE1 0x0000005c
380#define SCALER_DISPBASEX(x) (SCALER_DISPBASE0 + \
381 (x) * (SCALER_DISPBASE1 - \
382 SCALER_DISPBASE0))
383#define SCALER_DISPCTRL2 0x00000060
384#define SCALER_DISPCTRLX(x) (SCALER_DISPCTRL0 + \
385 (x) * (SCALER_DISPCTRL1 - \
386 SCALER_DISPCTRL0))
387#define SCALER_DISPBKGND2 0x00000064
388#define SCALER_DISPSTAT2 0x00000068
389#define SCALER_DISPBASE2 0x0000006c
390#define SCALER_DISPALPHA2 0x00000070
391#define SCALER_GAMADDR 0x00000078
392# define SCALER_GAMADDR_AUTOINC BIT(31)
393/* Enables all gamma ramp SRAMs, not just those of CRTCs with gamma
394 * enabled.
395 */
396# define SCALER_GAMADDR_SRAMENB BIT(30)
397
398#define SCALER_OLEDOFFS 0x00000080
399/* Clamps R to [16,235] and G/B to [16,240]. */
400# define SCALER_OLEDOFFS_YUVCLAMP BIT(31)
401
402/* Chooses which display FIFO the matrix applies to. */
403# define SCALER_OLEDOFFS_DISPFIFO_MASK VC4_MASK(25, 24)
404# define SCALER_OLEDOFFS_DISPFIFO_SHIFT 24
405# define SCALER_OLEDOFFS_DISPFIFO_DISABLED 0
406# define SCALER_OLEDOFFS_DISPFIFO_0 1
407# define SCALER_OLEDOFFS_DISPFIFO_1 2
408# define SCALER_OLEDOFFS_DISPFIFO_2 3
409
410/* Offsets are 8-bit 2s-complement. */
411# define SCALER_OLEDOFFS_RED_MASK VC4_MASK(23, 16)
412# define SCALER_OLEDOFFS_RED_SHIFT 16
413# define SCALER_OLEDOFFS_GREEN_MASK VC4_MASK(15, 8)
414# define SCALER_OLEDOFFS_GREEN_SHIFT 8
415# define SCALER_OLEDOFFS_BLUE_MASK VC4_MASK(7, 0)
416# define SCALER_OLEDOFFS_BLUE_SHIFT 0
417
418/* The coefficients are S0.9 fractions. */
419#define SCALER_OLEDCOEF0 0x00000084
420# define SCALER_OLEDCOEF0_B_TO_R_MASK VC4_MASK(29, 20)
421# define SCALER_OLEDCOEF0_B_TO_R_SHIFT 20
422# define SCALER_OLEDCOEF0_B_TO_G_MASK VC4_MASK(19, 10)
423# define SCALER_OLEDCOEF0_B_TO_G_SHIFT 10
424# define SCALER_OLEDCOEF0_B_TO_B_MASK VC4_MASK(9, 0)
425# define SCALER_OLEDCOEF0_B_TO_B_SHIFT 0
426
427#define SCALER_OLEDCOEF1 0x00000088
428# define SCALER_OLEDCOEF1_G_TO_R_MASK VC4_MASK(29, 20)
429# define SCALER_OLEDCOEF1_G_TO_R_SHIFT 20
430# define SCALER_OLEDCOEF1_G_TO_G_MASK VC4_MASK(19, 10)
431# define SCALER_OLEDCOEF1_G_TO_G_SHIFT 10
432# define SCALER_OLEDCOEF1_G_TO_B_MASK VC4_MASK(9, 0)
433# define SCALER_OLEDCOEF1_G_TO_B_SHIFT 0
434
435#define SCALER_OLEDCOEF2 0x0000008c
436# define SCALER_OLEDCOEF2_R_TO_R_MASK VC4_MASK(29, 20)
437# define SCALER_OLEDCOEF2_R_TO_R_SHIFT 20
438# define SCALER_OLEDCOEF2_R_TO_G_MASK VC4_MASK(19, 10)
439# define SCALER_OLEDCOEF2_R_TO_G_SHIFT 10
440# define SCALER_OLEDCOEF2_R_TO_B_MASK VC4_MASK(9, 0)
441# define SCALER_OLEDCOEF2_R_TO_B_SHIFT 0
442
443/* Slave addresses for DMAing from HVS composition output to other
444 * devices. The top bits are valid only in !FIFO32 mode.
445 */
446#define SCALER_DISPSLAVE0 0x000000c0
447#define SCALER_DISPSLAVE1 0x000000c9
448#define SCALER_DISPSLAVE2 0x000000d0
449# define SCALER_DISPSLAVE_ISSUE_VSTART BIT(31)
450# define SCALER_DISPSLAVE_ISSUE_HSTART BIT(30)
451/* Set when the current line has been read and an HSTART is required. */
452# define SCALER_DISPSLAVE_EOL BIT(26)
453/* Set when the display FIFO is empty. */
454# define SCALER_DISPSLAVE_EMPTY BIT(25)
455/* Set when there is RGB data ready to read. */
456# define SCALER_DISPSLAVE_VALID BIT(24)
457# define SCALER_DISPSLAVE_RGB_MASK VC4_MASK(23, 0)
458# define SCALER_DISPSLAVE_RGB_SHIFT 0
459
460#define SCALER_GAMDATA 0x000000e0
461#define SCALER_DLIST_START 0x00002000
462#define SCALER_DLIST_SIZE 0x00004000
463
464#define VC4_HDMI_CORE_REV 0x000
465
466#define VC4_HDMI_SW_RESET_CONTROL 0x004
467# define VC4_HDMI_SW_RESET_FORMAT_DETECT BIT(1)
468# define VC4_HDMI_SW_RESET_HDMI BIT(0)
469
470#define VC4_HDMI_HOTPLUG_INT 0x008
471
472#define VC4_HDMI_HOTPLUG 0x00c
473# define VC4_HDMI_HOTPLUG_CONNECTED BIT(0)
474
475/* 3 bits per field, where each field maps from that corresponding MAI
476 * bus channel to the given HDMI channel.
477 */
478#define VC4_HDMI_MAI_CHANNEL_MAP 0x090
479
480#define VC4_HDMI_MAI_CONFIG 0x094
481# define VC4_HDMI_MAI_CONFIG_FORMAT_REVERSE BIT(27)
482# define VC4_HDMI_MAI_CONFIG_BIT_REVERSE BIT(26)
483# define VC4_HDMI_MAI_CHANNEL_MASK_MASK VC4_MASK(15, 0)
484# define VC4_HDMI_MAI_CHANNEL_MASK_SHIFT 0
485
486/* Last received format word on the MAI bus. */
487#define VC4_HDMI_MAI_FORMAT 0x098
488
489#define VC4_HDMI_AUDIO_PACKET_CONFIG 0x09c
490# define VC4_HDMI_AUDIO_PACKET_ZERO_DATA_ON_SAMPLE_FLAT BIT(29)
491# define VC4_HDMI_AUDIO_PACKET_ZERO_DATA_ON_INACTIVE_CHANNELS BIT(24)
492# define VC4_HDMI_AUDIO_PACKET_FORCE_SAMPLE_PRESENT BIT(19)
493# define VC4_HDMI_AUDIO_PACKET_FORCE_B_FRAME BIT(18)
494# define VC4_HDMI_AUDIO_PACKET_B_FRAME_IDENTIFIER_MASK VC4_MASK(13, 10)
495# define VC4_HDMI_AUDIO_PACKET_B_FRAME_IDENTIFIER_SHIFT 10
496/* If set, then multichannel, otherwise 2 channel. */
497# define VC4_HDMI_AUDIO_PACKET_AUDIO_LAYOUT BIT(9)
498/* If set, then AUDIO_LAYOUT overrides audio_cea_mask */
499# define VC4_HDMI_AUDIO_PACKET_FORCE_AUDIO_LAYOUT BIT(8)
500# define VC4_HDMI_AUDIO_PACKET_CEA_MASK_MASK VC4_MASK(7, 0)
501# define VC4_HDMI_AUDIO_PACKET_CEA_MASK_SHIFT 0
502
503#define VC4_HDMI_RAM_PACKET_CONFIG 0x0a0
504# define VC4_HDMI_RAM_PACKET_ENABLE BIT(16)
505
506#define VC4_HDMI_RAM_PACKET_STATUS 0x0a4
507
508#define VC4_HDMI_CRP_CFG 0x0a8
509/* When set, the CTS_PERIOD counts based on MAI bus sync pulse instead
510 * of pixel clock.
511 */
512# define VC4_HDMI_CRP_USE_MAI_BUS_SYNC_FOR_CTS BIT(26)
513/* When set, no CRP packets will be sent. */
514# define VC4_HDMI_CRP_CFG_DISABLE BIT(25)
515/* If set, generates CTS values based on N, audio clock, and video
516 * clock. N must be divisible by 128.
517 */
518# define VC4_HDMI_CRP_CFG_EXTERNAL_CTS_EN BIT(24)
519# define VC4_HDMI_CRP_CFG_N_MASK VC4_MASK(19, 0)
520# define VC4_HDMI_CRP_CFG_N_SHIFT 0
521
522/* 20-bit fields containing CTS values to be transmitted if !EXTERNAL_CTS_EN */
523#define VC4_HDMI_CTS_0 0x0ac
524#define VC4_HDMI_CTS_1 0x0b0
525/* 20-bit fields containing number of clocks to send CTS0/1 before
526 * switching to the other one.
527 */
528#define VC4_HDMI_CTS_PERIOD_0 0x0b4
529#define VC4_HDMI_CTS_PERIOD_1 0x0b8
530
531#define VC4_HDMI_HORZA 0x0c4
532# define VC4_HDMI_HORZA_VPOS BIT(14)
533# define VC4_HDMI_HORZA_HPOS BIT(13)
534/* Horizontal active pixels (hdisplay). */
535# define VC4_HDMI_HORZA_HAP_MASK VC4_MASK(12, 0)
536# define VC4_HDMI_HORZA_HAP_SHIFT 0
537
538#define VC4_HDMI_HORZB 0x0c8
539/* Horizontal pack porch (htotal - hsync_end). */
540# define VC4_HDMI_HORZB_HBP_MASK VC4_MASK(29, 20)
541# define VC4_HDMI_HORZB_HBP_SHIFT 20
542/* Horizontal sync pulse (hsync_end - hsync_start). */
543# define VC4_HDMI_HORZB_HSP_MASK VC4_MASK(19, 10)
544# define VC4_HDMI_HORZB_HSP_SHIFT 10
545/* Horizontal front porch (hsync_start - hdisplay). */
546# define VC4_HDMI_HORZB_HFP_MASK VC4_MASK(9, 0)
547# define VC4_HDMI_HORZB_HFP_SHIFT 0
548
549#define VC4_HDMI_FIFO_CTL 0x05c
550# define VC4_HDMI_FIFO_CTL_RECENTER_DONE BIT(14)
551# define VC4_HDMI_FIFO_CTL_USE_EMPTY BIT(13)
552# define VC4_HDMI_FIFO_CTL_ON_VB BIT(7)
553# define VC4_HDMI_FIFO_CTL_RECENTER BIT(6)
554# define VC4_HDMI_FIFO_CTL_FIFO_RESET BIT(5)
555# define VC4_HDMI_FIFO_CTL_USE_PLL_LOCK BIT(4)
556# define VC4_HDMI_FIFO_CTL_INV_CLK_XFR BIT(3)
557# define VC4_HDMI_FIFO_CTL_CAPTURE_PTR BIT(2)
558# define VC4_HDMI_FIFO_CTL_USE_FULL BIT(1)
559# define VC4_HDMI_FIFO_CTL_MASTER_SLAVE_N BIT(0)
560# define VC4_HDMI_FIFO_VALID_WRITE_MASK 0xefff
561
562#define VC4_HDMI_SCHEDULER_CONTROL 0x0c0
563# define VC4_HDMI_SCHEDULER_CONTROL_MANUAL_FORMAT BIT(15)
564# define VC4_HDMI_SCHEDULER_CONTROL_IGNORE_VSYNC_PREDICTS BIT(5)
565# define VC4_HDMI_SCHEDULER_CONTROL_VERT_ALWAYS_KEEPOUT BIT(3)
566# define VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE BIT(1)
567# define VC4_HDMI_SCHEDULER_CONTROL_MODE_HDMI BIT(0)
568
569#define VC4_HDMI_VERTA0 0x0cc
570#define VC4_HDMI_VERTA1 0x0d4
571/* Vertical sync pulse (vsync_end - vsync_start). */
572# define VC4_HDMI_VERTA_VSP_MASK VC4_MASK(24, 20)
573# define VC4_HDMI_VERTA_VSP_SHIFT 20
574/* Vertical front porch (vsync_start - vdisplay). */
575# define VC4_HDMI_VERTA_VFP_MASK VC4_MASK(19, 13)
576# define VC4_HDMI_VERTA_VFP_SHIFT 13
577/* Vertical active lines (vdisplay). */
578# define VC4_HDMI_VERTA_VAL_MASK VC4_MASK(12, 0)
579# define VC4_HDMI_VERTA_VAL_SHIFT 0
580
581#define VC4_HDMI_VERTB0 0x0d0
582#define VC4_HDMI_VERTB1 0x0d8
583/* Vertical sync pulse offset (for interlaced) */
584# define VC4_HDMI_VERTB_VSPO_MASK VC4_MASK(21, 9)
585# define VC4_HDMI_VERTB_VSPO_SHIFT 9
586/* Vertical pack porch (vtotal - vsync_end). */
587# define VC4_HDMI_VERTB_VBP_MASK VC4_MASK(8, 0)
588# define VC4_HDMI_VERTB_VBP_SHIFT 0
589
590#define VC4_HDMI_CEC_CNTRL_1 0x0e8
591/* Set when the transmission has ended. */
592# define VC4_HDMI_CEC_TX_EOM BIT(31)
593/* If set, transmission was acked on the 1st or 2nd attempt (only one
594 * retry is attempted). If in continuous mode, this means TX needs to
595 * be filled if !TX_EOM.
596 */
597# define VC4_HDMI_CEC_TX_STATUS_GOOD BIT(30)
598# define VC4_HDMI_CEC_RX_EOM BIT(29)
599# define VC4_HDMI_CEC_RX_STATUS_GOOD BIT(28)
600/* Number of bytes received for the message. */
601# define VC4_HDMI_CEC_REC_WRD_CNT_MASK VC4_MASK(27, 24)
602# define VC4_HDMI_CEC_REC_WRD_CNT_SHIFT 24
603/* Sets continuous receive mode. Generates interrupt after each 8
604 * bytes to signal that RX_DATA should be consumed, and at RX_EOM.
605 *
606 * If disabled, maximum 16 bytes will be received (including header),
607 * and interrupt at RX_EOM. Later bytes will be acked but not put
608 * into the RX_DATA.
609 */
610# define VC4_HDMI_CEC_RX_CONTINUE BIT(23)
611# define VC4_HDMI_CEC_TX_CONTINUE BIT(22)
612/* Set this after a CEC interrupt. */
613# define VC4_HDMI_CEC_CLEAR_RECEIVE_OFF BIT(21)
614/* Starts a TX. Will wait for appropriate idel time before CEC
615 * activity. Must be cleared in between transmits.
616 */
617# define VC4_HDMI_CEC_START_XMIT_BEGIN BIT(20)
618# define VC4_HDMI_CEC_MESSAGE_LENGTH_MASK VC4_MASK(19, 16)
619# define VC4_HDMI_CEC_MESSAGE_LENGTH_SHIFT 16
620/* Device's CEC address */
621# define VC4_HDMI_CEC_ADDR_MASK VC4_MASK(15, 12)
622# define VC4_HDMI_CEC_ADDR_SHIFT 12
623/* Divides off of HSM clock to generate CEC bit clock. */
624/* With the current defaults the CEC bit clock is 40 kHz = 25 usec */
625# define VC4_HDMI_CEC_DIV_CLK_CNT_MASK VC4_MASK(11, 0)
626# define VC4_HDMI_CEC_DIV_CLK_CNT_SHIFT 0
627
628/* Set these fields to how many bit clock cycles get to that many
629 * microseconds.
630 */
631#define VC4_HDMI_CEC_CNTRL_2 0x0ec
632# define VC4_HDMI_CEC_CNT_TO_1500_US_MASK VC4_MASK(30, 24)
633# define VC4_HDMI_CEC_CNT_TO_1500_US_SHIFT 24
634# define VC4_HDMI_CEC_CNT_TO_1300_US_MASK VC4_MASK(23, 17)
635# define VC4_HDMI_CEC_CNT_TO_1300_US_SHIFT 17
636# define VC4_HDMI_CEC_CNT_TO_800_US_MASK VC4_MASK(16, 11)
637# define VC4_HDMI_CEC_CNT_TO_800_US_SHIFT 11
638# define VC4_HDMI_CEC_CNT_TO_600_US_MASK VC4_MASK(10, 5)
639# define VC4_HDMI_CEC_CNT_TO_600_US_SHIFT 5
640# define VC4_HDMI_CEC_CNT_TO_400_US_MASK VC4_MASK(4, 0)
641# define VC4_HDMI_CEC_CNT_TO_400_US_SHIFT 0
642
643#define VC4_HDMI_CEC_CNTRL_3 0x0f0
644# define VC4_HDMI_CEC_CNT_TO_2750_US_MASK VC4_MASK(31, 24)
645# define VC4_HDMI_CEC_CNT_TO_2750_US_SHIFT 24
646# define VC4_HDMI_CEC_CNT_TO_2400_US_MASK VC4_MASK(23, 16)
647# define VC4_HDMI_CEC_CNT_TO_2400_US_SHIFT 16
648# define VC4_HDMI_CEC_CNT_TO_2050_US_MASK VC4_MASK(15, 8)
649# define VC4_HDMI_CEC_CNT_TO_2050_US_SHIFT 8
650# define VC4_HDMI_CEC_CNT_TO_1700_US_MASK VC4_MASK(7, 0)
651# define VC4_HDMI_CEC_CNT_TO_1700_US_SHIFT 0
652
653#define VC4_HDMI_CEC_CNTRL_4 0x0f4
654# define VC4_HDMI_CEC_CNT_TO_4300_US_MASK VC4_MASK(31, 24)
655# define VC4_HDMI_CEC_CNT_TO_4300_US_SHIFT 24
656# define VC4_HDMI_CEC_CNT_TO_3900_US_MASK VC4_MASK(23, 16)
657# define VC4_HDMI_CEC_CNT_TO_3900_US_SHIFT 16
658# define VC4_HDMI_CEC_CNT_TO_3600_US_MASK VC4_MASK(15, 8)
659# define VC4_HDMI_CEC_CNT_TO_3600_US_SHIFT 8
660# define VC4_HDMI_CEC_CNT_TO_3500_US_MASK VC4_MASK(7, 0)
661# define VC4_HDMI_CEC_CNT_TO_3500_US_SHIFT 0
662
663#define VC4_HDMI_CEC_CNTRL_5 0x0f8
664# define VC4_HDMI_CEC_TX_SW_RESET BIT(27)
665# define VC4_HDMI_CEC_RX_SW_RESET BIT(26)
666# define VC4_HDMI_CEC_PAD_SW_RESET BIT(25)
667# define VC4_HDMI_CEC_MUX_TP_OUT_CEC BIT(24)
668# define VC4_HDMI_CEC_RX_CEC_INT BIT(23)
669# define VC4_HDMI_CEC_CLK_PRELOAD_MASK VC4_MASK(22, 16)
670# define VC4_HDMI_CEC_CLK_PRELOAD_SHIFT 16
671# define VC4_HDMI_CEC_CNT_TO_4700_US_MASK VC4_MASK(15, 8)
672# define VC4_HDMI_CEC_CNT_TO_4700_US_SHIFT 8
673# define VC4_HDMI_CEC_CNT_TO_4500_US_MASK VC4_MASK(7, 0)
674# define VC4_HDMI_CEC_CNT_TO_4500_US_SHIFT 0
675
676/* Transmit data, first byte is low byte of the 32-bit reg. MSB of
677 * each byte transmitted first.
678 */
679#define VC4_HDMI_CEC_TX_DATA_1 0x0fc
680#define VC4_HDMI_CEC_TX_DATA_2 0x100
681#define VC4_HDMI_CEC_TX_DATA_3 0x104
682#define VC4_HDMI_CEC_TX_DATA_4 0x108
683#define VC4_HDMI_CEC_RX_DATA_1 0x10c
684#define VC4_HDMI_CEC_RX_DATA_2 0x110
685#define VC4_HDMI_CEC_RX_DATA_3 0x114
686#define VC4_HDMI_CEC_RX_DATA_4 0x118
687
688#define VC4_HDMI_TX_PHY_RESET_CTL 0x2c0
689
690#define VC4_HDMI_TX_PHY_CTL0 0x2c4
691# define VC4_HDMI_TX_PHY_RNG_PWRDN BIT(25)
692
693/* Interrupt status bits */
694#define VC4_HDMI_CPU_STATUS 0x340
695#define VC4_HDMI_CPU_SET 0x344
696#define VC4_HDMI_CPU_CLEAR 0x348
697# define VC4_HDMI_CPU_CEC BIT(6)
698# define VC4_HDMI_CPU_HOTPLUG BIT(0)
699
700#define VC4_HDMI_CPU_MASK_STATUS 0x34c
701#define VC4_HDMI_CPU_MASK_SET 0x350
702#define VC4_HDMI_CPU_MASK_CLEAR 0x354
703
704#define VC4_HDMI_GCP(x) (0x400 + ((x) * 0x4))
705#define VC4_HDMI_RAM_PACKET(x) (0x400 + ((x) * 0x24))
706#define VC4_HDMI_PACKET_STRIDE 0x24
707
708#define VC4_HD_M_CTL 0x00c
709/* Debug: Current receive value on the CEC pad. */
710# define VC4_HD_CECRXD BIT(9)
711/* Debug: Override CEC output to 0. */
712# define VC4_HD_CECOVR BIT(8)
713# define VC4_HD_M_REGISTER_FILE_STANDBY (3 << 6)
714# define VC4_HD_M_RAM_STANDBY (3 << 4)
715# define VC4_HD_M_SW_RST BIT(2)
716# define VC4_HD_M_ENABLE BIT(0)
717
718#define VC4_HD_MAI_CTL 0x014
719/* Set when audio stream is received at a slower rate than the
720 * sampling period, so MAI fifo goes empty. Write 1 to clear.
721 */
722# define VC4_HD_MAI_CTL_DLATE BIT(15)
723# define VC4_HD_MAI_CTL_BUSY BIT(14)
724# define VC4_HD_MAI_CTL_CHALIGN BIT(13)
725# define VC4_HD_MAI_CTL_WHOLSMP BIT(12)
726# define VC4_HD_MAI_CTL_FULL BIT(11)
727# define VC4_HD_MAI_CTL_EMPTY BIT(10)
728# define VC4_HD_MAI_CTL_FLUSH BIT(9)
729/* If set, MAI bus generates SPDIF (bit 31) parity instead of passing
730 * through.
731 */
732# define VC4_HD_MAI_CTL_PAREN BIT(8)
733# define VC4_HD_MAI_CTL_CHNUM_MASK VC4_MASK(7, 4)
734# define VC4_HD_MAI_CTL_CHNUM_SHIFT 4
735# define VC4_HD_MAI_CTL_ENABLE BIT(3)
736/* Underflow error status bit, write 1 to clear. */
737# define VC4_HD_MAI_CTL_ERRORE BIT(2)
738/* Overflow error status bit, write 1 to clear. */
739# define VC4_HD_MAI_CTL_ERRORF BIT(1)
740/* Single-shot reset bit. Read value is undefined. */
741# define VC4_HD_MAI_CTL_RESET BIT(0)
742
743#define VC4_HD_MAI_THR 0x018
744# define VC4_HD_MAI_THR_PANICHIGH_MASK VC4_MASK(29, 24)
745# define VC4_HD_MAI_THR_PANICHIGH_SHIFT 24
746# define VC4_HD_MAI_THR_PANICLOW_MASK VC4_MASK(21, 16)
747# define VC4_HD_MAI_THR_PANICLOW_SHIFT 16
748# define VC4_HD_MAI_THR_DREQHIGH_MASK VC4_MASK(13, 8)
749# define VC4_HD_MAI_THR_DREQHIGH_SHIFT 8
750# define VC4_HD_MAI_THR_DREQLOW_MASK VC4_MASK(5, 0)
751# define VC4_HD_MAI_THR_DREQLOW_SHIFT 0
752
753/* Format header to be placed on the MAI data. Unused. */
754#define VC4_HD_MAI_FMT 0x01c
755
756/* Register for DMAing in audio data to be transported over the MAI
757 * bus to the Falcon core.
758 */
759#define VC4_HD_MAI_DATA 0x020
760
761/* Divider from HDMI HSM clock to MAI serial clock. Sampling period
762 * converges to N / (M + 1) cycles.
763 */
764#define VC4_HD_MAI_SMP 0x02c
765# define VC4_HD_MAI_SMP_N_MASK VC4_MASK(31, 8)
766# define VC4_HD_MAI_SMP_N_SHIFT 8
767# define VC4_HD_MAI_SMP_M_MASK VC4_MASK(7, 0)
768# define VC4_HD_MAI_SMP_M_SHIFT 0
769
770#define VC4_HD_VID_CTL 0x038
771# define VC4_HD_VID_CTL_ENABLE BIT(31)
772# define VC4_HD_VID_CTL_UNDERFLOW_ENABLE BIT(30)
773# define VC4_HD_VID_CTL_FRAME_COUNTER_RESET BIT(29)
774# define VC4_HD_VID_CTL_VSYNC_LOW BIT(28)
775# define VC4_HD_VID_CTL_HSYNC_LOW BIT(27)
776
777#define VC4_HD_CSC_CTL 0x040
778# define VC4_HD_CSC_CTL_ORDER_MASK VC4_MASK(7, 5)
779# define VC4_HD_CSC_CTL_ORDER_SHIFT 5
780# define VC4_HD_CSC_CTL_ORDER_RGB 0
781# define VC4_HD_CSC_CTL_ORDER_BGR 1
782# define VC4_HD_CSC_CTL_ORDER_BRG 2
783# define VC4_HD_CSC_CTL_ORDER_GRB 3
784# define VC4_HD_CSC_CTL_ORDER_GBR 4
785# define VC4_HD_CSC_CTL_ORDER_RBG 5
786# define VC4_HD_CSC_CTL_PADMSB BIT(4)
787# define VC4_HD_CSC_CTL_MODE_MASK VC4_MASK(3, 2)
788# define VC4_HD_CSC_CTL_MODE_SHIFT 2
789# define VC4_HD_CSC_CTL_MODE_RGB_TO_SD_YPRPB 0
790# define VC4_HD_CSC_CTL_MODE_RGB_TO_HD_YPRPB 1
791# define VC4_HD_CSC_CTL_MODE_CUSTOM 3
792# define VC4_HD_CSC_CTL_RGB2YCC BIT(1)
793# define VC4_HD_CSC_CTL_ENABLE BIT(0)
794
795#define VC4_HD_CSC_12_11 0x044
796#define VC4_HD_CSC_14_13 0x048
797#define VC4_HD_CSC_22_21 0x04c
798#define VC4_HD_CSC_24_23 0x050
799#define VC4_HD_CSC_32_31 0x054
800#define VC4_HD_CSC_34_33 0x058
801
802#define VC4_HD_FRAME_COUNT 0x068
803
804/* HVS display list information. */
805#define HVS_BOOTLOADER_DLIST_END 32
806
807enum hvs_pixel_format {
808 /* 8bpp */
809 HVS_PIXEL_FORMAT_RGB332 = 0,
810 /* 16bpp */
811 HVS_PIXEL_FORMAT_RGBA4444 = 1,
812 HVS_PIXEL_FORMAT_RGB555 = 2,
813 HVS_PIXEL_FORMAT_RGBA5551 = 3,
814 HVS_PIXEL_FORMAT_RGB565 = 4,
815 /* 24bpp */
816 HVS_PIXEL_FORMAT_RGB888 = 5,
817 HVS_PIXEL_FORMAT_RGBA6666 = 6,
818 /* 32bpp */
819 HVS_PIXEL_FORMAT_RGBA8888 = 7,
820
821 HVS_PIXEL_FORMAT_YCBCR_YUV420_3PLANE = 8,
822 HVS_PIXEL_FORMAT_YCBCR_YUV420_2PLANE = 9,
823 HVS_PIXEL_FORMAT_YCBCR_YUV422_3PLANE = 10,
824 HVS_PIXEL_FORMAT_YCBCR_YUV422_2PLANE = 11,
825 HVS_PIXEL_FORMAT_H264 = 12,
826 HVS_PIXEL_FORMAT_PALETTE = 13,
827 HVS_PIXEL_FORMAT_YUV444_RGB = 14,
828 HVS_PIXEL_FORMAT_AYUV444_RGB = 15,
829};
830
831/* Note: the LSB is the rightmost character shown. Only valid for
832 * HVS_PIXEL_FORMAT_RGB8888, not RGB888.
833 */
834#define HVS_PIXEL_ORDER_RGBA 0
835#define HVS_PIXEL_ORDER_BGRA 1
836#define HVS_PIXEL_ORDER_ARGB 2
837#define HVS_PIXEL_ORDER_ABGR 3
838
839#define HVS_PIXEL_ORDER_XBRG 0
840#define HVS_PIXEL_ORDER_XRBG 1
841#define HVS_PIXEL_ORDER_XRGB 2
842#define HVS_PIXEL_ORDER_XBGR 3
843
844#define HVS_PIXEL_ORDER_XYCBCR 0
845#define HVS_PIXEL_ORDER_XYCRCB 1
846#define HVS_PIXEL_ORDER_YXCBCR 2
847#define HVS_PIXEL_ORDER_YXCRCB 3
848
849#define SCALER_CTL0_END BIT(31)
850#define SCALER_CTL0_VALID BIT(30)
851
852#define SCALER_CTL0_SIZE_MASK VC4_MASK(29, 24)
853#define SCALER_CTL0_SIZE_SHIFT 24
854
855#define SCALER_CTL0_TILING_MASK VC4_MASK(21, 20)
856#define SCALER_CTL0_TILING_SHIFT 20
857#define SCALER_CTL0_TILING_LINEAR 0
858#define SCALER_CTL0_TILING_64B 1
859#define SCALER_CTL0_TILING_128B 2
860#define SCALER_CTL0_TILING_256B_OR_T 3
861
862#define SCALER_CTL0_ALPHA_MASK BIT(19)
863#define SCALER_CTL0_HFLIP BIT(16)
864#define SCALER_CTL0_VFLIP BIT(15)
865
866#define SCALER_CTL0_KEY_MODE_MASK VC4_MASK(18, 17)
867#define SCALER_CTL0_KEY_MODE_SHIFT 17
868#define SCALER_CTL0_KEY_DISABLED 0
869#define SCALER_CTL0_KEY_LUMA_OR_COMMON_RGB 1
870#define SCALER_CTL0_KEY_MATCH 2 /* turn transparent */
871#define SCALER_CTL0_KEY_REPLACE 3 /* replace with value from key mask word 2 */
872
873#define SCALER_CTL0_ORDER_MASK VC4_MASK(14, 13)
874#define SCALER_CTL0_ORDER_SHIFT 13
875
876#define SCALER_CTL0_RGBA_EXPAND_MASK VC4_MASK(12, 11)
877#define SCALER_CTL0_RGBA_EXPAND_SHIFT 11
878#define SCALER_CTL0_RGBA_EXPAND_ZERO 0
879#define SCALER_CTL0_RGBA_EXPAND_LSB 1
880#define SCALER_CTL0_RGBA_EXPAND_MSB 2
881#define SCALER_CTL0_RGBA_EXPAND_ROUND 3
882
883#define SCALER_CTL0_SCL1_MASK VC4_MASK(10, 8)
884#define SCALER_CTL0_SCL1_SHIFT 8
885
886#define SCALER_CTL0_SCL0_MASK VC4_MASK(7, 5)
887#define SCALER_CTL0_SCL0_SHIFT 5
888
889#define SCALER_CTL0_SCL_H_PPF_V_PPF 0
890#define SCALER_CTL0_SCL_H_TPZ_V_PPF 1
891#define SCALER_CTL0_SCL_H_PPF_V_TPZ 2
892#define SCALER_CTL0_SCL_H_TPZ_V_TPZ 3
893#define SCALER_CTL0_SCL_H_PPF_V_NONE 4
894#define SCALER_CTL0_SCL_H_NONE_V_PPF 5
895#define SCALER_CTL0_SCL_H_NONE_V_TPZ 6
896#define SCALER_CTL0_SCL_H_TPZ_V_NONE 7
897
898/* Set to indicate no scaling. */
899#define SCALER_CTL0_UNITY BIT(4)
900
901#define SCALER_CTL0_PIXEL_FORMAT_MASK VC4_MASK(3, 0)
902#define SCALER_CTL0_PIXEL_FORMAT_SHIFT 0
903
904#define SCALER_POS0_FIXED_ALPHA_MASK VC4_MASK(31, 24)
905#define SCALER_POS0_FIXED_ALPHA_SHIFT 24
906
907#define SCALER_POS0_START_Y_MASK VC4_MASK(23, 12)
908#define SCALER_POS0_START_Y_SHIFT 12
909
910#define SCALER_POS0_START_X_MASK VC4_MASK(11, 0)
911#define SCALER_POS0_START_X_SHIFT 0
912
913#define SCALER_POS1_SCL_HEIGHT_MASK VC4_MASK(27, 16)
914#define SCALER_POS1_SCL_HEIGHT_SHIFT 16
915
916#define SCALER_POS1_SCL_WIDTH_MASK VC4_MASK(11, 0)
917#define SCALER_POS1_SCL_WIDTH_SHIFT 0
918
919#define SCALER_POS2_ALPHA_MODE_MASK VC4_MASK(31, 30)
920#define SCALER_POS2_ALPHA_MODE_SHIFT 30
921#define SCALER_POS2_ALPHA_MODE_PIPELINE 0
922#define SCALER_POS2_ALPHA_MODE_FIXED 1
923#define SCALER_POS2_ALPHA_MODE_FIXED_NONZERO 2
924#define SCALER_POS2_ALPHA_MODE_FIXED_OVER_0x07 3
925#define SCALER_POS2_ALPHA_PREMULT BIT(29)
926#define SCALER_POS2_ALPHA_MIX BIT(28)
927
928#define SCALER_POS2_HEIGHT_MASK VC4_MASK(27, 16)
929#define SCALER_POS2_HEIGHT_SHIFT 16
930
931#define SCALER_POS2_WIDTH_MASK VC4_MASK(11, 0)
932#define SCALER_POS2_WIDTH_SHIFT 0
933
934/* Color Space Conversion words. Some values are S2.8 signed
935 * integers, except that the 2 integer bits map as {0x0: 0, 0x1: 1,
936 * 0x2: 2, 0x3: -1}
937 */
938/* bottom 8 bits of S2.8 contribution of Cr to Blue */
939#define SCALER_CSC0_COEF_CR_BLU_MASK VC4_MASK(31, 24)
940#define SCALER_CSC0_COEF_CR_BLU_SHIFT 24
941/* Signed offset to apply to Y before CSC. (Y' = Y + YY_OFS) */
942#define SCALER_CSC0_COEF_YY_OFS_MASK VC4_MASK(23, 16)
943#define SCALER_CSC0_COEF_YY_OFS_SHIFT 16
944/* Signed offset to apply to CB before CSC (Cb' = Cb - 128 + CB_OFS). */
945#define SCALER_CSC0_COEF_CB_OFS_MASK VC4_MASK(15, 8)
946#define SCALER_CSC0_COEF_CB_OFS_SHIFT 8
947/* Signed offset to apply to CB before CSC (Cr' = Cr - 128 + CR_OFS). */
948#define SCALER_CSC0_COEF_CR_OFS_MASK VC4_MASK(7, 0)
949#define SCALER_CSC0_COEF_CR_OFS_SHIFT 0
950#define SCALER_CSC0_ITR_R_601_5 0x00f00000
951#define SCALER_CSC0_ITR_R_709_3 0x00f00000
952#define SCALER_CSC0_JPEG_JFIF 0x00000000
953
954/* S2.8 contribution of Cb to Green */
955#define SCALER_CSC1_COEF_CB_GRN_MASK VC4_MASK(31, 22)
956#define SCALER_CSC1_COEF_CB_GRN_SHIFT 22
957/* S2.8 contribution of Cr to Green */
958#define SCALER_CSC1_COEF_CR_GRN_MASK VC4_MASK(21, 12)
959#define SCALER_CSC1_COEF_CR_GRN_SHIFT 12
960/* S2.8 contribution of Y to all of RGB */
961#define SCALER_CSC1_COEF_YY_ALL_MASK VC4_MASK(11, 2)
962#define SCALER_CSC1_COEF_YY_ALL_SHIFT 2
963/* top 2 bits of S2.8 contribution of Cr to Blue */
964#define SCALER_CSC1_COEF_CR_BLU_MASK VC4_MASK(1, 0)
965#define SCALER_CSC1_COEF_CR_BLU_SHIFT 0
966#define SCALER_CSC1_ITR_R_601_5 0xe73304a8
967#define SCALER_CSC1_ITR_R_709_3 0xf2b784a8
968#define SCALER_CSC1_JPEG_JFIF 0xea34a400
969
970/* S2.8 contribution of Cb to Red */
971#define SCALER_CSC2_COEF_CB_RED_MASK VC4_MASK(29, 20)
972#define SCALER_CSC2_COEF_CB_RED_SHIFT 20
973/* S2.8 contribution of Cr to Red */
974#define SCALER_CSC2_COEF_CR_RED_MASK VC4_MASK(19, 10)
975#define SCALER_CSC2_COEF_CR_RED_SHIFT 10
976/* S2.8 contribution of Cb to Blue */
977#define SCALER_CSC2_COEF_CB_BLU_MASK VC4_MASK(19, 10)
978#define SCALER_CSC2_COEF_CB_BLU_SHIFT 10
979#define SCALER_CSC2_ITR_R_601_5 0x00066204
980#define SCALER_CSC2_ITR_R_709_3 0x00072a1c
981#define SCALER_CSC2_JPEG_JFIF 0x000599c5
982
983#define SCALER_TPZ0_VERT_RECALC BIT(31)
984#define SCALER_TPZ0_SCALE_MASK VC4_MASK(28, 8)
985#define SCALER_TPZ0_SCALE_SHIFT 8
986#define SCALER_TPZ0_IPHASE_MASK VC4_MASK(7, 0)
987#define SCALER_TPZ0_IPHASE_SHIFT 0
988#define SCALER_TPZ1_RECIP_MASK VC4_MASK(15, 0)
989#define SCALER_TPZ1_RECIP_SHIFT 0
990
991/* Skips interpolating coefficients to 64 phases, so just 8 are used.
992 * Required for nearest neighbor.
993 */
994#define SCALER_PPF_NOINTERP BIT(31)
995/* Replaes the highest valued coefficient with one that makes all 4
996 * sum to unity.
997 */
998#define SCALER_PPF_AGC BIT(30)
999#define SCALER_PPF_SCALE_MASK VC4_MASK(24, 8)
1000#define SCALER_PPF_SCALE_SHIFT 8
1001#define SCALER_PPF_IPHASE_MASK VC4_MASK(6, 0)
1002#define SCALER_PPF_IPHASE_SHIFT 0
1003
1004#define SCALER_PPF_KERNEL_OFFSET_MASK VC4_MASK(13, 0)
1005#define SCALER_PPF_KERNEL_OFFSET_SHIFT 0
1006#define SCALER_PPF_KERNEL_UNCACHED BIT(31)
1007
1008/* PITCH0/1/2 fields for raster. */
1009#define SCALER_SRC_PITCH_MASK VC4_MASK(15, 0)
1010#define SCALER_SRC_PITCH_SHIFT 0
1011
1012/* PITCH0/1/2 fields for tiled (SAND). */
1013#define SCALER_TILE_SKIP_0_MASK VC4_MASK(18, 16)
1014#define SCALER_TILE_SKIP_0_SHIFT 16
1015#define SCALER_TILE_HEIGHT_MASK VC4_MASK(15, 0)
1016#define SCALER_TILE_HEIGHT_SHIFT 0
1017
1018/* Common PITCH0 fields */
1019#define SCALER_PITCH0_SINK_PIX_MASK VC4_MASK(31, 26)
1020#define SCALER_PITCH0_SINK_PIX_SHIFT 26
1021
1022/* PITCH0 fields for T-tiled. */
1023#define SCALER_PITCH0_TILE_WIDTH_L_MASK VC4_MASK(22, 16)
1024#define SCALER_PITCH0_TILE_WIDTH_L_SHIFT 16
1025#define SCALER_PITCH0_TILE_LINE_DIR BIT(15)
1026#define SCALER_PITCH0_TILE_INITIAL_LINE_DIR BIT(14)
1027/* Y offset within a tile. */
1028#define SCALER_PITCH0_TILE_Y_OFFSET_MASK VC4_MASK(13, 8)
1029#define SCALER_PITCH0_TILE_Y_OFFSET_SHIFT 8
1030#define SCALER_PITCH0_TILE_WIDTH_R_MASK VC4_MASK(6, 0)
1031#define SCALER_PITCH0_TILE_WIDTH_R_SHIFT 0
1032
1033#endif /* VC4_REGS_H */