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1/* SPDX-License-Identifier: GPL-2.0-only */
2/*
3 * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd
4 * Author:Mark Yao <mark.yao@rock-chips.com>
5 */
6
7#ifndef _ROCKCHIP_VOP_REG_H
8#define _ROCKCHIP_VOP_REG_H
9
10/* rk3288 register definition */
11#define RK3288_REG_CFG_DONE 0x0000
12#define RK3288_VERSION_INFO 0x0004
13#define RK3288_SYS_CTRL 0x0008
14#define RK3288_SYS_CTRL1 0x000c
15#define RK3288_DSP_CTRL0 0x0010
16#define RK3288_DSP_CTRL1 0x0014
17#define RK3288_DSP_BG 0x0018
18#define RK3288_MCU_CTRL 0x001c
19#define RK3288_INTR_CTRL0 0x0020
20#define RK3288_INTR_CTRL1 0x0024
21#define RK3288_WIN0_CTRL0 0x0030
22#define RK3288_WIN0_CTRL1 0x0034
23#define RK3288_WIN0_COLOR_KEY 0x0038
24#define RK3288_WIN0_VIR 0x003c
25#define RK3288_WIN0_YRGB_MST 0x0040
26#define RK3288_WIN0_CBR_MST 0x0044
27#define RK3288_WIN0_ACT_INFO 0x0048
28#define RK3288_WIN0_DSP_INFO 0x004c
29#define RK3288_WIN0_DSP_ST 0x0050
30#define RK3288_WIN0_SCL_FACTOR_YRGB 0x0054
31#define RK3288_WIN0_SCL_FACTOR_CBR 0x0058
32#define RK3288_WIN0_SCL_OFFSET 0x005c
33#define RK3288_WIN0_SRC_ALPHA_CTRL 0x0060
34#define RK3288_WIN0_DST_ALPHA_CTRL 0x0064
35#define RK3288_WIN0_FADING_CTRL 0x0068
36#define RK3288_WIN0_CTRL2 0x006c
37
38/* win1 register */
39#define RK3288_WIN1_CTRL0 0x0070
40#define RK3288_WIN1_CTRL1 0x0074
41#define RK3288_WIN1_COLOR_KEY 0x0078
42#define RK3288_WIN1_VIR 0x007c
43#define RK3288_WIN1_YRGB_MST 0x0080
44#define RK3288_WIN1_CBR_MST 0x0084
45#define RK3288_WIN1_ACT_INFO 0x0088
46#define RK3288_WIN1_DSP_INFO 0x008c
47#define RK3288_WIN1_DSP_ST 0x0090
48#define RK3288_WIN1_SCL_FACTOR_YRGB 0x0094
49#define RK3288_WIN1_SCL_FACTOR_CBR 0x0098
50#define RK3288_WIN1_SCL_OFFSET 0x009c
51#define RK3288_WIN1_SRC_ALPHA_CTRL 0x00a0
52#define RK3288_WIN1_DST_ALPHA_CTRL 0x00a4
53#define RK3288_WIN1_FADING_CTRL 0x00a8
54/* win2 register */
55#define RK3288_WIN2_CTRL0 0x00b0
56#define RK3288_WIN2_CTRL1 0x00b4
57#define RK3288_WIN2_VIR0_1 0x00b8
58#define RK3288_WIN2_VIR2_3 0x00bc
59#define RK3288_WIN2_MST0 0x00c0
60#define RK3288_WIN2_DSP_INFO0 0x00c4
61#define RK3288_WIN2_DSP_ST0 0x00c8
62#define RK3288_WIN2_COLOR_KEY 0x00cc
63#define RK3288_WIN2_MST1 0x00d0
64#define RK3288_WIN2_DSP_INFO1 0x00d4
65#define RK3288_WIN2_DSP_ST1 0x00d8
66#define RK3288_WIN2_SRC_ALPHA_CTRL 0x00dc
67#define RK3288_WIN2_MST2 0x00e0
68#define RK3288_WIN2_DSP_INFO2 0x00e4
69#define RK3288_WIN2_DSP_ST2 0x00e8
70#define RK3288_WIN2_DST_ALPHA_CTRL 0x00ec
71#define RK3288_WIN2_MST3 0x00f0
72#define RK3288_WIN2_DSP_INFO3 0x00f4
73#define RK3288_WIN2_DSP_ST3 0x00f8
74#define RK3288_WIN2_FADING_CTRL 0x00fc
75/* win3 register */
76#define RK3288_WIN3_CTRL0 0x0100
77#define RK3288_WIN3_CTRL1 0x0104
78#define RK3288_WIN3_VIR0_1 0x0108
79#define RK3288_WIN3_VIR2_3 0x010c
80#define RK3288_WIN3_MST0 0x0110
81#define RK3288_WIN3_DSP_INFO0 0x0114
82#define RK3288_WIN3_DSP_ST0 0x0118
83#define RK3288_WIN3_COLOR_KEY 0x011c
84#define RK3288_WIN3_MST1 0x0120
85#define RK3288_WIN3_DSP_INFO1 0x0124
86#define RK3288_WIN3_DSP_ST1 0x0128
87#define RK3288_WIN3_SRC_ALPHA_CTRL 0x012c
88#define RK3288_WIN3_MST2 0x0130
89#define RK3288_WIN3_DSP_INFO2 0x0134
90#define RK3288_WIN3_DSP_ST2 0x0138
91#define RK3288_WIN3_DST_ALPHA_CTRL 0x013c
92#define RK3288_WIN3_MST3 0x0140
93#define RK3288_WIN3_DSP_INFO3 0x0144
94#define RK3288_WIN3_DSP_ST3 0x0148
95#define RK3288_WIN3_FADING_CTRL 0x014c
96/* hwc register */
97#define RK3288_HWC_CTRL0 0x0150
98#define RK3288_HWC_CTRL1 0x0154
99#define RK3288_HWC_MST 0x0158
100#define RK3288_HWC_DSP_ST 0x015c
101#define RK3288_HWC_SRC_ALPHA_CTRL 0x0160
102#define RK3288_HWC_DST_ALPHA_CTRL 0x0164
103#define RK3288_HWC_FADING_CTRL 0x0168
104/* post process register */
105#define RK3288_POST_DSP_HACT_INFO 0x0170
106#define RK3288_POST_DSP_VACT_INFO 0x0174
107#define RK3288_POST_SCL_FACTOR_YRGB 0x0178
108#define RK3288_POST_SCL_CTRL 0x0180
109#define RK3288_POST_DSP_VACT_INFO_F1 0x0184
110#define RK3288_DSP_HTOTAL_HS_END 0x0188
111#define RK3288_DSP_HACT_ST_END 0x018c
112#define RK3288_DSP_VTOTAL_VS_END 0x0190
113#define RK3288_DSP_VACT_ST_END 0x0194
114#define RK3288_DSP_VS_ST_END_F1 0x0198
115#define RK3288_DSP_VACT_ST_END_F1 0x019c
116/* register definition end */
117
118/* rk3368 register definition */
119#define RK3368_REG_CFG_DONE 0x0000
120#define RK3368_VERSION_INFO 0x0004
121#define RK3368_SYS_CTRL 0x0008
122#define RK3368_SYS_CTRL1 0x000c
123#define RK3368_DSP_CTRL0 0x0010
124#define RK3368_DSP_CTRL1 0x0014
125#define RK3368_DSP_BG 0x0018
126#define RK3368_MCU_CTRL 0x001c
127#define RK3368_LINE_FLAG 0x0020
128#define RK3368_INTR_EN 0x0024
129#define RK3368_INTR_CLEAR 0x0028
130#define RK3368_INTR_STATUS 0x002c
131#define RK3368_WIN0_CTRL0 0x0030
132#define RK3368_WIN0_CTRL1 0x0034
133#define RK3368_WIN0_COLOR_KEY 0x0038
134#define RK3368_WIN0_VIR 0x003c
135#define RK3368_WIN0_YRGB_MST 0x0040
136#define RK3368_WIN0_CBR_MST 0x0044
137#define RK3368_WIN0_ACT_INFO 0x0048
138#define RK3368_WIN0_DSP_INFO 0x004c
139#define RK3368_WIN0_DSP_ST 0x0050
140#define RK3368_WIN0_SCL_FACTOR_YRGB 0x0054
141#define RK3368_WIN0_SCL_FACTOR_CBR 0x0058
142#define RK3368_WIN0_SCL_OFFSET 0x005c
143#define RK3368_WIN0_SRC_ALPHA_CTRL 0x0060
144#define RK3368_WIN0_DST_ALPHA_CTRL 0x0064
145#define RK3368_WIN0_FADING_CTRL 0x0068
146#define RK3368_WIN0_CTRL2 0x006c
147#define RK3368_WIN1_CTRL0 0x0070
148#define RK3368_WIN1_CTRL1 0x0074
149#define RK3368_WIN1_COLOR_KEY 0x0078
150#define RK3368_WIN1_VIR 0x007c
151#define RK3368_WIN1_YRGB_MST 0x0080
152#define RK3368_WIN1_CBR_MST 0x0084
153#define RK3368_WIN1_ACT_INFO 0x0088
154#define RK3368_WIN1_DSP_INFO 0x008c
155#define RK3368_WIN1_DSP_ST 0x0090
156#define RK3368_WIN1_SCL_FACTOR_YRGB 0x0094
157#define RK3368_WIN1_SCL_FACTOR_CBR 0x0098
158#define RK3368_WIN1_SCL_OFFSET 0x009c
159#define RK3368_WIN1_SRC_ALPHA_CTRL 0x00a0
160#define RK3368_WIN1_DST_ALPHA_CTRL 0x00a4
161#define RK3368_WIN1_FADING_CTRL 0x00a8
162#define RK3368_WIN1_CTRL2 0x00ac
163#define RK3368_WIN2_CTRL0 0x00b0
164#define RK3368_WIN2_CTRL1 0x00b4
165#define RK3368_WIN2_VIR0_1 0x00b8
166#define RK3368_WIN2_VIR2_3 0x00bc
167#define RK3368_WIN2_MST0 0x00c0
168#define RK3368_WIN2_DSP_INFO0 0x00c4
169#define RK3368_WIN2_DSP_ST0 0x00c8
170#define RK3368_WIN2_COLOR_KEY 0x00cc
171#define RK3368_WIN2_MST1 0x00d0
172#define RK3368_WIN2_DSP_INFO1 0x00d4
173#define RK3368_WIN2_DSP_ST1 0x00d8
174#define RK3368_WIN2_SRC_ALPHA_CTRL 0x00dc
175#define RK3368_WIN2_MST2 0x00e0
176#define RK3368_WIN2_DSP_INFO2 0x00e4
177#define RK3368_WIN2_DSP_ST2 0x00e8
178#define RK3368_WIN2_DST_ALPHA_CTRL 0x00ec
179#define RK3368_WIN2_MST3 0x00f0
180#define RK3368_WIN2_DSP_INFO3 0x00f4
181#define RK3368_WIN2_DSP_ST3 0x00f8
182#define RK3368_WIN2_FADING_CTRL 0x00fc
183#define RK3368_WIN3_CTRL0 0x0100
184#define RK3368_WIN3_CTRL1 0x0104
185#define RK3368_WIN3_VIR0_1 0x0108
186#define RK3368_WIN3_VIR2_3 0x010c
187#define RK3368_WIN3_MST0 0x0110
188#define RK3368_WIN3_DSP_INFO0 0x0114
189#define RK3368_WIN3_DSP_ST0 0x0118
190#define RK3368_WIN3_COLOR_KEY 0x011c
191#define RK3368_WIN3_MST1 0x0120
192#define RK3368_WIN3_DSP_INFO1 0x0124
193#define RK3368_WIN3_DSP_ST1 0x0128
194#define RK3368_WIN3_SRC_ALPHA_CTRL 0x012c
195#define RK3368_WIN3_MST2 0x0130
196#define RK3368_WIN3_DSP_INFO2 0x0134
197#define RK3368_WIN3_DSP_ST2 0x0138
198#define RK3368_WIN3_DST_ALPHA_CTRL 0x013c
199#define RK3368_WIN3_MST3 0x0140
200#define RK3368_WIN3_DSP_INFO3 0x0144
201#define RK3368_WIN3_DSP_ST3 0x0148
202#define RK3368_WIN3_FADING_CTRL 0x014c
203#define RK3368_HWC_CTRL0 0x0150
204#define RK3368_HWC_CTRL1 0x0154
205#define RK3368_HWC_MST 0x0158
206#define RK3368_HWC_DSP_ST 0x015c
207#define RK3368_HWC_SRC_ALPHA_CTRL 0x0160
208#define RK3368_HWC_DST_ALPHA_CTRL 0x0164
209#define RK3368_HWC_FADING_CTRL 0x0168
210#define RK3368_HWC_RESERVED1 0x016c
211#define RK3368_POST_DSP_HACT_INFO 0x0170
212#define RK3368_POST_DSP_VACT_INFO 0x0174
213#define RK3368_POST_SCL_FACTOR_YRGB 0x0178
214#define RK3368_POST_RESERVED 0x017c
215#define RK3368_POST_SCL_CTRL 0x0180
216#define RK3368_POST_DSP_VACT_INFO_F1 0x0184
217#define RK3368_DSP_HTOTAL_HS_END 0x0188
218#define RK3368_DSP_HACT_ST_END 0x018c
219#define RK3368_DSP_VTOTAL_VS_END 0x0190
220#define RK3368_DSP_VACT_ST_END 0x0194
221#define RK3368_DSP_VS_ST_END_F1 0x0198
222#define RK3368_DSP_VACT_ST_END_F1 0x019c
223#define RK3368_PWM_CTRL 0x01a0
224#define RK3368_PWM_PERIOD_HPR 0x01a4
225#define RK3368_PWM_DUTY_LPR 0x01a8
226#define RK3368_PWM_CNT 0x01ac
227#define RK3368_BCSH_COLOR_BAR 0x01b0
228#define RK3368_BCSH_BCS 0x01b4
229#define RK3368_BCSH_H 0x01b8
230#define RK3368_BCSH_CTRL 0x01bc
231#define RK3368_CABC_CTRL0 0x01c0
232#define RK3368_CABC_CTRL1 0x01c4
233#define RK3368_CABC_CTRL2 0x01c8
234#define RK3368_CABC_CTRL3 0x01cc
235#define RK3368_CABC_GAUSS_LINE0_0 0x01d0
236#define RK3368_CABC_GAUSS_LINE0_1 0x01d4
237#define RK3368_CABC_GAUSS_LINE1_0 0x01d8
238#define RK3368_CABC_GAUSS_LINE1_1 0x01dc
239#define RK3368_CABC_GAUSS_LINE2_0 0x01e0
240#define RK3368_CABC_GAUSS_LINE2_1 0x01e4
241#define RK3368_FRC_LOWER01_0 0x01e8
242#define RK3368_FRC_LOWER01_1 0x01ec
243#define RK3368_FRC_LOWER10_0 0x01f0
244#define RK3368_FRC_LOWER10_1 0x01f4
245#define RK3368_FRC_LOWER11_0 0x01f8
246#define RK3368_FRC_LOWER11_1 0x01fc
247#define RK3368_IFBDC_CTRL 0x0200
248#define RK3368_IFBDC_TILES_NUM 0x0204
249#define RK3368_IFBDC_FRAME_RST_CYCLE 0x0208
250#define RK3368_IFBDC_BASE_ADDR 0x020c
251#define RK3368_IFBDC_MB_SIZE 0x0210
252#define RK3368_IFBDC_CMP_INDEX_INIT 0x0214
253#define RK3368_IFBDC_VIR 0x0220
254#define RK3368_IFBDC_DEBUG0 0x0230
255#define RK3368_IFBDC_DEBUG1 0x0234
256#define RK3368_LATENCY_CTRL0 0x0250
257#define RK3368_RD_MAX_LATENCY_NUM0 0x0254
258#define RK3368_RD_LATENCY_THR_NUM0 0x0258
259#define RK3368_RD_LATENCY_SAMP_NUM0 0x025c
260#define RK3368_WIN0_DSP_BG 0x0260
261#define RK3368_WIN1_DSP_BG 0x0264
262#define RK3368_WIN2_DSP_BG 0x0268
263#define RK3368_WIN3_DSP_BG 0x026c
264#define RK3368_SCAN_LINE_NUM 0x0270
265#define RK3368_CABC_DEBUG0 0x0274
266#define RK3368_CABC_DEBUG1 0x0278
267#define RK3368_CABC_DEBUG2 0x027c
268#define RK3368_DBG_REG_000 0x0280
269#define RK3368_DBG_REG_001 0x0284
270#define RK3368_DBG_REG_002 0x0288
271#define RK3368_DBG_REG_003 0x028c
272#define RK3368_DBG_REG_004 0x0290
273#define RK3368_DBG_REG_005 0x0294
274#define RK3368_DBG_REG_006 0x0298
275#define RK3368_DBG_REG_007 0x029c
276#define RK3368_DBG_REG_008 0x02a0
277#define RK3368_DBG_REG_016 0x02c0
278#define RK3368_DBG_REG_017 0x02c4
279#define RK3368_DBG_REG_018 0x02c8
280#define RK3368_DBG_REG_019 0x02cc
281#define RK3368_DBG_REG_020 0x02d0
282#define RK3368_DBG_REG_021 0x02d4
283#define RK3368_DBG_REG_022 0x02d8
284#define RK3368_DBG_REG_023 0x02dc
285#define RK3368_DBG_REG_028 0x02f0
286#define RK3368_MMU_DTE_ADDR 0x0300
287#define RK3368_MMU_STATUS 0x0304
288#define RK3368_MMU_COMMAND 0x0308
289#define RK3368_MMU_PAGE_FAULT_ADDR 0x030c
290#define RK3368_MMU_ZAP_ONE_LINE 0x0310
291#define RK3368_MMU_INT_RAWSTAT 0x0314
292#define RK3368_MMU_INT_CLEAR 0x0318
293#define RK3368_MMU_INT_MASK 0x031c
294#define RK3368_MMU_INT_STATUS 0x0320
295#define RK3368_MMU_AUTO_GATING 0x0324
296#define RK3368_WIN2_LUT_ADDR 0x0400
297#define RK3368_WIN3_LUT_ADDR 0x0800
298#define RK3368_HWC_LUT_ADDR 0x0c00
299#define RK3368_GAMMA_LUT_ADDR 0x1000
300#define RK3368_CABC_GAMMA_LUT_ADDR 0x1800
301#define RK3368_MCU_BYPASS_WPORT 0x2200
302#define RK3368_MCU_BYPASS_RPORT 0x2300
303/* rk3368 register definition end */
304
305#define RK3366_REG_CFG_DONE 0x0000
306#define RK3366_VERSION_INFO 0x0004
307#define RK3366_SYS_CTRL 0x0008
308#define RK3366_SYS_CTRL1 0x000c
309#define RK3366_DSP_CTRL0 0x0010
310#define RK3366_DSP_CTRL1 0x0014
311#define RK3366_DSP_BG 0x0018
312#define RK3366_MCU_CTRL 0x001c
313#define RK3366_WB_CTRL0 0x0020
314#define RK3366_WB_CTRL1 0x0024
315#define RK3366_WB_YRGB_MST 0x0028
316#define RK3366_WB_CBR_MST 0x002c
317#define RK3366_WIN0_CTRL0 0x0030
318#define RK3366_WIN0_CTRL1 0x0034
319#define RK3366_WIN0_COLOR_KEY 0x0038
320#define RK3366_WIN0_VIR 0x003c
321#define RK3366_WIN0_YRGB_MST 0x0040
322#define RK3366_WIN0_CBR_MST 0x0044
323#define RK3366_WIN0_ACT_INFO 0x0048
324#define RK3366_WIN0_DSP_INFO 0x004c
325#define RK3366_WIN0_DSP_ST 0x0050
326#define RK3366_WIN0_SCL_FACTOR_YRGB 0x0054
327#define RK3366_WIN0_SCL_FACTOR_CBR 0x0058
328#define RK3366_WIN0_SCL_OFFSET 0x005c
329#define RK3366_WIN0_SRC_ALPHA_CTRL 0x0060
330#define RK3366_WIN0_DST_ALPHA_CTRL 0x0064
331#define RK3366_WIN0_FADING_CTRL 0x0068
332#define RK3366_WIN0_CTRL2 0x006c
333#define RK3366_WIN1_CTRL0 0x0070
334#define RK3366_WIN1_CTRL1 0x0074
335#define RK3366_WIN1_COLOR_KEY 0x0078
336#define RK3366_WIN1_VIR 0x007c
337#define RK3366_WIN1_YRGB_MST 0x0080
338#define RK3366_WIN1_CBR_MST 0x0084
339#define RK3366_WIN1_ACT_INFO 0x0088
340#define RK3366_WIN1_DSP_INFO 0x008c
341#define RK3366_WIN1_DSP_ST 0x0090
342#define RK3366_WIN1_SCL_FACTOR_YRGB 0x0094
343#define RK3366_WIN1_SCL_FACTOR_CBR 0x0098
344#define RK3366_WIN1_SCL_OFFSET 0x009c
345#define RK3366_WIN1_SRC_ALPHA_CTRL 0x00a0
346#define RK3366_WIN1_DST_ALPHA_CTRL 0x00a4
347#define RK3366_WIN1_FADING_CTRL 0x00a8
348#define RK3366_WIN1_CTRL2 0x00ac
349#define RK3366_WIN2_CTRL0 0x00b0
350#define RK3366_WIN2_CTRL1 0x00b4
351#define RK3366_WIN2_VIR0_1 0x00b8
352#define RK3366_WIN2_VIR2_3 0x00bc
353#define RK3366_WIN2_MST0 0x00c0
354#define RK3366_WIN2_DSP_INFO0 0x00c4
355#define RK3366_WIN2_DSP_ST0 0x00c8
356#define RK3366_WIN2_COLOR_KEY 0x00cc
357#define RK3366_WIN2_MST1 0x00d0
358#define RK3366_WIN2_DSP_INFO1 0x00d4
359#define RK3366_WIN2_DSP_ST1 0x00d8
360#define RK3366_WIN2_SRC_ALPHA_CTRL 0x00dc
361#define RK3366_WIN2_MST2 0x00e0
362#define RK3366_WIN2_DSP_INFO2 0x00e4
363#define RK3366_WIN2_DSP_ST2 0x00e8
364#define RK3366_WIN2_DST_ALPHA_CTRL 0x00ec
365#define RK3366_WIN2_MST3 0x00f0
366#define RK3366_WIN2_DSP_INFO3 0x00f4
367#define RK3366_WIN2_DSP_ST3 0x00f8
368#define RK3366_WIN2_FADING_CTRL 0x00fc
369#define RK3366_WIN3_CTRL0 0x0100
370#define RK3366_WIN3_CTRL1 0x0104
371#define RK3366_WIN3_VIR0_1 0x0108
372#define RK3366_WIN3_VIR2_3 0x010c
373#define RK3366_WIN3_MST0 0x0110
374#define RK3366_WIN3_DSP_INFO0 0x0114
375#define RK3366_WIN3_DSP_ST0 0x0118
376#define RK3366_WIN3_COLOR_KEY 0x011c
377#define RK3366_WIN3_MST1 0x0120
378#define RK3366_WIN3_DSP_INFO1 0x0124
379#define RK3366_WIN3_DSP_ST1 0x0128
380#define RK3366_WIN3_SRC_ALPHA_CTRL 0x012c
381#define RK3366_WIN3_MST2 0x0130
382#define RK3366_WIN3_DSP_INFO2 0x0134
383#define RK3366_WIN3_DSP_ST2 0x0138
384#define RK3366_WIN3_DST_ALPHA_CTRL 0x013c
385#define RK3366_WIN3_MST3 0x0140
386#define RK3366_WIN3_DSP_INFO3 0x0144
387#define RK3366_WIN3_DSP_ST3 0x0148
388#define RK3366_WIN3_FADING_CTRL 0x014c
389#define RK3366_HWC_CTRL0 0x0150
390#define RK3366_HWC_CTRL1 0x0154
391#define RK3366_HWC_MST 0x0158
392#define RK3366_HWC_DSP_ST 0x015c
393#define RK3366_HWC_SRC_ALPHA_CTRL 0x0160
394#define RK3366_HWC_DST_ALPHA_CTRL 0x0164
395#define RK3366_HWC_FADING_CTRL 0x0168
396#define RK3366_HWC_RESERVED1 0x016c
397#define RK3366_POST_DSP_HACT_INFO 0x0170
398#define RK3366_POST_DSP_VACT_INFO 0x0174
399#define RK3366_POST_SCL_FACTOR_YRGB 0x0178
400#define RK3366_POST_RESERVED 0x017c
401#define RK3366_POST_SCL_CTRL 0x0180
402#define RK3366_POST_DSP_VACT_INFO_F1 0x0184
403#define RK3366_DSP_HTOTAL_HS_END 0x0188
404#define RK3366_DSP_HACT_ST_END 0x018c
405#define RK3366_DSP_VTOTAL_VS_END 0x0190
406#define RK3366_DSP_VACT_ST_END 0x0194
407#define RK3366_DSP_VS_ST_END_F1 0x0198
408#define RK3366_DSP_VACT_ST_END_F1 0x019c
409#define RK3366_PWM_CTRL 0x01a0
410#define RK3366_PWM_PERIOD_HPR 0x01a4
411#define RK3366_PWM_DUTY_LPR 0x01a8
412#define RK3366_PWM_CNT 0x01ac
413#define RK3366_BCSH_COLOR_BAR 0x01b0
414#define RK3366_BCSH_BCS 0x01b4
415#define RK3366_BCSH_H 0x01b8
416#define RK3366_BCSH_CTRL 0x01bc
417#define RK3366_CABC_CTRL0 0x01c0
418#define RK3366_CABC_CTRL1 0x01c4
419#define RK3366_CABC_CTRL2 0x01c8
420#define RK3366_CABC_CTRL3 0x01cc
421#define RK3366_CABC_GAUSS_LINE0_0 0x01d0
422#define RK3366_CABC_GAUSS_LINE0_1 0x01d4
423#define RK3366_CABC_GAUSS_LINE1_0 0x01d8
424#define RK3366_CABC_GAUSS_LINE1_1 0x01dc
425#define RK3366_CABC_GAUSS_LINE2_0 0x01e0
426#define RK3366_CABC_GAUSS_LINE2_1 0x01e4
427#define RK3366_FRC_LOWER01_0 0x01e8
428#define RK3366_FRC_LOWER01_1 0x01ec
429#define RK3366_FRC_LOWER10_0 0x01f0
430#define RK3366_FRC_LOWER10_1 0x01f4
431#define RK3366_FRC_LOWER11_0 0x01f8
432#define RK3366_FRC_LOWER11_1 0x01fc
433#define RK3366_INTR_EN0 0x0280
434#define RK3366_INTR_CLEAR0 0x0284
435#define RK3366_INTR_STATUS0 0x0288
436#define RK3366_INTR_RAW_STATUS0 0x028c
437#define RK3366_INTR_EN1 0x0290
438#define RK3366_INTR_CLEAR1 0x0294
439#define RK3366_INTR_STATUS1 0x0298
440#define RK3366_INTR_RAW_STATUS1 0x029c
441#define RK3366_LINE_FLAG 0x02a0
442#define RK3366_VOP_STATUS 0x02a4
443#define RK3366_BLANKING_VALUE 0x02a8
444#define RK3366_WIN0_DSP_BG 0x02b0
445#define RK3366_WIN1_DSP_BG 0x02b4
446#define RK3366_WIN2_DSP_BG 0x02b8
447#define RK3366_WIN3_DSP_BG 0x02bc
448#define RK3366_WIN2_LUT_ADDR 0x0400
449#define RK3366_WIN3_LUT_ADDR 0x0800
450#define RK3366_HWC_LUT_ADDR 0x0c00
451#define RK3366_GAMMA0_LUT_ADDR 0x1000
452#define RK3366_GAMMA1_LUT_ADDR 0x1400
453#define RK3366_CABC_GAMMA_LUT_ADDR 0x1800
454#define RK3366_MCU_BYPASS_WPORT 0x2200
455#define RK3366_MCU_BYPASS_RPORT 0x2300
456#define RK3366_MMU_DTE_ADDR 0x2400
457#define RK3366_MMU_STATUS 0x2404
458#define RK3366_MMU_COMMAND 0x2408
459#define RK3366_MMU_PAGE_FAULT_ADDR 0x240c
460#define RK3366_MMU_ZAP_ONE_LINE 0x2410
461#define RK3366_MMU_INT_RAWSTAT 0x2414
462#define RK3366_MMU_INT_CLEAR 0x2418
463#define RK3366_MMU_INT_MASK 0x241c
464#define RK3366_MMU_INT_STATUS 0x2420
465#define RK3366_MMU_AUTO_GATING 0x2424
466
467/* rk3399 register definition */
468#define RK3399_REG_CFG_DONE 0x0000
469#define RK3399_VERSION_INFO 0x0004
470#define RK3399_SYS_CTRL 0x0008
471#define RK3399_SYS_CTRL1 0x000c
472#define RK3399_DSP_CTRL0 0x0010
473#define RK3399_DSP_CTRL1 0x0014
474#define RK3399_DSP_BG 0x0018
475#define RK3399_MCU_CTRL 0x001c
476#define RK3399_WB_CTRL0 0x0020
477#define RK3399_WB_CTRL1 0x0024
478#define RK3399_WB_YRGB_MST 0x0028
479#define RK3399_WB_CBR_MST 0x002c
480#define RK3399_WIN0_CTRL0 0x0030
481#define RK3399_WIN0_CTRL1 0x0034
482#define RK3399_WIN0_COLOR_KEY 0x0038
483#define RK3399_WIN0_VIR 0x003c
484#define RK3399_WIN0_YRGB_MST 0x0040
485#define RK3399_WIN0_CBR_MST 0x0044
486#define RK3399_WIN0_ACT_INFO 0x0048
487#define RK3399_WIN0_DSP_INFO 0x004c
488#define RK3399_WIN0_DSP_ST 0x0050
489#define RK3399_WIN0_SCL_FACTOR_YRGB 0x0054
490#define RK3399_WIN0_SCL_FACTOR_CBR 0x0058
491#define RK3399_WIN0_SCL_OFFSET 0x005c
492#define RK3399_WIN0_SRC_ALPHA_CTRL 0x0060
493#define RK3399_WIN0_DST_ALPHA_CTRL 0x0064
494#define RK3399_WIN0_FADING_CTRL 0x0068
495#define RK3399_WIN0_CTRL2 0x006c
496#define RK3399_WIN1_CTRL0 0x0070
497#define RK3399_WIN1_CTRL1 0x0074
498#define RK3399_WIN1_COLOR_KEY 0x0078
499#define RK3399_WIN1_VIR 0x007c
500#define RK3399_WIN1_YRGB_MST 0x0080
501#define RK3399_WIN1_CBR_MST 0x0084
502#define RK3399_WIN1_ACT_INFO 0x0088
503#define RK3399_WIN1_DSP_INFO 0x008c
504#define RK3399_WIN1_DSP_ST 0x0090
505#define RK3399_WIN1_SCL_FACTOR_YRGB 0x0094
506#define RK3399_WIN1_SCL_FACTOR_CBR 0x0098
507#define RK3399_WIN1_SCL_OFFSET 0x009c
508#define RK3399_WIN1_SRC_ALPHA_CTRL 0x00a0
509#define RK3399_WIN1_DST_ALPHA_CTRL 0x00a4
510#define RK3399_WIN1_FADING_CTRL 0x00a8
511#define RK3399_WIN1_CTRL2 0x00ac
512#define RK3399_WIN2_CTRL0 0x00b0
513#define RK3399_WIN2_CTRL1 0x00b4
514#define RK3399_WIN2_VIR0_1 0x00b8
515#define RK3399_WIN2_VIR2_3 0x00bc
516#define RK3399_WIN2_MST0 0x00c0
517#define RK3399_WIN2_DSP_INFO0 0x00c4
518#define RK3399_WIN2_DSP_ST0 0x00c8
519#define RK3399_WIN2_COLOR_KEY 0x00cc
520#define RK3399_WIN2_MST1 0x00d0
521#define RK3399_WIN2_DSP_INFO1 0x00d4
522#define RK3399_WIN2_DSP_ST1 0x00d8
523#define RK3399_WIN2_SRC_ALPHA_CTRL 0x00dc
524#define RK3399_WIN2_MST2 0x00e0
525#define RK3399_WIN2_DSP_INFO2 0x00e4
526#define RK3399_WIN2_DSP_ST2 0x00e8
527#define RK3399_WIN2_DST_ALPHA_CTRL 0x00ec
528#define RK3399_WIN2_MST3 0x00f0
529#define RK3399_WIN2_DSP_INFO3 0x00f4
530#define RK3399_WIN2_DSP_ST3 0x00f8
531#define RK3399_WIN2_FADING_CTRL 0x00fc
532#define RK3399_WIN3_CTRL0 0x0100
533#define RK3399_WIN3_CTRL1 0x0104
534#define RK3399_WIN3_VIR0_1 0x0108
535#define RK3399_WIN3_VIR2_3 0x010c
536#define RK3399_WIN3_MST0 0x0110
537#define RK3399_WIN3_DSP_INFO0 0x0114
538#define RK3399_WIN3_DSP_ST0 0x0118
539#define RK3399_WIN3_COLOR_KEY 0x011c
540#define RK3399_WIN3_MST1 0x0120
541#define RK3399_WIN3_DSP_INFO1 0x0124
542#define RK3399_WIN3_DSP_ST1 0x0128
543#define RK3399_WIN3_SRC_ALPHA_CTRL 0x012c
544#define RK3399_WIN3_MST2 0x0130
545#define RK3399_WIN3_DSP_INFO2 0x0134
546#define RK3399_WIN3_DSP_ST2 0x0138
547#define RK3399_WIN3_DST_ALPHA_CTRL 0x013c
548#define RK3399_WIN3_MST3 0x0140
549#define RK3399_WIN3_DSP_INFO3 0x0144
550#define RK3399_WIN3_DSP_ST3 0x0148
551#define RK3399_WIN3_FADING_CTRL 0x014c
552#define RK3399_HWC_CTRL0 0x0150
553#define RK3399_HWC_CTRL1 0x0154
554#define RK3399_HWC_MST 0x0158
555#define RK3399_HWC_DSP_ST 0x015c
556#define RK3399_HWC_SRC_ALPHA_CTRL 0x0160
557#define RK3399_HWC_DST_ALPHA_CTRL 0x0164
558#define RK3399_HWC_FADING_CTRL 0x0168
559#define RK3399_HWC_RESERVED1 0x016c
560#define RK3399_POST_DSP_HACT_INFO 0x0170
561#define RK3399_POST_DSP_VACT_INFO 0x0174
562#define RK3399_POST_SCL_FACTOR_YRGB 0x0178
563#define RK3399_POST_RESERVED 0x017c
564#define RK3399_POST_SCL_CTRL 0x0180
565#define RK3399_POST_DSP_VACT_INFO_F1 0x0184
566#define RK3399_DSP_HTOTAL_HS_END 0x0188
567#define RK3399_DSP_HACT_ST_END 0x018c
568#define RK3399_DSP_VTOTAL_VS_END 0x0190
569#define RK3399_DSP_VACT_ST_END 0x0194
570#define RK3399_DSP_VS_ST_END_F1 0x0198
571#define RK3399_DSP_VACT_ST_END_F1 0x019c
572#define RK3399_PWM_CTRL 0x01a0
573#define RK3399_PWM_PERIOD_HPR 0x01a4
574#define RK3399_PWM_DUTY_LPR 0x01a8
575#define RK3399_PWM_CNT 0x01ac
576#define RK3399_BCSH_COLOR_BAR 0x01b0
577#define RK3399_BCSH_BCS 0x01b4
578#define RK3399_BCSH_H 0x01b8
579#define RK3399_BCSH_CTRL 0x01bc
580#define RK3399_CABC_CTRL0 0x01c0
581#define RK3399_CABC_CTRL1 0x01c4
582#define RK3399_CABC_CTRL2 0x01c8
583#define RK3399_CABC_CTRL3 0x01cc
584#define RK3399_CABC_GAUSS_LINE0_0 0x01d0
585#define RK3399_CABC_GAUSS_LINE0_1 0x01d4
586#define RK3399_CABC_GAUSS_LINE1_0 0x01d8
587#define RK3399_CABC_GAUSS_LINE1_1 0x01dc
588#define RK3399_CABC_GAUSS_LINE2_0 0x01e0
589#define RK3399_CABC_GAUSS_LINE2_1 0x01e4
590#define RK3399_FRC_LOWER01_0 0x01e8
591#define RK3399_FRC_LOWER01_1 0x01ec
592#define RK3399_FRC_LOWER10_0 0x01f0
593#define RK3399_FRC_LOWER10_1 0x01f4
594#define RK3399_FRC_LOWER11_0 0x01f8
595#define RK3399_FRC_LOWER11_1 0x01fc
596#define RK3399_AFBCD0_CTRL 0x0200
597#define RK3399_AFBCD0_HDR_PTR 0x0204
598#define RK3399_AFBCD0_PIC_SIZE 0x0208
599#define RK3399_AFBCD0_STATUS 0x020c
600#define RK3399_AFBCD1_CTRL 0x0220
601#define RK3399_AFBCD1_HDR_PTR 0x0224
602#define RK3399_AFBCD1_PIC_SIZE 0x0228
603#define RK3399_AFBCD1_STATUS 0x022c
604#define RK3399_AFBCD2_CTRL 0x0240
605#define RK3399_AFBCD2_HDR_PTR 0x0244
606#define RK3399_AFBCD2_PIC_SIZE 0x0248
607#define RK3399_AFBCD2_STATUS 0x024c
608#define RK3399_AFBCD3_CTRL 0x0260
609#define RK3399_AFBCD3_HDR_PTR 0x0264
610#define RK3399_AFBCD3_PIC_SIZE 0x0268
611#define RK3399_AFBCD3_STATUS 0x026c
612#define RK3399_INTR_EN0 0x0280
613#define RK3399_INTR_CLEAR0 0x0284
614#define RK3399_INTR_STATUS0 0x0288
615#define RK3399_INTR_RAW_STATUS0 0x028c
616#define RK3399_INTR_EN1 0x0290
617#define RK3399_INTR_CLEAR1 0x0294
618#define RK3399_INTR_STATUS1 0x0298
619#define RK3399_INTR_RAW_STATUS1 0x029c
620#define RK3399_LINE_FLAG 0x02a0
621#define RK3399_VOP_STATUS 0x02a4
622#define RK3399_BLANKING_VALUE 0x02a8
623#define RK3399_MCU_BYPASS_PORT 0x02ac
624#define RK3399_WIN0_DSP_BG 0x02b0
625#define RK3399_WIN1_DSP_BG 0x02b4
626#define RK3399_WIN2_DSP_BG 0x02b8
627#define RK3399_WIN3_DSP_BG 0x02bc
628#define RK3399_YUV2YUV_WIN 0x02c0
629#define RK3399_YUV2YUV_POST 0x02c4
630#define RK3399_AUTO_GATING_EN 0x02cc
631#define RK3399_WIN0_CSC_COE 0x03a0
632#define RK3399_WIN1_CSC_COE 0x03c0
633#define RK3399_WIN2_CSC_COE 0x03e0
634#define RK3399_WIN3_CSC_COE 0x0400
635#define RK3399_HWC_CSC_COE 0x0420
636#define RK3399_BCSH_R2Y_CSC_COE 0x0440
637#define RK3399_BCSH_Y2R_CSC_COE 0x0460
638#define RK3399_POST_YUV2YUV_Y2R_COE 0x0480
639#define RK3399_POST_YUV2YUV_3X3_COE 0x04a0
640#define RK3399_POST_YUV2YUV_R2Y_COE 0x04c0
641#define RK3399_WIN0_YUV2YUV_Y2R 0x04e0
642#define RK3399_WIN0_YUV2YUV_3X3 0x0500
643#define RK3399_WIN0_YUV2YUV_R2Y 0x0520
644#define RK3399_WIN1_YUV2YUV_Y2R 0x0540
645#define RK3399_WIN1_YUV2YUV_3X3 0x0560
646#define RK3399_WIN1_YUV2YUV_R2Y 0x0580
647#define RK3399_WIN2_YUV2YUV_Y2R 0x05a0
648#define RK3399_WIN2_YUV2YUV_3X3 0x05c0
649#define RK3399_WIN2_YUV2YUV_R2Y 0x05e0
650#define RK3399_WIN3_YUV2YUV_Y2R 0x0600
651#define RK3399_WIN3_YUV2YUV_3X3 0x0620
652#define RK3399_WIN3_YUV2YUV_R2Y 0x0640
653#define RK3399_WIN2_LUT_ADDR 0x1000
654#define RK3399_WIN3_LUT_ADDR 0x1400
655#define RK3399_HWC_LUT_ADDR 0x1800
656#define RK3399_CABC_GAMMA_LUT_ADDR 0x1c00
657#define RK3399_GAMMA_LUT_ADDR 0x2000
658/* rk3399 register definition end */
659
660/* rk3328 register definition end */
661#define RK3328_REG_CFG_DONE 0x00000000
662#define RK3328_VERSION_INFO 0x00000004
663#define RK3328_SYS_CTRL 0x00000008
664#define RK3328_SYS_CTRL1 0x0000000c
665#define RK3328_DSP_CTRL0 0x00000010
666#define RK3328_DSP_CTRL1 0x00000014
667#define RK3328_DSP_BG 0x00000018
668#define RK3328_AUTO_GATING_EN 0x0000003c
669#define RK3328_LINE_FLAG 0x00000040
670#define RK3328_VOP_STATUS 0x00000044
671#define RK3328_BLANKING_VALUE 0x00000048
672#define RK3328_WIN0_DSP_BG 0x00000050
673#define RK3328_WIN1_DSP_BG 0x00000054
674#define RK3328_DBG_PERF_LATENCY_CTRL0 0x000000c0
675#define RK3328_DBG_PERF_RD_MAX_LATENCY_NUM0 0x000000c4
676#define RK3328_DBG_PERF_RD_LATENCY_THR_NUM0 0x000000c8
677#define RK3328_DBG_PERF_RD_LATENCY_SAMP_NUM0 0x000000cc
678#define RK3328_INTR_EN0 0x000000e0
679#define RK3328_INTR_CLEAR0 0x000000e4
680#define RK3328_INTR_STATUS0 0x000000e8
681#define RK3328_INTR_RAW_STATUS0 0x000000ec
682#define RK3328_INTR_EN1 0x000000f0
683#define RK3328_INTR_CLEAR1 0x000000f4
684#define RK3328_INTR_STATUS1 0x000000f8
685#define RK3328_INTR_RAW_STATUS1 0x000000fc
686#define RK3328_WIN0_CTRL0 0x00000100
687#define RK3328_WIN0_CTRL1 0x00000104
688#define RK3328_WIN0_COLOR_KEY 0x00000108
689#define RK3328_WIN0_VIR 0x0000010c
690#define RK3328_WIN0_YRGB_MST 0x00000110
691#define RK3328_WIN0_CBR_MST 0x00000114
692#define RK3328_WIN0_ACT_INFO 0x00000118
693#define RK3328_WIN0_DSP_INFO 0x0000011c
694#define RK3328_WIN0_DSP_ST 0x00000120
695#define RK3328_WIN0_SCL_FACTOR_YRGB 0x00000124
696#define RK3328_WIN0_SCL_FACTOR_CBR 0x00000128
697#define RK3328_WIN0_SCL_OFFSET 0x0000012c
698#define RK3328_WIN0_SRC_ALPHA_CTRL 0x00000130
699#define RK3328_WIN0_DST_ALPHA_CTRL 0x00000134
700#define RK3328_WIN0_FADING_CTRL 0x00000138
701#define RK3328_WIN0_CTRL2 0x0000013c
702#define RK3328_DBG_WIN0_REG0 0x000001f0
703#define RK3328_DBG_WIN0_REG1 0x000001f4
704#define RK3328_DBG_WIN0_REG2 0x000001f8
705#define RK3328_DBG_WIN0_RESERVED 0x000001fc
706#define RK3328_WIN1_CTRL0 0x00000200
707#define RK3328_WIN1_CTRL1 0x00000204
708#define RK3328_WIN1_COLOR_KEY 0x00000208
709#define RK3328_WIN1_VIR 0x0000020c
710#define RK3328_WIN1_YRGB_MST 0x00000210
711#define RK3328_WIN1_CBR_MST 0x00000214
712#define RK3328_WIN1_ACT_INFO 0x00000218
713#define RK3328_WIN1_DSP_INFO 0x0000021c
714#define RK3328_WIN1_DSP_ST 0x00000220
715#define RK3328_WIN1_SCL_FACTOR_YRGB 0x00000224
716#define RK3328_WIN1_SCL_FACTOR_CBR 0x00000228
717#define RK3328_WIN1_SCL_OFFSET 0x0000022c
718#define RK3328_WIN1_SRC_ALPHA_CTRL 0x00000230
719#define RK3328_WIN1_DST_ALPHA_CTRL 0x00000234
720#define RK3328_WIN1_FADING_CTRL 0x00000238
721#define RK3328_WIN1_CTRL2 0x0000023c
722#define RK3328_DBG_WIN1_REG0 0x000002f0
723#define RK3328_DBG_WIN1_REG1 0x000002f4
724#define RK3328_DBG_WIN1_REG2 0x000002f8
725#define RK3328_DBG_WIN1_RESERVED 0x000002fc
726#define RK3328_WIN2_CTRL0 0x00000300
727#define RK3328_WIN2_CTRL1 0x00000304
728#define RK3328_WIN2_COLOR_KEY 0x00000308
729#define RK3328_WIN2_VIR 0x0000030c
730#define RK3328_WIN2_YRGB_MST 0x00000310
731#define RK3328_WIN2_CBR_MST 0x00000314
732#define RK3328_WIN2_ACT_INFO 0x00000318
733#define RK3328_WIN2_DSP_INFO 0x0000031c
734#define RK3328_WIN2_DSP_ST 0x00000320
735#define RK3328_WIN2_SCL_FACTOR_YRGB 0x00000324
736#define RK3328_WIN2_SCL_FACTOR_CBR 0x00000328
737#define RK3328_WIN2_SCL_OFFSET 0x0000032c
738#define RK3328_WIN2_SRC_ALPHA_CTRL 0x00000330
739#define RK3328_WIN2_DST_ALPHA_CTRL 0x00000334
740#define RK3328_WIN2_FADING_CTRL 0x00000338
741#define RK3328_WIN2_CTRL2 0x0000033c
742#define RK3328_DBG_WIN2_REG0 0x000003f0
743#define RK3328_DBG_WIN2_REG1 0x000003f4
744#define RK3328_DBG_WIN2_REG2 0x000003f8
745#define RK3328_DBG_WIN2_RESERVED 0x000003fc
746#define RK3328_WIN3_CTRL0 0x00000400
747#define RK3328_WIN3_CTRL1 0x00000404
748#define RK3328_WIN3_COLOR_KEY 0x00000408
749#define RK3328_WIN3_VIR 0x0000040c
750#define RK3328_WIN3_YRGB_MST 0x00000410
751#define RK3328_WIN3_CBR_MST 0x00000414
752#define RK3328_WIN3_ACT_INFO 0x00000418
753#define RK3328_WIN3_DSP_INFO 0x0000041c
754#define RK3328_WIN3_DSP_ST 0x00000420
755#define RK3328_WIN3_SCL_FACTOR_YRGB 0x00000424
756#define RK3328_WIN3_SCL_FACTOR_CBR 0x00000428
757#define RK3328_WIN3_SCL_OFFSET 0x0000042c
758#define RK3328_WIN3_SRC_ALPHA_CTRL 0x00000430
759#define RK3328_WIN3_DST_ALPHA_CTRL 0x00000434
760#define RK3328_WIN3_FADING_CTRL 0x00000438
761#define RK3328_WIN3_CTRL2 0x0000043c
762#define RK3328_DBG_WIN3_REG0 0x000004f0
763#define RK3328_DBG_WIN3_REG1 0x000004f4
764#define RK3328_DBG_WIN3_REG2 0x000004f8
765#define RK3328_DBG_WIN3_RESERVED 0x000004fc
766
767#define RK3328_HWC_CTRL0 0x00000500
768#define RK3328_HWC_CTRL1 0x00000504
769#define RK3328_HWC_MST 0x00000508
770#define RK3328_HWC_DSP_ST 0x0000050c
771#define RK3328_HWC_SRC_ALPHA_CTRL 0x00000510
772#define RK3328_HWC_DST_ALPHA_CTRL 0x00000514
773#define RK3328_HWC_FADING_CTRL 0x00000518
774#define RK3328_HWC_RESERVED1 0x0000051c
775#define RK3328_POST_DSP_HACT_INFO 0x00000600
776#define RK3328_POST_DSP_VACT_INFO 0x00000604
777#define RK3328_POST_SCL_FACTOR_YRGB 0x00000608
778#define RK3328_POST_RESERVED 0x0000060c
779#define RK3328_POST_SCL_CTRL 0x00000610
780#define RK3328_POST_DSP_VACT_INFO_F1 0x00000614
781#define RK3328_DSP_HTOTAL_HS_END 0x00000618
782#define RK3328_DSP_HACT_ST_END 0x0000061c
783#define RK3328_DSP_VTOTAL_VS_END 0x00000620
784#define RK3328_DSP_VACT_ST_END 0x00000624
785#define RK3328_DSP_VS_ST_END_F1 0x00000628
786#define RK3328_DSP_VACT_ST_END_F1 0x0000062c
787#define RK3328_BCSH_COLOR_BAR 0x00000640
788#define RK3328_BCSH_BCS 0x00000644
789#define RK3328_BCSH_H 0x00000648
790#define RK3328_BCSH_CTRL 0x0000064c
791#define RK3328_FRC_LOWER01_0 0x00000678
792#define RK3328_FRC_LOWER01_1 0x0000067c
793#define RK3328_FRC_LOWER10_0 0x00000680
794#define RK3328_FRC_LOWER10_1 0x00000684
795#define RK3328_FRC_LOWER11_0 0x00000688
796#define RK3328_FRC_LOWER11_1 0x0000068c
797#define RK3328_DBG_POST_REG0 0x000006e8
798#define RK3328_DBG_POST_RESERVED 0x000006ec
799#define RK3328_DBG_DATAO 0x000006f0
800#define RK3328_DBG_DATAO_2 0x000006f4
801
802/* sdr to hdr */
803#define RK3328_SDR2HDR_CTRL 0x00000700
804#define RK3328_EOTF_OETF_Y0 0x00000704
805#define RK3328_RESERVED0001 0x00000708
806#define RK3328_RESERVED0002 0x0000070c
807#define RK3328_EOTF_OETF_Y1 0x00000710
808#define RK3328_EOTF_OETF_Y64 0x0000080c
809#define RK3328_OETF_DX_DXPOW1 0x00000810
810#define RK3328_OETF_DX_DXPOW64 0x0000090c
811#define RK3328_OETF_XN1 0x00000910
812#define RK3328_OETF_XN63 0x00000a08
813
814/* hdr to sdr */
815#define RK3328_HDR2SDR_CTRL 0x00000a10
816#define RK3328_HDR2SDR_SRC_RANGE 0x00000a14
817#define RK3328_HDR2SDR_NORMFACEETF 0x00000a18
818#define RK3328_RESERVED0003 0x00000a1c
819#define RK3328_HDR2SDR_DST_RANGE 0x00000a20
820#define RK3328_HDR2SDR_NORMFACCGAMMA 0x00000a24
821#define RK3328_EETF_OETF_Y0 0x00000a28
822#define RK3328_SAT_Y0 0x00000a2c
823#define RK3328_EETF_OETF_Y1 0x00000a30
824#define RK3328_SAT_Y1 0x00000ab0
825#define RK3328_SAT_Y8 0x00000acc
826
827#define RK3328_HWC_LUT_ADDR 0x00000c00
828
829/* rk3036 register definition */
830#define RK3036_SYS_CTRL 0x00
831#define RK3036_DSP_CTRL0 0x04
832#define RK3036_DSP_CTRL1 0x08
833#define RK3036_INT_STATUS 0x10
834#define RK3036_ALPHA_CTRL 0x14
835#define RK3036_WIN0_COLOR_KEY 0x18
836#define RK3036_WIN1_COLOR_KEY 0x1c
837#define RK3036_WIN0_YRGB_MST 0x20
838#define RK3036_WIN0_CBR_MST 0x24
839#define RK3036_WIN1_VIR 0x28
840#define RK3036_AXI_BUS_CTRL 0x2c
841#define RK3036_WIN0_VIR 0x30
842#define RK3036_WIN0_ACT_INFO 0x34
843#define RK3036_WIN0_DSP_INFO 0x38
844#define RK3036_WIN0_DSP_ST 0x3c
845#define RK3036_WIN0_SCL_FACTOR_YRGB 0x40
846#define RK3036_WIN0_SCL_FACTOR_CBR 0x44
847#define RK3036_WIN0_SCL_OFFSET 0x48
848#define RK3036_HWC_MST 0x58
849#define RK3036_HWC_DSP_ST 0x5c
850#define RK3036_DSP_HTOTAL_HS_END 0x6c
851#define RK3036_DSP_HACT_ST_END 0x70
852#define RK3036_DSP_VTOTAL_VS_END 0x74
853#define RK3036_DSP_VACT_ST_END 0x78
854#define RK3036_DSP_VS_ST_END_F1 0x7c
855#define RK3036_DSP_VACT_ST_END_F1 0x80
856#define RK3036_GATHER_TRANSFER 0x84
857#define RK3036_VERSION_INFO 0x94
858#define RK3036_REG_CFG_DONE 0x90
859#define RK3036_WIN1_MST 0xa0
860#define RK3036_WIN1_ACT_INFO 0xb4
861#define RK3036_WIN1_DSP_INFO 0xb8
862#define RK3036_WIN1_DSP_ST 0xbc
863#define RK3036_WIN1_SCL_FACTOR_YRGB 0xc0
864#define RK3036_WIN1_SCL_OFFSET 0xc8
865#define RK3036_BCSH_CTRL 0xd0
866#define RK3036_BCSH_COLOR_BAR 0xd4
867#define RK3036_BCSH_BCS 0xd8
868#define RK3036_BCSH_H 0xdc
869#define RK3036_WIN1_LUT_ADDR 0x400
870#define RK3036_HWC_LUT_ADDR 0x800
871/* rk3036 register definition end */
872
873/* rk3126 register definition */
874#define RK3126_WIN1_MST 0x4c
875#define RK3126_WIN1_DSP_INFO 0x50
876#define RK3126_WIN1_DSP_ST 0x54
877/* rk3126 register definition end */
878
879/* px30 register definition */
880#define PX30_REG_CFG_DONE 0x00000
881#define PX30_VERSION 0x00004
882#define PX30_DSP_BG 0x00008
883#define PX30_MCU_CTRL 0x0000c
884#define PX30_SYS_CTRL0 0x00010
885#define PX30_SYS_CTRL1 0x00014
886#define PX30_SYS_CTRL2 0x00018
887#define PX30_DSP_CTRL0 0x00020
888#define PX30_DSP_CTRL2 0x00028
889#define PX30_VOP_STATUS 0x0002c
890#define PX30_LINE_FLAG 0x00030
891#define PX30_INTR_EN 0x00034
892#define PX30_INTR_CLEAR 0x00038
893#define PX30_INTR_STATUS 0x0003c
894#define PX30_WIN0_CTRL0 0x00050
895#define PX30_WIN0_CTRL1 0x00054
896#define PX30_WIN0_COLOR_KEY 0x00058
897#define PX30_WIN0_VIR 0x0005c
898#define PX30_WIN0_YRGB_MST0 0x00060
899#define PX30_WIN0_CBR_MST0 0x00064
900#define PX30_WIN0_ACT_INFO 0x00068
901#define PX30_WIN0_DSP_INFO 0x0006c
902#define PX30_WIN0_DSP_ST 0x00070
903#define PX30_WIN0_SCL_FACTOR_YRGB 0x00074
904#define PX30_WIN0_SCL_FACTOR_CBR 0x00078
905#define PX30_WIN0_SCL_OFFSET 0x0007c
906#define PX30_WIN0_ALPHA_CTRL 0x00080
907#define PX30_WIN1_CTRL0 0x00090
908#define PX30_WIN1_CTRL1 0x00094
909#define PX30_WIN1_VIR 0x00098
910#define PX30_WIN1_MST 0x000a0
911#define PX30_WIN1_DSP_INFO 0x000a4
912#define PX30_WIN1_DSP_ST 0x000a8
913#define PX30_WIN1_COLOR_KEY 0x000ac
914#define PX30_WIN1_ALPHA_CTRL 0x000bc
915#define PX30_HWC_CTRL0 0x000e0
916#define PX30_HWC_CTRL1 0x000e4
917#define PX30_HWC_MST 0x000e8
918#define PX30_HWC_DSP_ST 0x000ec
919#define PX30_HWC_ALPHA_CTRL 0x000f0
920#define PX30_DSP_HTOTAL_HS_END 0x00100
921#define PX30_DSP_HACT_ST_END 0x00104
922#define PX30_DSP_VTOTAL_VS_END 0x00108
923#define PX30_DSP_VACT_ST_END 0x0010c
924#define PX30_DSP_VS_ST_END_F1 0x00110
925#define PX30_DSP_VACT_ST_END_F1 0x00114
926#define PX30_BCSH_CTRL 0x00160
927#define PX30_BCSH_COL_BAR 0x00164
928#define PX30_BCSH_BCS 0x00168
929#define PX30_BCSH_H 0x0016c
930#define PX30_FRC_LOWER01_0 0x00170
931#define PX30_FRC_LOWER01_1 0x00174
932#define PX30_FRC_LOWER10_0 0x00178
933#define PX30_FRC_LOWER10_1 0x0017c
934#define PX30_FRC_LOWER11_0 0x00180
935#define PX30_FRC_LOWER11_1 0x00184
936#define PX30_MCU_RW_BYPASS_PORT 0x0018c
937#define PX30_WIN2_CTRL0 0x00190
938#define PX30_WIN2_CTRL1 0x00194
939#define PX30_WIN2_VIR0_1 0x00198
940#define PX30_WIN2_VIR2_3 0x0019c
941#define PX30_WIN2_MST0 0x001a0
942#define PX30_WIN2_DSP_INFO0 0x001a4
943#define PX30_WIN2_DSP_ST0 0x001a8
944#define PX30_WIN2_COLOR_KEY 0x001ac
945#define PX30_WIN2_ALPHA_CTRL 0x001bc
946#define PX30_BLANKING_VALUE 0x001f4
947#define PX30_FLAG_REG_FRM_VALID 0x001f8
948#define PX30_FLAG_REG 0x001fc
949#define PX30_HWC_LUT_ADDR 0x00600
950#define PX30_GAMMA_LUT_ADDR 0x00a00
951/* px30 register definition end */
952
953/* rk3188 register definition */
954#define RK3188_SYS_CTRL 0x00
955#define RK3188_DSP_CTRL0 0x04
956#define RK3188_DSP_CTRL1 0x08
957#define RK3188_INT_STATUS 0x10
958#define RK3188_WIN0_YRGB_MST0 0x20
959#define RK3188_WIN0_CBR_MST0 0x24
960#define RK3188_WIN0_YRGB_MST1 0x28
961#define RK3188_WIN0_CBR_MST1 0x2c
962#define RK3188_WIN_VIR 0x30
963#define RK3188_WIN0_ACT_INFO 0x34
964#define RK3188_WIN0_DSP_INFO 0x38
965#define RK3188_WIN0_DSP_ST 0x3c
966#define RK3188_WIN0_SCL_FACTOR_YRGB 0x40
967#define RK3188_WIN0_SCL_FACTOR_CBR 0x44
968#define RK3188_WIN1_MST 0x4c
969#define RK3188_WIN1_DSP_INFO 0x50
970#define RK3188_WIN1_DSP_ST 0x54
971#define RK3188_DSP_HTOTAL_HS_END 0x6c
972#define RK3188_DSP_HACT_ST_END 0x70
973#define RK3188_DSP_VTOTAL_VS_END 0x74
974#define RK3188_DSP_VACT_ST_END 0x78
975#define RK3188_REG_CFG_DONE 0x90
976/* rk3188 register definition end */
977
978/* rk3066 register definition */
979#define RK3066_SYS_CTRL0 0x00
980#define RK3066_SYS_CTRL1 0x04
981#define RK3066_DSP_CTRL0 0x08
982#define RK3066_DSP_CTRL1 0x0c
983#define RK3066_INT_STATUS 0x10
984#define RK3066_MCU_CTRL 0x14
985#define RK3066_BLEND_CTRL 0x18
986#define RK3066_WIN0_COLOR_KEY_CTRL 0x1c
987#define RK3066_WIN1_COLOR_KEY_CTRL 0x20
988#define RK3066_WIN2_COLOR_KEY_CTRL 0x24
989#define RK3066_WIN0_YRGB_MST0 0x28
990#define RK3066_WIN0_CBR_MST0 0x2c
991#define RK3066_WIN0_YRGB_MST1 0x30
992#define RK3066_WIN0_CBR_MST1 0x34
993#define RK3066_WIN0_VIR 0x38
994#define RK3066_WIN0_ACT_INFO 0x3c
995#define RK3066_WIN0_DSP_INFO 0x40
996#define RK3066_WIN0_DSP_ST 0x44
997#define RK3066_WIN0_SCL_FACTOR_YRGB 0x48
998#define RK3066_WIN0_SCL_FACTOR_CBR 0x4c
999#define RK3066_WIN0_SCL_OFFSET 0x50
1000#define RK3066_WIN1_YRGB_MST 0x54
1001#define RK3066_WIN1_CBR_MST 0x58
1002#define RK3066_WIN1_VIR 0x5c
1003#define RK3066_WIN1_ACT_INFO 0x60
1004#define RK3066_WIN1_DSP_INFO 0x64
1005#define RK3066_WIN1_DSP_ST 0x68
1006#define RK3066_WIN1_SCL_FACTOR_YRGB 0x6c
1007#define RK3066_WIN1_SCL_FACTOR_CBR 0x70
1008#define RK3066_WIN1_SCL_OFFSET 0x74
1009#define RK3066_WIN2_MST 0x78
1010#define RK3066_WIN2_VIR 0x7c
1011#define RK3066_WIN2_DSP_INFO 0x80
1012#define RK3066_WIN2_DSP_ST 0x84
1013#define RK3066_HWC_MST 0x88
1014#define RK3066_HWC_DSP_ST 0x8c
1015#define RK3066_HWC_COLOR_LUT0 0x90
1016#define RK3066_HWC_COLOR_LUT1 0x94
1017#define RK3066_HWC_COLOR_LUT2 0x98
1018#define RK3066_DSP_HTOTAL_HS_END 0x9c
1019#define RK3066_DSP_HACT_ST_END 0xa0
1020#define RK3066_DSP_VTOTAL_VS_END 0xa4
1021#define RK3066_DSP_VACT_ST_END 0xa8
1022#define RK3066_DSP_VS_ST_END_F1 0xac
1023#define RK3066_DSP_VACT_ST_END_F1 0xb0
1024#define RK3066_REG_CFG_DONE 0xc0
1025#define RK3066_MCU_BYPASS_WPORT 0x100
1026#define RK3066_MCU_BYPASS_RPORT 0x200
1027#define RK3066_WIN2_LUT_ADDR 0x400
1028#define RK3066_DSP_LUT_ADDR 0x800
1029/* rk3066 register definition end */
1030
1031#endif /* _ROCKCHIP_VOP_REG_H */