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1/* SPDX-License-Identifier: GPL-2.0-only */
2/*
3 * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd
4 * Zheng Yang <zhengyang@rock-chips.com>
5 * Yakir Yang <ykk@rock-chips.com>
6 */
7
8#ifndef __INNO_HDMI_H__
9#define __INNO_HDMI_H__
10
11#define DDC_SEGMENT_ADDR 0x30
12
13enum PWR_MODE {
14 NORMAL,
15 LOWER_PWR,
16};
17
18#define HDMI_SCL_RATE (100*1000)
19#define DDC_BUS_FREQ_L 0x4b
20#define DDC_BUS_FREQ_H 0x4c
21
22#define HDMI_SYS_CTRL 0x00
23#define m_RST_ANALOG (1 << 6)
24#define v_RST_ANALOG (0 << 6)
25#define v_NOT_RST_ANALOG (1 << 6)
26#define m_RST_DIGITAL (1 << 5)
27#define v_RST_DIGITAL (0 << 5)
28#define v_NOT_RST_DIGITAL (1 << 5)
29#define m_REG_CLK_INV (1 << 4)
30#define v_REG_CLK_NOT_INV (0 << 4)
31#define v_REG_CLK_INV (1 << 4)
32#define m_VCLK_INV (1 << 3)
33#define v_VCLK_NOT_INV (0 << 3)
34#define v_VCLK_INV (1 << 3)
35#define m_REG_CLK_SOURCE (1 << 2)
36#define v_REG_CLK_SOURCE_TMDS (0 << 2)
37#define v_REG_CLK_SOURCE_SYS (1 << 2)
38#define m_POWER (1 << 1)
39#define v_PWR_ON (0 << 1)
40#define v_PWR_OFF (1 << 1)
41#define m_INT_POL (1 << 0)
42#define v_INT_POL_HIGH 1
43#define v_INT_POL_LOW 0
44
45#define HDMI_VIDEO_CONTRL1 0x01
46#define m_VIDEO_INPUT_FORMAT (7 << 1)
47#define m_DE_SOURCE (1 << 0)
48#define v_VIDEO_INPUT_FORMAT(n) (n << 1)
49#define v_DE_EXTERNAL 1
50#define v_DE_INTERNAL 0
51enum {
52 VIDEO_INPUT_SDR_RGB444 = 0,
53 VIDEO_INPUT_DDR_RGB444 = 5,
54 VIDEO_INPUT_DDR_YCBCR422 = 6
55};
56
57#define HDMI_VIDEO_CONTRL2 0x02
58#define m_VIDEO_OUTPUT_COLOR (3 << 6)
59#define m_VIDEO_INPUT_BITS (3 << 4)
60#define m_VIDEO_INPUT_CSP (1 << 0)
61#define v_VIDEO_OUTPUT_COLOR(n) (((n) & 0x3) << 6)
62#define v_VIDEO_INPUT_BITS(n) (n << 4)
63#define v_VIDEO_INPUT_CSP(n) (n << 0)
64enum {
65 VIDEO_INPUT_12BITS = 0,
66 VIDEO_INPUT_10BITS = 1,
67 VIDEO_INPUT_REVERT = 2,
68 VIDEO_INPUT_8BITS = 3,
69};
70
71#define HDMI_VIDEO_CONTRL 0x03
72#define m_VIDEO_AUTO_CSC (1 << 7)
73#define v_VIDEO_AUTO_CSC(n) (n << 7)
74#define m_VIDEO_C0_C2_SWAP (1 << 0)
75#define v_VIDEO_C0_C2_SWAP(n) (n << 0)
76enum {
77 C0_C2_CHANGE_ENABLE = 0,
78 C0_C2_CHANGE_DISABLE = 1,
79 AUTO_CSC_DISABLE = 0,
80 AUTO_CSC_ENABLE = 1,
81};
82
83#define HDMI_VIDEO_CONTRL3 0x04
84#define m_COLOR_DEPTH_NOT_INDICATED (1 << 4)
85#define m_SOF (1 << 3)
86#define m_COLOR_RANGE (1 << 2)
87#define m_CSC (1 << 0)
88#define v_COLOR_DEPTH_NOT_INDICATED(n) ((n) << 4)
89#define v_SOF_ENABLE (0 << 3)
90#define v_SOF_DISABLE (1 << 3)
91#define v_COLOR_RANGE_FULL (1 << 2)
92#define v_COLOR_RANGE_LIMITED (0 << 2)
93#define v_CSC_ENABLE 1
94#define v_CSC_DISABLE 0
95
96#define HDMI_AV_MUTE 0x05
97#define m_AVMUTE_CLEAR (1 << 7)
98#define m_AVMUTE_ENABLE (1 << 6)
99#define m_AUDIO_MUTE (1 << 1)
100#define m_VIDEO_BLACK (1 << 0)
101#define v_AVMUTE_CLEAR(n) (n << 7)
102#define v_AVMUTE_ENABLE(n) (n << 6)
103#define v_AUDIO_MUTE(n) (n << 1)
104#define v_VIDEO_MUTE(n) (n << 0)
105
106#define HDMI_VIDEO_TIMING_CTL 0x08
107#define v_HSYNC_POLARITY(n) (n << 3)
108#define v_VSYNC_POLARITY(n) (n << 2)
109#define v_INETLACE(n) (n << 1)
110#define v_EXTERANL_VIDEO(n) (n << 0)
111
112#define HDMI_VIDEO_EXT_HTOTAL_L 0x09
113#define HDMI_VIDEO_EXT_HTOTAL_H 0x0a
114#define HDMI_VIDEO_EXT_HBLANK_L 0x0b
115#define HDMI_VIDEO_EXT_HBLANK_H 0x0c
116#define HDMI_VIDEO_EXT_HDELAY_L 0x0d
117#define HDMI_VIDEO_EXT_HDELAY_H 0x0e
118#define HDMI_VIDEO_EXT_HDURATION_L 0x0f
119#define HDMI_VIDEO_EXT_HDURATION_H 0x10
120#define HDMI_VIDEO_EXT_VTOTAL_L 0x11
121#define HDMI_VIDEO_EXT_VTOTAL_H 0x12
122#define HDMI_VIDEO_EXT_VBLANK 0x13
123#define HDMI_VIDEO_EXT_VDELAY 0x14
124#define HDMI_VIDEO_EXT_VDURATION 0x15
125
126#define HDMI_VIDEO_CSC_COEF 0x18
127
128#define HDMI_AUDIO_CTRL1 0x35
129enum {
130 CTS_SOURCE_INTERNAL = 0,
131 CTS_SOURCE_EXTERNAL = 1,
132};
133#define v_CTS_SOURCE(n) (n << 7)
134
135enum {
136 DOWNSAMPLE_DISABLE = 0,
137 DOWNSAMPLE_1_2 = 1,
138 DOWNSAMPLE_1_4 = 2,
139};
140#define v_DOWN_SAMPLE(n) (n << 5)
141
142enum {
143 AUDIO_SOURCE_IIS = 0,
144 AUDIO_SOURCE_SPDIF = 1,
145};
146#define v_AUDIO_SOURCE(n) (n << 3)
147
148#define v_MCLK_ENABLE(n) (n << 2)
149enum {
150 MCLK_128FS = 0,
151 MCLK_256FS = 1,
152 MCLK_384FS = 2,
153 MCLK_512FS = 3,
154};
155#define v_MCLK_RATIO(n) (n)
156
157#define AUDIO_SAMPLE_RATE 0x37
158enum {
159 AUDIO_32K = 0x3,
160 AUDIO_441K = 0x0,
161 AUDIO_48K = 0x2,
162 AUDIO_882K = 0x8,
163 AUDIO_96K = 0xa,
164 AUDIO_1764K = 0xc,
165 AUDIO_192K = 0xe,
166};
167
168#define AUDIO_I2S_MODE 0x38
169enum {
170 I2S_CHANNEL_1_2 = 1,
171 I2S_CHANNEL_3_4 = 3,
172 I2S_CHANNEL_5_6 = 7,
173 I2S_CHANNEL_7_8 = 0xf
174};
175#define v_I2S_CHANNEL(n) ((n) << 2)
176enum {
177 I2S_STANDARD = 0,
178 I2S_LEFT_JUSTIFIED = 1,
179 I2S_RIGHT_JUSTIFIED = 2,
180};
181#define v_I2S_MODE(n) (n)
182
183#define AUDIO_I2S_MAP 0x39
184#define AUDIO_I2S_SWAPS_SPDIF 0x3a
185#define v_SPIDF_FREQ(n) (n)
186
187#define N_32K 0x1000
188#define N_441K 0x1880
189#define N_882K 0x3100
190#define N_1764K 0x6200
191#define N_48K 0x1800
192#define N_96K 0x3000
193#define N_192K 0x6000
194
195#define HDMI_AUDIO_CHANNEL_STATUS 0x3e
196#define m_AUDIO_STATUS_NLPCM (1 << 7)
197#define m_AUDIO_STATUS_USE (1 << 6)
198#define m_AUDIO_STATUS_COPYRIGHT (1 << 5)
199#define m_AUDIO_STATUS_ADDITION (3 << 2)
200#define m_AUDIO_STATUS_CLK_ACCURACY (2 << 0)
201#define v_AUDIO_STATUS_NLPCM(n) ((n & 1) << 7)
202#define AUDIO_N_H 0x3f
203#define AUDIO_N_M 0x40
204#define AUDIO_N_L 0x41
205
206#define HDMI_AUDIO_CTS_H 0x45
207#define HDMI_AUDIO_CTS_M 0x46
208#define HDMI_AUDIO_CTS_L 0x47
209
210#define HDMI_DDC_CLK_L 0x4b
211#define HDMI_DDC_CLK_H 0x4c
212
213#define HDMI_EDID_SEGMENT_POINTER 0x4d
214#define HDMI_EDID_WORD_ADDR 0x4e
215#define HDMI_EDID_FIFO_OFFSET 0x4f
216#define HDMI_EDID_FIFO_ADDR 0x50
217
218#define HDMI_PACKET_SEND_MANUAL 0x9c
219#define HDMI_PACKET_SEND_AUTO 0x9d
220#define m_PACKET_GCP_EN (1 << 7)
221#define m_PACKET_MSI_EN (1 << 6)
222#define m_PACKET_SDI_EN (1 << 5)
223#define m_PACKET_VSI_EN (1 << 4)
224#define v_PACKET_GCP_EN(n) ((n & 1) << 7)
225#define v_PACKET_MSI_EN(n) ((n & 1) << 6)
226#define v_PACKET_SDI_EN(n) ((n & 1) << 5)
227#define v_PACKET_VSI_EN(n) ((n & 1) << 4)
228
229#define HDMI_CONTROL_PACKET_BUF_INDEX 0x9f
230enum {
231 INFOFRAME_VSI = 0x05,
232 INFOFRAME_AVI = 0x06,
233 INFOFRAME_AAI = 0x08,
234};
235
236#define HDMI_CONTROL_PACKET_ADDR 0xa0
237#define HDMI_MAXIMUM_INFO_FRAME_SIZE 0x11
238enum {
239 AVI_COLOR_MODE_RGB = 0,
240 AVI_COLOR_MODE_YCBCR422 = 1,
241 AVI_COLOR_MODE_YCBCR444 = 2,
242 AVI_COLORIMETRY_NO_DATA = 0,
243
244 AVI_COLORIMETRY_SMPTE_170M = 1,
245 AVI_COLORIMETRY_ITU709 = 2,
246 AVI_COLORIMETRY_EXTENDED = 3,
247
248 AVI_CODED_FRAME_ASPECT_NO_DATA = 0,
249 AVI_CODED_FRAME_ASPECT_4_3 = 1,
250 AVI_CODED_FRAME_ASPECT_16_9 = 2,
251
252 ACTIVE_ASPECT_RATE_SAME_AS_CODED_FRAME = 0x08,
253 ACTIVE_ASPECT_RATE_4_3 = 0x09,
254 ACTIVE_ASPECT_RATE_16_9 = 0x0A,
255 ACTIVE_ASPECT_RATE_14_9 = 0x0B,
256};
257
258#define HDMI_HDCP_CTRL 0x52
259#define m_HDMI_DVI (1 << 1)
260#define v_HDMI_DVI(n) (n << 1)
261
262#define HDMI_INTERRUPT_MASK1 0xc0
263#define HDMI_INTERRUPT_STATUS1 0xc1
264#define m_INT_ACTIVE_VSYNC (1 << 5)
265#define m_INT_EDID_READY (1 << 2)
266
267#define HDMI_INTERRUPT_MASK2 0xc2
268#define HDMI_INTERRUPT_STATUS2 0xc3
269#define m_INT_HDCP_ERR (1 << 7)
270#define m_INT_BKSV_FLAG (1 << 6)
271#define m_INT_HDCP_OK (1 << 4)
272
273#define HDMI_STATUS 0xc8
274#define m_HOTPLUG (1 << 7)
275#define m_MASK_INT_HOTPLUG (1 << 5)
276#define m_INT_HOTPLUG (1 << 1)
277#define v_MASK_INT_HOTPLUG(n) ((n & 0x1) << 5)
278
279#define HDMI_COLORBAR 0xc9
280
281#define HDMI_PHY_SYNC 0xce
282#define HDMI_PHY_SYS_CTL 0xe0
283#define m_TMDS_CLK_SOURCE (1 << 5)
284#define v_TMDS_FROM_PLL (0 << 5)
285#define v_TMDS_FROM_GEN (1 << 5)
286#define m_PHASE_CLK (1 << 4)
287#define v_DEFAULT_PHASE (0 << 4)
288#define v_SYNC_PHASE (1 << 4)
289#define m_TMDS_CURRENT_PWR (1 << 3)
290#define v_TURN_ON_CURRENT (0 << 3)
291#define v_CAT_OFF_CURRENT (1 << 3)
292#define m_BANDGAP_PWR (1 << 2)
293#define v_BANDGAP_PWR_UP (0 << 2)
294#define v_BANDGAP_PWR_DOWN (1 << 2)
295#define m_PLL_PWR (1 << 1)
296#define v_PLL_PWR_UP (0 << 1)
297#define v_PLL_PWR_DOWN (1 << 1)
298#define m_TMDS_CHG_PWR (1 << 0)
299#define v_TMDS_CHG_PWR_UP (0 << 0)
300#define v_TMDS_CHG_PWR_DOWN (1 << 0)
301
302#define HDMI_PHY_CHG_PWR 0xe1
303#define v_CLK_CHG_PWR(n) ((n & 1) << 3)
304#define v_DATA_CHG_PWR(n) ((n & 7) << 0)
305
306#define HDMI_PHY_DRIVER 0xe2
307#define v_CLK_MAIN_DRIVER(n) (n << 4)
308#define v_DATA_MAIN_DRIVER(n) (n << 0)
309
310#define HDMI_PHY_PRE_EMPHASIS 0xe3
311#define v_PRE_EMPHASIS(n) ((n & 7) << 4)
312#define v_CLK_PRE_DRIVER(n) ((n & 3) << 2)
313#define v_DATA_PRE_DRIVER(n) ((n & 3) << 0)
314
315#define HDMI_PHY_FEEDBACK_DIV_RATIO_LOW 0xe7
316#define v_FEEDBACK_DIV_LOW(n) (n & 0xff)
317#define HDMI_PHY_FEEDBACK_DIV_RATIO_HIGH 0xe8
318#define v_FEEDBACK_DIV_HIGH(n) (n & 1)
319
320#define HDMI_PHY_PRE_DIV_RATIO 0xed
321#define v_PRE_DIV_RATIO(n) (n & 0x1f)
322
323#define HDMI_CEC_CTRL 0xd0
324#define m_ADJUST_FOR_HISENSE (1 << 6)
325#define m_REJECT_RX_BROADCAST (1 << 5)
326#define m_BUSFREETIME_ENABLE (1 << 2)
327#define m_REJECT_RX (1 << 1)
328#define m_START_TX (1 << 0)
329
330#define HDMI_CEC_DATA 0xd1
331#define HDMI_CEC_TX_OFFSET 0xd2
332#define HDMI_CEC_RX_OFFSET 0xd3
333#define HDMI_CEC_CLK_H 0xd4
334#define HDMI_CEC_CLK_L 0xd5
335#define HDMI_CEC_TX_LENGTH 0xd6
336#define HDMI_CEC_RX_LENGTH 0xd7
337#define HDMI_CEC_TX_INT_MASK 0xd8
338#define m_TX_DONE (1 << 3)
339#define m_TX_NOACK (1 << 2)
340#define m_TX_BROADCAST_REJ (1 << 1)
341#define m_TX_BUSNOTFREE (1 << 0)
342
343#define HDMI_CEC_RX_INT_MASK 0xd9
344#define m_RX_LA_ERR (1 << 4)
345#define m_RX_GLITCH (1 << 3)
346#define m_RX_DONE (1 << 0)
347
348#define HDMI_CEC_TX_INT 0xda
349#define HDMI_CEC_RX_INT 0xdb
350#define HDMI_CEC_BUSFREETIME_L 0xdc
351#define HDMI_CEC_BUSFREETIME_H 0xdd
352#define HDMI_CEC_LOGICADDR 0xde
353
354#endif /* __INNO_HDMI_H__ */