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1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28#include <linux/seq_file.h>
29#include <linux/slab.h>
30#include "drmP.h"
31#include "radeon_drm.h"
32#include "radeon_reg.h"
33#include "radeon.h"
34#include "atom.h"
35
36int radeon_debugfs_ib_init(struct radeon_device *rdev);
37
38void radeon_ib_bogus_cleanup(struct radeon_device *rdev)
39{
40 struct radeon_ib *ib, *n;
41
42 list_for_each_entry_safe(ib, n, &rdev->ib_pool.bogus_ib, list) {
43 list_del(&ib->list);
44 vfree(ib->ptr);
45 kfree(ib);
46 }
47}
48
49void radeon_ib_bogus_add(struct radeon_device *rdev, struct radeon_ib *ib)
50{
51 struct radeon_ib *bib;
52
53 bib = kmalloc(sizeof(*bib), GFP_KERNEL);
54 if (bib == NULL)
55 return;
56 bib->ptr = vmalloc(ib->length_dw * 4);
57 if (bib->ptr == NULL) {
58 kfree(bib);
59 return;
60 }
61 memcpy(bib->ptr, ib->ptr, ib->length_dw * 4);
62 bib->length_dw = ib->length_dw;
63 mutex_lock(&rdev->ib_pool.mutex);
64 list_add_tail(&bib->list, &rdev->ib_pool.bogus_ib);
65 mutex_unlock(&rdev->ib_pool.mutex);
66}
67
68/*
69 * IB.
70 */
71int radeon_ib_get(struct radeon_device *rdev, struct radeon_ib **ib)
72{
73 struct radeon_fence *fence;
74 struct radeon_ib *nib;
75 int r = 0, i, c;
76
77 *ib = NULL;
78 r = radeon_fence_create(rdev, &fence);
79 if (r) {
80 dev_err(rdev->dev, "failed to create fence for new IB\n");
81 return r;
82 }
83 mutex_lock(&rdev->ib_pool.mutex);
84 for (i = rdev->ib_pool.head_id, c = 0, nib = NULL; c < RADEON_IB_POOL_SIZE; c++, i++) {
85 i &= (RADEON_IB_POOL_SIZE - 1);
86 if (rdev->ib_pool.ibs[i].free) {
87 nib = &rdev->ib_pool.ibs[i];
88 break;
89 }
90 }
91 if (nib == NULL) {
92 /* This should never happen, it means we allocated all
93 * IB and haven't scheduled one yet, return EBUSY to
94 * userspace hoping that on ioctl recall we get better
95 * luck
96 */
97 dev_err(rdev->dev, "no free indirect buffer !\n");
98 mutex_unlock(&rdev->ib_pool.mutex);
99 radeon_fence_unref(&fence);
100 return -EBUSY;
101 }
102 rdev->ib_pool.head_id = (nib->idx + 1) & (RADEON_IB_POOL_SIZE - 1);
103 nib->free = false;
104 if (nib->fence) {
105 mutex_unlock(&rdev->ib_pool.mutex);
106 r = radeon_fence_wait(nib->fence, false);
107 if (r) {
108 dev_err(rdev->dev, "error waiting fence of IB(%u:0x%016lX:%u)\n",
109 nib->idx, (unsigned long)nib->gpu_addr, nib->length_dw);
110 mutex_lock(&rdev->ib_pool.mutex);
111 nib->free = true;
112 mutex_unlock(&rdev->ib_pool.mutex);
113 radeon_fence_unref(&fence);
114 return r;
115 }
116 mutex_lock(&rdev->ib_pool.mutex);
117 }
118 radeon_fence_unref(&nib->fence);
119 nib->fence = fence;
120 nib->length_dw = 0;
121 mutex_unlock(&rdev->ib_pool.mutex);
122 *ib = nib;
123 return 0;
124}
125
126void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib **ib)
127{
128 struct radeon_ib *tmp = *ib;
129
130 *ib = NULL;
131 if (tmp == NULL) {
132 return;
133 }
134 if (!tmp->fence->emited)
135 radeon_fence_unref(&tmp->fence);
136 mutex_lock(&rdev->ib_pool.mutex);
137 tmp->free = true;
138 mutex_unlock(&rdev->ib_pool.mutex);
139}
140
141int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib)
142{
143 int r = 0;
144
145 if (!ib->length_dw || !rdev->cp.ready) {
146 /* TODO: Nothings in the ib we should report. */
147 DRM_ERROR("radeon: couldn't schedule IB(%u).\n", ib->idx);
148 return -EINVAL;
149 }
150
151 /* 64 dwords should be enough for fence too */
152 r = radeon_ring_lock(rdev, 64);
153 if (r) {
154 DRM_ERROR("radeon: scheduling IB failed (%d).\n", r);
155 return r;
156 }
157 radeon_ring_ib_execute(rdev, ib);
158 radeon_fence_emit(rdev, ib->fence);
159 mutex_lock(&rdev->ib_pool.mutex);
160 /* once scheduled IB is considered free and protected by the fence */
161 ib->free = true;
162 mutex_unlock(&rdev->ib_pool.mutex);
163 radeon_ring_unlock_commit(rdev);
164 return 0;
165}
166
167int radeon_ib_pool_init(struct radeon_device *rdev)
168{
169 void *ptr;
170 uint64_t gpu_addr;
171 int i;
172 int r = 0;
173
174 if (rdev->ib_pool.robj)
175 return 0;
176 INIT_LIST_HEAD(&rdev->ib_pool.bogus_ib);
177 /* Allocate 1M object buffer */
178 r = radeon_bo_create(rdev, RADEON_IB_POOL_SIZE*64*1024,
179 PAGE_SIZE, true, RADEON_GEM_DOMAIN_GTT,
180 &rdev->ib_pool.robj);
181 if (r) {
182 DRM_ERROR("radeon: failed to ib pool (%d).\n", r);
183 return r;
184 }
185 r = radeon_bo_reserve(rdev->ib_pool.robj, false);
186 if (unlikely(r != 0))
187 return r;
188 r = radeon_bo_pin(rdev->ib_pool.robj, RADEON_GEM_DOMAIN_GTT, &gpu_addr);
189 if (r) {
190 radeon_bo_unreserve(rdev->ib_pool.robj);
191 DRM_ERROR("radeon: failed to pin ib pool (%d).\n", r);
192 return r;
193 }
194 r = radeon_bo_kmap(rdev->ib_pool.robj, &ptr);
195 radeon_bo_unreserve(rdev->ib_pool.robj);
196 if (r) {
197 DRM_ERROR("radeon: failed to map ib pool (%d).\n", r);
198 return r;
199 }
200 for (i = 0; i < RADEON_IB_POOL_SIZE; i++) {
201 unsigned offset;
202
203 offset = i * 64 * 1024;
204 rdev->ib_pool.ibs[i].gpu_addr = gpu_addr + offset;
205 rdev->ib_pool.ibs[i].ptr = ptr + offset;
206 rdev->ib_pool.ibs[i].idx = i;
207 rdev->ib_pool.ibs[i].length_dw = 0;
208 rdev->ib_pool.ibs[i].free = true;
209 }
210 rdev->ib_pool.head_id = 0;
211 rdev->ib_pool.ready = true;
212 DRM_INFO("radeon: ib pool ready.\n");
213 if (radeon_debugfs_ib_init(rdev)) {
214 DRM_ERROR("Failed to register debugfs file for IB !\n");
215 }
216 return r;
217}
218
219void radeon_ib_pool_fini(struct radeon_device *rdev)
220{
221 int r;
222 struct radeon_bo *robj;
223
224 if (!rdev->ib_pool.ready) {
225 return;
226 }
227 mutex_lock(&rdev->ib_pool.mutex);
228 radeon_ib_bogus_cleanup(rdev);
229 robj = rdev->ib_pool.robj;
230 rdev->ib_pool.robj = NULL;
231 mutex_unlock(&rdev->ib_pool.mutex);
232
233 if (robj) {
234 r = radeon_bo_reserve(robj, false);
235 if (likely(r == 0)) {
236 radeon_bo_kunmap(robj);
237 radeon_bo_unpin(robj);
238 radeon_bo_unreserve(robj);
239 }
240 radeon_bo_unref(&robj);
241 }
242}
243
244
245/*
246 * Ring.
247 */
248void radeon_ring_free_size(struct radeon_device *rdev)
249{
250 if (rdev->wb.enabled)
251 rdev->cp.rptr = le32_to_cpu(rdev->wb.wb[RADEON_WB_CP_RPTR_OFFSET/4]);
252 else {
253 if (rdev->family >= CHIP_R600)
254 rdev->cp.rptr = RREG32(R600_CP_RB_RPTR);
255 else
256 rdev->cp.rptr = RREG32(RADEON_CP_RB_RPTR);
257 }
258 /* This works because ring_size is a power of 2 */
259 rdev->cp.ring_free_dw = (rdev->cp.rptr + (rdev->cp.ring_size / 4));
260 rdev->cp.ring_free_dw -= rdev->cp.wptr;
261 rdev->cp.ring_free_dw &= rdev->cp.ptr_mask;
262 if (!rdev->cp.ring_free_dw) {
263 rdev->cp.ring_free_dw = rdev->cp.ring_size / 4;
264 }
265}
266
267int radeon_ring_alloc(struct radeon_device *rdev, unsigned ndw)
268{
269 int r;
270
271 /* Align requested size with padding so unlock_commit can
272 * pad safely */
273 ndw = (ndw + rdev->cp.align_mask) & ~rdev->cp.align_mask;
274 while (ndw > (rdev->cp.ring_free_dw - 1)) {
275 radeon_ring_free_size(rdev);
276 if (ndw < rdev->cp.ring_free_dw) {
277 break;
278 }
279 r = radeon_fence_wait_next(rdev);
280 if (r)
281 return r;
282 }
283 rdev->cp.count_dw = ndw;
284 rdev->cp.wptr_old = rdev->cp.wptr;
285 return 0;
286}
287
288int radeon_ring_lock(struct radeon_device *rdev, unsigned ndw)
289{
290 int r;
291
292 mutex_lock(&rdev->cp.mutex);
293 r = radeon_ring_alloc(rdev, ndw);
294 if (r) {
295 mutex_unlock(&rdev->cp.mutex);
296 return r;
297 }
298 return 0;
299}
300
301void radeon_ring_commit(struct radeon_device *rdev)
302{
303 unsigned count_dw_pad;
304 unsigned i;
305
306 /* We pad to match fetch size */
307 count_dw_pad = (rdev->cp.align_mask + 1) -
308 (rdev->cp.wptr & rdev->cp.align_mask);
309 for (i = 0; i < count_dw_pad; i++) {
310 radeon_ring_write(rdev, 2 << 30);
311 }
312 DRM_MEMORYBARRIER();
313 radeon_cp_commit(rdev);
314}
315
316void radeon_ring_unlock_commit(struct radeon_device *rdev)
317{
318 radeon_ring_commit(rdev);
319 mutex_unlock(&rdev->cp.mutex);
320}
321
322void radeon_ring_unlock_undo(struct radeon_device *rdev)
323{
324 rdev->cp.wptr = rdev->cp.wptr_old;
325 mutex_unlock(&rdev->cp.mutex);
326}
327
328int radeon_ring_init(struct radeon_device *rdev, unsigned ring_size)
329{
330 int r;
331
332 rdev->cp.ring_size = ring_size;
333 /* Allocate ring buffer */
334 if (rdev->cp.ring_obj == NULL) {
335 r = radeon_bo_create(rdev, rdev->cp.ring_size, PAGE_SIZE, true,
336 RADEON_GEM_DOMAIN_GTT,
337 &rdev->cp.ring_obj);
338 if (r) {
339 dev_err(rdev->dev, "(%d) ring create failed\n", r);
340 return r;
341 }
342 r = radeon_bo_reserve(rdev->cp.ring_obj, false);
343 if (unlikely(r != 0))
344 return r;
345 r = radeon_bo_pin(rdev->cp.ring_obj, RADEON_GEM_DOMAIN_GTT,
346 &rdev->cp.gpu_addr);
347 if (r) {
348 radeon_bo_unreserve(rdev->cp.ring_obj);
349 dev_err(rdev->dev, "(%d) ring pin failed\n", r);
350 return r;
351 }
352 r = radeon_bo_kmap(rdev->cp.ring_obj,
353 (void **)&rdev->cp.ring);
354 radeon_bo_unreserve(rdev->cp.ring_obj);
355 if (r) {
356 dev_err(rdev->dev, "(%d) ring map failed\n", r);
357 return r;
358 }
359 }
360 rdev->cp.ptr_mask = (rdev->cp.ring_size / 4) - 1;
361 rdev->cp.ring_free_dw = rdev->cp.ring_size / 4;
362 return 0;
363}
364
365void radeon_ring_fini(struct radeon_device *rdev)
366{
367 int r;
368 struct radeon_bo *ring_obj;
369
370 mutex_lock(&rdev->cp.mutex);
371 ring_obj = rdev->cp.ring_obj;
372 rdev->cp.ring = NULL;
373 rdev->cp.ring_obj = NULL;
374 mutex_unlock(&rdev->cp.mutex);
375
376 if (ring_obj) {
377 r = radeon_bo_reserve(ring_obj, false);
378 if (likely(r == 0)) {
379 radeon_bo_kunmap(ring_obj);
380 radeon_bo_unpin(ring_obj);
381 radeon_bo_unreserve(ring_obj);
382 }
383 radeon_bo_unref(&ring_obj);
384 }
385}
386
387
388/*
389 * Debugfs info
390 */
391#if defined(CONFIG_DEBUG_FS)
392static int radeon_debugfs_ib_info(struct seq_file *m, void *data)
393{
394 struct drm_info_node *node = (struct drm_info_node *) m->private;
395 struct radeon_ib *ib = node->info_ent->data;
396 unsigned i;
397
398 if (ib == NULL) {
399 return 0;
400 }
401 seq_printf(m, "IB %04u\n", ib->idx);
402 seq_printf(m, "IB fence %p\n", ib->fence);
403 seq_printf(m, "IB size %05u dwords\n", ib->length_dw);
404 for (i = 0; i < ib->length_dw; i++) {
405 seq_printf(m, "[%05u]=0x%08X\n", i, ib->ptr[i]);
406 }
407 return 0;
408}
409
410static int radeon_debugfs_ib_bogus_info(struct seq_file *m, void *data)
411{
412 struct drm_info_node *node = (struct drm_info_node *) m->private;
413 struct radeon_device *rdev = node->info_ent->data;
414 struct radeon_ib *ib;
415 unsigned i;
416
417 mutex_lock(&rdev->ib_pool.mutex);
418 if (list_empty(&rdev->ib_pool.bogus_ib)) {
419 mutex_unlock(&rdev->ib_pool.mutex);
420 seq_printf(m, "no bogus IB recorded\n");
421 return 0;
422 }
423 ib = list_first_entry(&rdev->ib_pool.bogus_ib, struct radeon_ib, list);
424 list_del_init(&ib->list);
425 mutex_unlock(&rdev->ib_pool.mutex);
426 seq_printf(m, "IB size %05u dwords\n", ib->length_dw);
427 for (i = 0; i < ib->length_dw; i++) {
428 seq_printf(m, "[%05u]=0x%08X\n", i, ib->ptr[i]);
429 }
430 vfree(ib->ptr);
431 kfree(ib);
432 return 0;
433}
434
435static struct drm_info_list radeon_debugfs_ib_list[RADEON_IB_POOL_SIZE];
436static char radeon_debugfs_ib_names[RADEON_IB_POOL_SIZE][32];
437
438static struct drm_info_list radeon_debugfs_ib_bogus_info_list[] = {
439 {"radeon_ib_bogus", radeon_debugfs_ib_bogus_info, 0, NULL},
440};
441#endif
442
443int radeon_debugfs_ib_init(struct radeon_device *rdev)
444{
445#if defined(CONFIG_DEBUG_FS)
446 unsigned i;
447 int r;
448
449 radeon_debugfs_ib_bogus_info_list[0].data = rdev;
450 r = radeon_debugfs_add_files(rdev, radeon_debugfs_ib_bogus_info_list, 1);
451 if (r)
452 return r;
453 for (i = 0; i < RADEON_IB_POOL_SIZE; i++) {
454 sprintf(radeon_debugfs_ib_names[i], "radeon_ib_%04u", i);
455 radeon_debugfs_ib_list[i].name = radeon_debugfs_ib_names[i];
456 radeon_debugfs_ib_list[i].show = &radeon_debugfs_ib_info;
457 radeon_debugfs_ib_list[i].driver_features = 0;
458 radeon_debugfs_ib_list[i].data = &rdev->ib_pool.ibs[i];
459 }
460 return radeon_debugfs_add_files(rdev, radeon_debugfs_ib_list,
461 RADEON_IB_POOL_SIZE);
462#else
463 return 0;
464#endif
465}
1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 * Christian König
28 */
29
30#include <drm/drm_debugfs.h>
31#include <drm/drm_device.h>
32#include <drm/drm_file.h>
33
34#include "radeon.h"
35
36/*
37 * Rings
38 * Most engines on the GPU are fed via ring buffers. Ring
39 * buffers are areas of GPU accessible memory that the host
40 * writes commands into and the GPU reads commands out of.
41 * There is a rptr (read pointer) that determines where the
42 * GPU is currently reading, and a wptr (write pointer)
43 * which determines where the host has written. When the
44 * pointers are equal, the ring is idle. When the host
45 * writes commands to the ring buffer, it increments the
46 * wptr. The GPU then starts fetching commands and executes
47 * them until the pointers are equal again.
48 */
49static int radeon_debugfs_ring_init(struct radeon_device *rdev, struct radeon_ring *ring);
50
51/**
52 * radeon_ring_supports_scratch_reg - check if the ring supports
53 * writing to scratch registers
54 *
55 * @rdev: radeon_device pointer
56 * @ring: radeon_ring structure holding ring information
57 *
58 * Check if a specific ring supports writing to scratch registers (all asics).
59 * Returns true if the ring supports writing to scratch regs, false if not.
60 */
61bool radeon_ring_supports_scratch_reg(struct radeon_device *rdev,
62 struct radeon_ring *ring)
63{
64 switch (ring->idx) {
65 case RADEON_RING_TYPE_GFX_INDEX:
66 case CAYMAN_RING_TYPE_CP1_INDEX:
67 case CAYMAN_RING_TYPE_CP2_INDEX:
68 return true;
69 default:
70 return false;
71 }
72}
73
74/**
75 * radeon_ring_free_size - update the free size
76 *
77 * @rdev: radeon_device pointer
78 * @ring: radeon_ring structure holding ring information
79 *
80 * Update the free dw slots in the ring buffer (all asics).
81 */
82void radeon_ring_free_size(struct radeon_device *rdev, struct radeon_ring *ring)
83{
84 uint32_t rptr = radeon_ring_get_rptr(rdev, ring);
85
86 /* This works because ring_size is a power of 2 */
87 ring->ring_free_dw = rptr + (ring->ring_size / 4);
88 ring->ring_free_dw -= ring->wptr;
89 ring->ring_free_dw &= ring->ptr_mask;
90 if (!ring->ring_free_dw) {
91 /* this is an empty ring */
92 ring->ring_free_dw = ring->ring_size / 4;
93 /* update lockup info to avoid false positive */
94 radeon_ring_lockup_update(rdev, ring);
95 }
96}
97
98/**
99 * radeon_ring_alloc - allocate space on the ring buffer
100 *
101 * @rdev: radeon_device pointer
102 * @ring: radeon_ring structure holding ring information
103 * @ndw: number of dwords to allocate in the ring buffer
104 *
105 * Allocate @ndw dwords in the ring buffer (all asics).
106 * Returns 0 on success, error on failure.
107 */
108int radeon_ring_alloc(struct radeon_device *rdev, struct radeon_ring *ring, unsigned ndw)
109{
110 int r;
111
112 /* make sure we aren't trying to allocate more space than there is on the ring */
113 if (ndw > (ring->ring_size / 4))
114 return -ENOMEM;
115 /* Align requested size with padding so unlock_commit can
116 * pad safely */
117 radeon_ring_free_size(rdev, ring);
118 ndw = (ndw + ring->align_mask) & ~ring->align_mask;
119 while (ndw > (ring->ring_free_dw - 1)) {
120 radeon_ring_free_size(rdev, ring);
121 if (ndw < ring->ring_free_dw) {
122 break;
123 }
124 r = radeon_fence_wait_next(rdev, ring->idx);
125 if (r)
126 return r;
127 }
128 ring->count_dw = ndw;
129 ring->wptr_old = ring->wptr;
130 return 0;
131}
132
133/**
134 * radeon_ring_lock - lock the ring and allocate space on it
135 *
136 * @rdev: radeon_device pointer
137 * @ring: radeon_ring structure holding ring information
138 * @ndw: number of dwords to allocate in the ring buffer
139 *
140 * Lock the ring and allocate @ndw dwords in the ring buffer
141 * (all asics).
142 * Returns 0 on success, error on failure.
143 */
144int radeon_ring_lock(struct radeon_device *rdev, struct radeon_ring *ring, unsigned ndw)
145{
146 int r;
147
148 mutex_lock(&rdev->ring_lock);
149 r = radeon_ring_alloc(rdev, ring, ndw);
150 if (r) {
151 mutex_unlock(&rdev->ring_lock);
152 return r;
153 }
154 return 0;
155}
156
157/**
158 * radeon_ring_commit - tell the GPU to execute the new
159 * commands on the ring buffer
160 *
161 * @rdev: radeon_device pointer
162 * @ring: radeon_ring structure holding ring information
163 * @hdp_flush: Whether or not to perform an HDP cache flush
164 *
165 * Update the wptr (write pointer) to tell the GPU to
166 * execute new commands on the ring buffer (all asics).
167 */
168void radeon_ring_commit(struct radeon_device *rdev, struct radeon_ring *ring,
169 bool hdp_flush)
170{
171 /* If we are emitting the HDP flush via the ring buffer, we need to
172 * do it before padding.
173 */
174 if (hdp_flush && rdev->asic->ring[ring->idx]->hdp_flush)
175 rdev->asic->ring[ring->idx]->hdp_flush(rdev, ring);
176 /* We pad to match fetch size */
177 while (ring->wptr & ring->align_mask) {
178 radeon_ring_write(ring, ring->nop);
179 }
180 mb();
181 /* If we are emitting the HDP flush via MMIO, we need to do it after
182 * all CPU writes to VRAM finished.
183 */
184 if (hdp_flush && rdev->asic->mmio_hdp_flush)
185 rdev->asic->mmio_hdp_flush(rdev);
186 radeon_ring_set_wptr(rdev, ring);
187}
188
189/**
190 * radeon_ring_unlock_commit - tell the GPU to execute the new
191 * commands on the ring buffer and unlock it
192 *
193 * @rdev: radeon_device pointer
194 * @ring: radeon_ring structure holding ring information
195 * @hdp_flush: Whether or not to perform an HDP cache flush
196 *
197 * Call radeon_ring_commit() then unlock the ring (all asics).
198 */
199void radeon_ring_unlock_commit(struct radeon_device *rdev, struct radeon_ring *ring,
200 bool hdp_flush)
201{
202 radeon_ring_commit(rdev, ring, hdp_flush);
203 mutex_unlock(&rdev->ring_lock);
204}
205
206/**
207 * radeon_ring_undo - reset the wptr
208 *
209 * @ring: radeon_ring structure holding ring information
210 *
211 * Reset the driver's copy of the wptr (all asics).
212 */
213void radeon_ring_undo(struct radeon_ring *ring)
214{
215 ring->wptr = ring->wptr_old;
216}
217
218/**
219 * radeon_ring_unlock_undo - reset the wptr and unlock the ring
220 *
221 * @ring: radeon_ring structure holding ring information
222 *
223 * Call radeon_ring_undo() then unlock the ring (all asics).
224 */
225void radeon_ring_unlock_undo(struct radeon_device *rdev, struct radeon_ring *ring)
226{
227 radeon_ring_undo(ring);
228 mutex_unlock(&rdev->ring_lock);
229}
230
231/**
232 * radeon_ring_lockup_update - update lockup variables
233 *
234 * @ring: radeon_ring structure holding ring information
235 *
236 * Update the last rptr value and timestamp (all asics).
237 */
238void radeon_ring_lockup_update(struct radeon_device *rdev,
239 struct radeon_ring *ring)
240{
241 atomic_set(&ring->last_rptr, radeon_ring_get_rptr(rdev, ring));
242 atomic64_set(&ring->last_activity, jiffies_64);
243}
244
245/**
246 * radeon_ring_test_lockup() - check if ring is lockedup by recording information
247 * @rdev: radeon device structure
248 * @ring: radeon_ring structure holding ring information
249 *
250 */
251bool radeon_ring_test_lockup(struct radeon_device *rdev, struct radeon_ring *ring)
252{
253 uint32_t rptr = radeon_ring_get_rptr(rdev, ring);
254 uint64_t last = atomic64_read(&ring->last_activity);
255 uint64_t elapsed;
256
257 if (rptr != atomic_read(&ring->last_rptr)) {
258 /* ring is still working, no lockup */
259 radeon_ring_lockup_update(rdev, ring);
260 return false;
261 }
262
263 elapsed = jiffies_to_msecs(jiffies_64 - last);
264 if (radeon_lockup_timeout && elapsed >= radeon_lockup_timeout) {
265 dev_err(rdev->dev, "ring %d stalled for more than %llumsec\n",
266 ring->idx, elapsed);
267 return true;
268 }
269 /* give a chance to the GPU ... */
270 return false;
271}
272
273/**
274 * radeon_ring_backup - Back up the content of a ring
275 *
276 * @rdev: radeon_device pointer
277 * @ring: the ring we want to back up
278 *
279 * Saves all unprocessed commits from a ring, returns the number of dwords saved.
280 */
281unsigned radeon_ring_backup(struct radeon_device *rdev, struct radeon_ring *ring,
282 uint32_t **data)
283{
284 unsigned size, ptr, i;
285
286 /* just in case lock the ring */
287 mutex_lock(&rdev->ring_lock);
288 *data = NULL;
289
290 if (ring->ring_obj == NULL) {
291 mutex_unlock(&rdev->ring_lock);
292 return 0;
293 }
294
295 /* it doesn't make sense to save anything if all fences are signaled */
296 if (!radeon_fence_count_emitted(rdev, ring->idx)) {
297 mutex_unlock(&rdev->ring_lock);
298 return 0;
299 }
300
301 /* calculate the number of dw on the ring */
302 if (ring->rptr_save_reg)
303 ptr = RREG32(ring->rptr_save_reg);
304 else if (rdev->wb.enabled)
305 ptr = le32_to_cpu(*ring->next_rptr_cpu_addr);
306 else {
307 /* no way to read back the next rptr */
308 mutex_unlock(&rdev->ring_lock);
309 return 0;
310 }
311
312 size = ring->wptr + (ring->ring_size / 4);
313 size -= ptr;
314 size &= ring->ptr_mask;
315 if (size == 0) {
316 mutex_unlock(&rdev->ring_lock);
317 return 0;
318 }
319
320 /* and then save the content of the ring */
321 *data = kvmalloc_array(size, sizeof(uint32_t), GFP_KERNEL);
322 if (!*data) {
323 mutex_unlock(&rdev->ring_lock);
324 return 0;
325 }
326 for (i = 0; i < size; ++i) {
327 (*data)[i] = ring->ring[ptr++];
328 ptr &= ring->ptr_mask;
329 }
330
331 mutex_unlock(&rdev->ring_lock);
332 return size;
333}
334
335/**
336 * radeon_ring_restore - append saved commands to the ring again
337 *
338 * @rdev: radeon_device pointer
339 * @ring: ring to append commands to
340 * @size: number of dwords we want to write
341 * @data: saved commands
342 *
343 * Allocates space on the ring and restore the previously saved commands.
344 */
345int radeon_ring_restore(struct radeon_device *rdev, struct radeon_ring *ring,
346 unsigned size, uint32_t *data)
347{
348 int i, r;
349
350 if (!size || !data)
351 return 0;
352
353 /* restore the saved ring content */
354 r = radeon_ring_lock(rdev, ring, size);
355 if (r)
356 return r;
357
358 for (i = 0; i < size; ++i) {
359 radeon_ring_write(ring, data[i]);
360 }
361
362 radeon_ring_unlock_commit(rdev, ring, false);
363 kvfree(data);
364 return 0;
365}
366
367/**
368 * radeon_ring_init - init driver ring struct.
369 *
370 * @rdev: radeon_device pointer
371 * @ring: radeon_ring structure holding ring information
372 * @ring_size: size of the ring
373 * @rptr_offs: offset of the rptr writeback location in the WB buffer
374 * @nop: nop packet for this ring
375 *
376 * Initialize the driver information for the selected ring (all asics).
377 * Returns 0 on success, error on failure.
378 */
379int radeon_ring_init(struct radeon_device *rdev, struct radeon_ring *ring, unsigned ring_size,
380 unsigned rptr_offs, u32 nop)
381{
382 int r;
383
384 ring->ring_size = ring_size;
385 ring->rptr_offs = rptr_offs;
386 ring->nop = nop;
387 /* Allocate ring buffer */
388 if (ring->ring_obj == NULL) {
389 r = radeon_bo_create(rdev, ring->ring_size, PAGE_SIZE, true,
390 RADEON_GEM_DOMAIN_GTT, 0, NULL,
391 NULL, &ring->ring_obj);
392 if (r) {
393 dev_err(rdev->dev, "(%d) ring create failed\n", r);
394 return r;
395 }
396 r = radeon_bo_reserve(ring->ring_obj, false);
397 if (unlikely(r != 0))
398 return r;
399 r = radeon_bo_pin(ring->ring_obj, RADEON_GEM_DOMAIN_GTT,
400 &ring->gpu_addr);
401 if (r) {
402 radeon_bo_unreserve(ring->ring_obj);
403 dev_err(rdev->dev, "(%d) ring pin failed\n", r);
404 return r;
405 }
406 r = radeon_bo_kmap(ring->ring_obj,
407 (void **)&ring->ring);
408 radeon_bo_unreserve(ring->ring_obj);
409 if (r) {
410 dev_err(rdev->dev, "(%d) ring map failed\n", r);
411 return r;
412 }
413 }
414 ring->ptr_mask = (ring->ring_size / 4) - 1;
415 ring->ring_free_dw = ring->ring_size / 4;
416 if (rdev->wb.enabled) {
417 u32 index = RADEON_WB_RING0_NEXT_RPTR + (ring->idx * 4);
418 ring->next_rptr_gpu_addr = rdev->wb.gpu_addr + index;
419 ring->next_rptr_cpu_addr = &rdev->wb.wb[index/4];
420 }
421 if (radeon_debugfs_ring_init(rdev, ring)) {
422 DRM_ERROR("Failed to register debugfs file for rings !\n");
423 }
424 radeon_ring_lockup_update(rdev, ring);
425 return 0;
426}
427
428/**
429 * radeon_ring_fini - tear down the driver ring struct.
430 *
431 * @rdev: radeon_device pointer
432 * @ring: radeon_ring structure holding ring information
433 *
434 * Tear down the driver information for the selected ring (all asics).
435 */
436void radeon_ring_fini(struct radeon_device *rdev, struct radeon_ring *ring)
437{
438 int r;
439 struct radeon_bo *ring_obj;
440
441 mutex_lock(&rdev->ring_lock);
442 ring_obj = ring->ring_obj;
443 ring->ready = false;
444 ring->ring = NULL;
445 ring->ring_obj = NULL;
446 mutex_unlock(&rdev->ring_lock);
447
448 if (ring_obj) {
449 r = radeon_bo_reserve(ring_obj, false);
450 if (likely(r == 0)) {
451 radeon_bo_kunmap(ring_obj);
452 radeon_bo_unpin(ring_obj);
453 radeon_bo_unreserve(ring_obj);
454 }
455 radeon_bo_unref(&ring_obj);
456 }
457}
458
459/*
460 * Debugfs info
461 */
462#if defined(CONFIG_DEBUG_FS)
463
464static int radeon_debugfs_ring_info(struct seq_file *m, void *data)
465{
466 struct drm_info_node *node = (struct drm_info_node *) m->private;
467 struct drm_device *dev = node->minor->dev;
468 struct radeon_device *rdev = dev->dev_private;
469 int ridx = *(int*)node->info_ent->data;
470 struct radeon_ring *ring = &rdev->ring[ridx];
471
472 uint32_t rptr, wptr, rptr_next;
473 unsigned count, i, j;
474
475 radeon_ring_free_size(rdev, ring);
476 count = (ring->ring_size / 4) - ring->ring_free_dw;
477
478 wptr = radeon_ring_get_wptr(rdev, ring);
479 seq_printf(m, "wptr: 0x%08x [%5d]\n",
480 wptr, wptr);
481
482 rptr = radeon_ring_get_rptr(rdev, ring);
483 seq_printf(m, "rptr: 0x%08x [%5d]\n",
484 rptr, rptr);
485
486 if (ring->rptr_save_reg) {
487 rptr_next = RREG32(ring->rptr_save_reg);
488 seq_printf(m, "rptr next(0x%04x): 0x%08x [%5d]\n",
489 ring->rptr_save_reg, rptr_next, rptr_next);
490 } else
491 rptr_next = ~0;
492
493 seq_printf(m, "driver's copy of the wptr: 0x%08x [%5d]\n",
494 ring->wptr, ring->wptr);
495 seq_printf(m, "last semaphore signal addr : 0x%016llx\n",
496 ring->last_semaphore_signal_addr);
497 seq_printf(m, "last semaphore wait addr : 0x%016llx\n",
498 ring->last_semaphore_wait_addr);
499 seq_printf(m, "%u free dwords in ring\n", ring->ring_free_dw);
500 seq_printf(m, "%u dwords in ring\n", count);
501
502 if (!ring->ring)
503 return 0;
504
505 /* print 8 dw before current rptr as often it's the last executed
506 * packet that is the root issue
507 */
508 i = (rptr + ring->ptr_mask + 1 - 32) & ring->ptr_mask;
509 for (j = 0; j <= (count + 32); j++) {
510 seq_printf(m, "r[%5d]=0x%08x", i, ring->ring[i]);
511 if (rptr == i)
512 seq_puts(m, " *");
513 if (rptr_next == i)
514 seq_puts(m, " #");
515 seq_puts(m, "\n");
516 i = (i + 1) & ring->ptr_mask;
517 }
518 return 0;
519}
520
521static int radeon_gfx_index = RADEON_RING_TYPE_GFX_INDEX;
522static int cayman_cp1_index = CAYMAN_RING_TYPE_CP1_INDEX;
523static int cayman_cp2_index = CAYMAN_RING_TYPE_CP2_INDEX;
524static int radeon_dma1_index = R600_RING_TYPE_DMA_INDEX;
525static int radeon_dma2_index = CAYMAN_RING_TYPE_DMA1_INDEX;
526static int r600_uvd_index = R600_RING_TYPE_UVD_INDEX;
527static int si_vce1_index = TN_RING_TYPE_VCE1_INDEX;
528static int si_vce2_index = TN_RING_TYPE_VCE2_INDEX;
529
530static struct drm_info_list radeon_debugfs_ring_info_list[] = {
531 {"radeon_ring_gfx", radeon_debugfs_ring_info, 0, &radeon_gfx_index},
532 {"radeon_ring_cp1", radeon_debugfs_ring_info, 0, &cayman_cp1_index},
533 {"radeon_ring_cp2", radeon_debugfs_ring_info, 0, &cayman_cp2_index},
534 {"radeon_ring_dma1", radeon_debugfs_ring_info, 0, &radeon_dma1_index},
535 {"radeon_ring_dma2", radeon_debugfs_ring_info, 0, &radeon_dma2_index},
536 {"radeon_ring_uvd", radeon_debugfs_ring_info, 0, &r600_uvd_index},
537 {"radeon_ring_vce1", radeon_debugfs_ring_info, 0, &si_vce1_index},
538 {"radeon_ring_vce2", radeon_debugfs_ring_info, 0, &si_vce2_index},
539};
540
541#endif
542
543static int radeon_debugfs_ring_init(struct radeon_device *rdev, struct radeon_ring *ring)
544{
545#if defined(CONFIG_DEBUG_FS)
546 unsigned i;
547 for (i = 0; i < ARRAY_SIZE(radeon_debugfs_ring_info_list); ++i) {
548 struct drm_info_list *info = &radeon_debugfs_ring_info_list[i];
549 int ridx = *(int*)radeon_debugfs_ring_info_list[i].data;
550 unsigned r;
551
552 if (&rdev->ring[ridx] != ring)
553 continue;
554
555 r = radeon_debugfs_add_files(rdev, info, 1);
556 if (r)
557 return r;
558 }
559#endif
560 return 0;
561}