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1/*
2 * Copyright 2018 Red Hat Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 */
22#include "head.h"
23#include "base.h"
24#include "core.h"
25#include "curs.h"
26#include "ovly.h"
27
28#include <nvif/class.h>
29
30#include <drm/drm_atomic_helper.h>
31#include <drm/drm_crtc_helper.h>
32#include "nouveau_connector.h"
33void
34nv50_head_flush_clr(struct nv50_head *head,
35 struct nv50_head_atom *asyh, bool flush)
36{
37 union nv50_head_atom_mask clr = {
38 .mask = asyh->clr.mask & ~(flush ? 0 : asyh->set.mask),
39 };
40 if (clr.olut) head->func->olut_clr(head);
41 if (clr.core) head->func->core_clr(head);
42 if (clr.curs) head->func->curs_clr(head);
43}
44
45void
46nv50_head_flush_set(struct nv50_head *head, struct nv50_head_atom *asyh)
47{
48 if (asyh->set.view ) head->func->view (head, asyh);
49 if (asyh->set.mode ) head->func->mode (head, asyh);
50 if (asyh->set.core ) head->func->core_set(head, asyh);
51 if (asyh->set.olut ) {
52 asyh->olut.offset = nv50_lut_load(&head->olut,
53 asyh->olut.buffer,
54 asyh->state.gamma_lut,
55 asyh->olut.load);
56 head->func->olut_set(head, asyh);
57 }
58 if (asyh->set.curs ) head->func->curs_set(head, asyh);
59 if (asyh->set.base ) head->func->base (head, asyh);
60 if (asyh->set.ovly ) head->func->ovly (head, asyh);
61 if (asyh->set.dither ) head->func->dither (head, asyh);
62 if (asyh->set.procamp) head->func->procamp (head, asyh);
63 if (asyh->set.or ) head->func->or (head, asyh);
64}
65
66static void
67nv50_head_atomic_check_procamp(struct nv50_head_atom *armh,
68 struct nv50_head_atom *asyh,
69 struct nouveau_conn_atom *asyc)
70{
71 const int vib = asyc->procamp.color_vibrance - 100;
72 const int hue = asyc->procamp.vibrant_hue - 90;
73 const int adj = (vib > 0) ? 50 : 0;
74 asyh->procamp.sat.cos = ((vib * 2047 + adj) / 100) & 0xfff;
75 asyh->procamp.sat.sin = ((hue * 2047) / 100) & 0xfff;
76 asyh->set.procamp = true;
77}
78
79static void
80nv50_head_atomic_check_dither(struct nv50_head_atom *armh,
81 struct nv50_head_atom *asyh,
82 struct nouveau_conn_atom *asyc)
83{
84 struct drm_connector *connector = asyc->state.connector;
85 u32 mode = 0x00;
86
87 if (asyc->dither.mode == DITHERING_MODE_AUTO) {
88 if (asyh->base.depth > connector->display_info.bpc * 3)
89 mode = DITHERING_MODE_DYNAMIC2X2;
90 } else {
91 mode = asyc->dither.mode;
92 }
93
94 if (asyc->dither.depth == DITHERING_DEPTH_AUTO) {
95 if (connector->display_info.bpc >= 8)
96 mode |= DITHERING_DEPTH_8BPC;
97 } else {
98 mode |= asyc->dither.depth;
99 }
100
101 asyh->dither.enable = mode;
102 asyh->dither.bits = mode >> 1;
103 asyh->dither.mode = mode >> 3;
104 asyh->set.dither = true;
105}
106
107static void
108nv50_head_atomic_check_view(struct nv50_head_atom *armh,
109 struct nv50_head_atom *asyh,
110 struct nouveau_conn_atom *asyc)
111{
112 struct drm_connector *connector = asyc->state.connector;
113 struct drm_display_mode *omode = &asyh->state.adjusted_mode;
114 struct drm_display_mode *umode = &asyh->state.mode;
115 int mode = asyc->scaler.mode;
116 struct edid *edid;
117 int umode_vdisplay, omode_hdisplay, omode_vdisplay;
118
119 if (connector->edid_blob_ptr)
120 edid = (struct edid *)connector->edid_blob_ptr->data;
121 else
122 edid = NULL;
123
124 if (!asyc->scaler.full) {
125 if (mode == DRM_MODE_SCALE_NONE)
126 omode = umode;
127 } else {
128 /* Non-EDID LVDS/eDP mode. */
129 mode = DRM_MODE_SCALE_FULLSCREEN;
130 }
131
132 /* For the user-specified mode, we must ignore doublescan and
133 * the like, but honor frame packing.
134 */
135 umode_vdisplay = umode->vdisplay;
136 if ((umode->flags & DRM_MODE_FLAG_3D_MASK) == DRM_MODE_FLAG_3D_FRAME_PACKING)
137 umode_vdisplay += umode->vtotal;
138 asyh->view.iW = umode->hdisplay;
139 asyh->view.iH = umode_vdisplay;
140 /* For the output mode, we can just use the stock helper. */
141 drm_mode_get_hv_timing(omode, &omode_hdisplay, &omode_vdisplay);
142 asyh->view.oW = omode_hdisplay;
143 asyh->view.oH = omode_vdisplay;
144
145 /* Add overscan compensation if necessary, will keep the aspect
146 * ratio the same as the backend mode unless overridden by the
147 * user setting both hborder and vborder properties.
148 */
149 if ((asyc->scaler.underscan.mode == UNDERSCAN_ON ||
150 (asyc->scaler.underscan.mode == UNDERSCAN_AUTO &&
151 drm_detect_hdmi_monitor(edid)))) {
152 u32 bX = asyc->scaler.underscan.hborder;
153 u32 bY = asyc->scaler.underscan.vborder;
154 u32 r = (asyh->view.oH << 19) / asyh->view.oW;
155
156 if (bX) {
157 asyh->view.oW -= (bX * 2);
158 if (bY) asyh->view.oH -= (bY * 2);
159 else asyh->view.oH = ((asyh->view.oW * r) + (r / 2)) >> 19;
160 } else {
161 asyh->view.oW -= (asyh->view.oW >> 4) + 32;
162 if (bY) asyh->view.oH -= (bY * 2);
163 else asyh->view.oH = ((asyh->view.oW * r) + (r / 2)) >> 19;
164 }
165 }
166
167 /* Handle CENTER/ASPECT scaling, taking into account the areas
168 * removed already for overscan compensation.
169 */
170 switch (mode) {
171 case DRM_MODE_SCALE_CENTER:
172 /* NOTE: This will cause scaling when the input is
173 * larger than the output.
174 */
175 asyh->view.oW = min(asyh->view.iW, asyh->view.oW);
176 asyh->view.oH = min(asyh->view.iH, asyh->view.oH);
177 break;
178 case DRM_MODE_SCALE_ASPECT:
179 /* Determine whether the scaling should be on width or on
180 * height. This is done by comparing the aspect ratios of the
181 * sizes. If the output AR is larger than input AR, that means
182 * we want to change the width (letterboxed on the
183 * left/right), otherwise on the height (letterboxed on the
184 * top/bottom).
185 *
186 * E.g. 4:3 (1.333) AR image displayed on a 16:10 (1.6) AR
187 * screen will have letterboxes on the left/right. However a
188 * 16:9 (1.777) AR image on that same screen will have
189 * letterboxes on the top/bottom.
190 *
191 * inputAR = iW / iH; outputAR = oW / oH
192 * outputAR > inputAR is equivalent to oW * iH > iW * oH
193 */
194 if (asyh->view.oW * asyh->view.iH > asyh->view.iW * asyh->view.oH) {
195 /* Recompute output width, i.e. left/right letterbox */
196 u32 r = (asyh->view.iW << 19) / asyh->view.iH;
197 asyh->view.oW = ((asyh->view.oH * r) + (r / 2)) >> 19;
198 } else {
199 /* Recompute output height, i.e. top/bottom letterbox */
200 u32 r = (asyh->view.iH << 19) / asyh->view.iW;
201 asyh->view.oH = ((asyh->view.oW * r) + (r / 2)) >> 19;
202 }
203 break;
204 default:
205 break;
206 }
207
208 asyh->set.view = true;
209}
210
211static int
212nv50_head_atomic_check_lut(struct nv50_head *head,
213 struct nv50_head_atom *asyh)
214{
215 struct nv50_disp *disp = nv50_disp(head->base.base.dev);
216 struct drm_property_blob *olut = asyh->state.gamma_lut;
217
218 /* Determine whether core output LUT should be enabled. */
219 if (olut) {
220 /* Check if any window(s) have stolen the core output LUT
221 * to as an input LUT for legacy gamma + I8 colour format.
222 */
223 if (asyh->wndw.olut) {
224 /* If any window has stolen the core output LUT,
225 * all of them must.
226 */
227 if (asyh->wndw.olut != asyh->wndw.mask)
228 return -EINVAL;
229 olut = NULL;
230 }
231 }
232
233 if (!olut && !head->func->olut_identity) {
234 asyh->olut.handle = 0;
235 return 0;
236 }
237
238 asyh->olut.handle = disp->core->chan.vram.handle;
239 asyh->olut.buffer = !asyh->olut.buffer;
240 head->func->olut(head, asyh);
241 return 0;
242}
243
244static void
245nv50_head_atomic_check_mode(struct nv50_head *head, struct nv50_head_atom *asyh)
246{
247 struct drm_display_mode *mode = &asyh->state.adjusted_mode;
248 struct nv50_head_mode *m = &asyh->mode;
249 u32 blankus;
250
251 drm_mode_set_crtcinfo(mode, CRTC_INTERLACE_HALVE_V | CRTC_STEREO_DOUBLE);
252
253 /*
254 * DRM modes are defined in terms of a repeating interval
255 * starting with the active display area. The hardware modes
256 * are defined in terms of a repeating interval starting one
257 * unit (pixel or line) into the sync pulse. So, add bias.
258 */
259
260 m->h.active = mode->crtc_htotal;
261 m->h.synce = mode->crtc_hsync_end - mode->crtc_hsync_start - 1;
262 m->h.blanke = mode->crtc_hblank_end - mode->crtc_hsync_start - 1;
263 m->h.blanks = m->h.blanke + mode->crtc_hdisplay;
264
265 m->v.active = mode->crtc_vtotal;
266 m->v.synce = mode->crtc_vsync_end - mode->crtc_vsync_start - 1;
267 m->v.blanke = mode->crtc_vblank_end - mode->crtc_vsync_start - 1;
268 m->v.blanks = m->v.blanke + mode->crtc_vdisplay;
269
270 /*XXX: Safe underestimate, even "0" works */
271 blankus = (m->v.active - mode->crtc_vdisplay - 2) * m->h.active;
272 blankus *= 1000;
273 blankus /= mode->crtc_clock;
274 m->v.blankus = blankus;
275
276 if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
277 m->v.blank2e = m->v.active + m->v.blanke;
278 m->v.blank2s = m->v.blank2e + mode->crtc_vdisplay;
279 m->v.active = (m->v.active * 2) + 1;
280 m->interlace = true;
281 } else {
282 m->v.blank2e = 0;
283 m->v.blank2s = 1;
284 m->interlace = false;
285 }
286 m->clock = mode->crtc_clock;
287
288 asyh->or.nhsync = !!(mode->flags & DRM_MODE_FLAG_NHSYNC);
289 asyh->or.nvsync = !!(mode->flags & DRM_MODE_FLAG_NVSYNC);
290 asyh->set.or = head->func->or != NULL;
291 asyh->set.mode = true;
292}
293
294static int
295nv50_head_atomic_check(struct drm_crtc *crtc, struct drm_crtc_state *state)
296{
297 struct nouveau_drm *drm = nouveau_drm(crtc->dev);
298 struct nv50_head *head = nv50_head(crtc);
299 struct nv50_head_atom *armh = nv50_head_atom(crtc->state);
300 struct nv50_head_atom *asyh = nv50_head_atom(state);
301 struct nouveau_conn_atom *asyc = NULL;
302 struct drm_connector_state *conns;
303 struct drm_connector *conn;
304 int i;
305
306 NV_ATOMIC(drm, "%s atomic_check %d\n", crtc->name, asyh->state.active);
307 if (asyh->state.active) {
308 for_each_new_connector_in_state(asyh->state.state, conn, conns, i) {
309 if (conns->crtc == crtc) {
310 asyc = nouveau_conn_atom(conns);
311 break;
312 }
313 }
314
315 if (armh->state.active) {
316 if (asyc) {
317 if (asyh->state.mode_changed)
318 asyc->set.scaler = true;
319 if (armh->base.depth != asyh->base.depth)
320 asyc->set.dither = true;
321 }
322 } else {
323 if (asyc)
324 asyc->set.mask = ~0;
325 asyh->set.mask = ~0;
326 asyh->set.or = head->func->or != NULL;
327 }
328
329 if (asyh->state.mode_changed || asyh->state.connectors_changed)
330 nv50_head_atomic_check_mode(head, asyh);
331
332 if (asyh->state.color_mgmt_changed ||
333 memcmp(&armh->wndw, &asyh->wndw, sizeof(asyh->wndw))) {
334 int ret = nv50_head_atomic_check_lut(head, asyh);
335 if (ret)
336 return ret;
337
338 asyh->olut.visible = asyh->olut.handle != 0;
339 }
340
341 if (asyc) {
342 if (asyc->set.scaler)
343 nv50_head_atomic_check_view(armh, asyh, asyc);
344 if (asyc->set.dither)
345 nv50_head_atomic_check_dither(armh, asyh, asyc);
346 if (asyc->set.procamp)
347 nv50_head_atomic_check_procamp(armh, asyh, asyc);
348 }
349
350 if (head->func->core_calc) {
351 head->func->core_calc(head, asyh);
352 if (!asyh->core.visible)
353 asyh->olut.visible = false;
354 }
355
356 asyh->set.base = armh->base.cpp != asyh->base.cpp;
357 asyh->set.ovly = armh->ovly.cpp != asyh->ovly.cpp;
358 } else {
359 asyh->olut.visible = false;
360 asyh->core.visible = false;
361 asyh->curs.visible = false;
362 asyh->base.cpp = 0;
363 asyh->ovly.cpp = 0;
364 }
365
366 if (!drm_atomic_crtc_needs_modeset(&asyh->state)) {
367 if (asyh->core.visible) {
368 if (memcmp(&armh->core, &asyh->core, sizeof(asyh->core)))
369 asyh->set.core = true;
370 } else
371 if (armh->core.visible) {
372 asyh->clr.core = true;
373 }
374
375 if (asyh->curs.visible) {
376 if (memcmp(&armh->curs, &asyh->curs, sizeof(asyh->curs)))
377 asyh->set.curs = true;
378 } else
379 if (armh->curs.visible) {
380 asyh->clr.curs = true;
381 }
382
383 if (asyh->olut.visible) {
384 if (memcmp(&armh->olut, &asyh->olut, sizeof(asyh->olut)))
385 asyh->set.olut = true;
386 } else
387 if (armh->olut.visible) {
388 asyh->clr.olut = true;
389 }
390 } else {
391 asyh->clr.olut = armh->olut.visible;
392 asyh->clr.core = armh->core.visible;
393 asyh->clr.curs = armh->curs.visible;
394 asyh->set.olut = asyh->olut.visible;
395 asyh->set.core = asyh->core.visible;
396 asyh->set.curs = asyh->curs.visible;
397 }
398
399 if (asyh->clr.mask || asyh->set.mask)
400 nv50_atom(asyh->state.state)->lock_core = true;
401 return 0;
402}
403
404static const struct drm_crtc_helper_funcs
405nv50_head_help = {
406 .atomic_check = nv50_head_atomic_check,
407};
408
409static void
410nv50_head_atomic_destroy_state(struct drm_crtc *crtc,
411 struct drm_crtc_state *state)
412{
413 struct nv50_head_atom *asyh = nv50_head_atom(state);
414 __drm_atomic_helper_crtc_destroy_state(&asyh->state);
415 kfree(asyh);
416}
417
418static struct drm_crtc_state *
419nv50_head_atomic_duplicate_state(struct drm_crtc *crtc)
420{
421 struct nv50_head_atom *armh = nv50_head_atom(crtc->state);
422 struct nv50_head_atom *asyh;
423 if (!(asyh = kmalloc(sizeof(*asyh), GFP_KERNEL)))
424 return NULL;
425 __drm_atomic_helper_crtc_duplicate_state(crtc, &asyh->state);
426 asyh->wndw = armh->wndw;
427 asyh->view = armh->view;
428 asyh->mode = armh->mode;
429 asyh->olut = armh->olut;
430 asyh->core = armh->core;
431 asyh->curs = armh->curs;
432 asyh->base = armh->base;
433 asyh->ovly = armh->ovly;
434 asyh->dither = armh->dither;
435 asyh->procamp = armh->procamp;
436 asyh->or = armh->or;
437 asyh->dp = armh->dp;
438 asyh->clr.mask = 0;
439 asyh->set.mask = 0;
440 return &asyh->state;
441}
442
443static void
444nv50_head_reset(struct drm_crtc *crtc)
445{
446 struct nv50_head_atom *asyh;
447
448 if (WARN_ON(!(asyh = kzalloc(sizeof(*asyh), GFP_KERNEL))))
449 return;
450
451 if (crtc->state)
452 nv50_head_atomic_destroy_state(crtc, crtc->state);
453
454 __drm_atomic_helper_crtc_reset(crtc, &asyh->state);
455}
456
457static void
458nv50_head_destroy(struct drm_crtc *crtc)
459{
460 struct nv50_head *head = nv50_head(crtc);
461 nv50_lut_fini(&head->olut);
462 drm_crtc_cleanup(crtc);
463 kfree(head);
464}
465
466static const struct drm_crtc_funcs
467nv50_head_func = {
468 .reset = nv50_head_reset,
469 .gamma_set = drm_atomic_helper_legacy_gamma_set,
470 .destroy = nv50_head_destroy,
471 .set_config = drm_atomic_helper_set_config,
472 .page_flip = drm_atomic_helper_page_flip,
473 .atomic_duplicate_state = nv50_head_atomic_duplicate_state,
474 .atomic_destroy_state = nv50_head_atomic_destroy_state,
475};
476
477int
478nv50_head_create(struct drm_device *dev, int index)
479{
480 struct nouveau_drm *drm = nouveau_drm(dev);
481 struct nv50_disp *disp = nv50_disp(dev);
482 struct nv50_head *head;
483 struct nv50_wndw *base, *ovly, *curs;
484 struct drm_crtc *crtc;
485 int ret;
486
487 head = kzalloc(sizeof(*head), GFP_KERNEL);
488 if (!head)
489 return -ENOMEM;
490
491 head->func = disp->core->func->head;
492 head->base.index = index;
493
494 if (disp->disp->object.oclass < GV100_DISP) {
495 ret = nv50_base_new(drm, head->base.index, &base);
496 ret = nv50_ovly_new(drm, head->base.index, &ovly);
497 } else {
498 ret = nv50_wndw_new(drm, DRM_PLANE_TYPE_PRIMARY,
499 head->base.index * 2 + 0, &base);
500 ret = nv50_wndw_new(drm, DRM_PLANE_TYPE_OVERLAY,
501 head->base.index * 2 + 1, &ovly);
502 }
503 if (ret == 0)
504 ret = nv50_curs_new(drm, head->base.index, &curs);
505 if (ret) {
506 kfree(head);
507 return ret;
508 }
509
510 crtc = &head->base.base;
511 drm_crtc_init_with_planes(dev, crtc, &base->plane, &curs->plane,
512 &nv50_head_func, "head-%d", head->base.index);
513 drm_crtc_helper_add(crtc, &nv50_head_help);
514 drm_mode_crtc_set_gamma_size(crtc, 256);
515 if (disp->disp->object.oclass >= GF110_DISP)
516 drm_crtc_enable_color_mgmt(crtc, 256, true, 256);
517 else
518 drm_crtc_enable_color_mgmt(crtc, 0, false, 256);
519
520 if (head->func->olut_set) {
521 ret = nv50_lut_init(disp, &drm->client.mmu, &head->olut);
522 if (ret)
523 goto out;
524 }
525
526out:
527 if (ret)
528 nv50_head_destroy(crtc);
529 return ret;
530}