1/* SPDX-License-Identifier: GPL-2.0-or-later */
  2/*
  3 * Copyright (C) 2010 Juergen Beisert, Pengutronix
  4 * Copyright (C) 2016 Marek Vasut <marex@denx.de>
  5 *
  6 * i.MX23/i.MX28/i.MX6SX MXSFB LCD controller driver.
  7 */
  8
  9#ifndef __MXSFB_REGS_H__
 10#define __MXSFB_REGS_H__
 11
 12#define REG_SET	4
 13#define REG_CLR	8
 14
 15#define LCDC_CTRL			0x00
 16#define LCDC_CTRL1			0x10
 17#define LCDC_V3_TRANSFER_COUNT		0x20
 18#define LCDC_V4_TRANSFER_COUNT		0x30
 19#define LCDC_V4_CUR_BUF			0x40
 20#define LCDC_V4_NEXT_BUF		0x50
 21#define LCDC_V3_CUR_BUF			0x30
 22#define LCDC_V3_NEXT_BUF		0x40
 23#define LCDC_VDCTRL0			0x70
 24#define LCDC_VDCTRL1			0x80
 25#define LCDC_VDCTRL2			0x90
 26#define LCDC_VDCTRL3			0xa0
 27#define LCDC_VDCTRL4			0xb0
 28#define LCDC_V4_DEBUG0			0x1d0
 29#define LCDC_V3_DEBUG0			0x1f0
 30
 31#define CTRL_SFTRST			(1 << 31)
 32#define CTRL_CLKGATE			(1 << 30)
 33#define CTRL_BYPASS_COUNT		(1 << 19)
 34#define CTRL_VSYNC_MODE			(1 << 18)
 35#define CTRL_DOTCLK_MODE		(1 << 17)
 36#define CTRL_DATA_SELECT		(1 << 16)
 37#define CTRL_SET_BUS_WIDTH(x)		(((x) & 0x3) << 10)
 38#define CTRL_GET_BUS_WIDTH(x)		(((x) >> 10) & 0x3)
 39#define CTRL_BUS_WIDTH_MASK		(0x3 << 10)
 40#define CTRL_SET_WORD_LENGTH(x)		(((x) & 0x3) << 8)
 41#define CTRL_GET_WORD_LENGTH(x)		(((x) >> 8) & 0x3)
 42#define CTRL_MASTER			(1 << 5)
 43#define CTRL_DF16			(1 << 3)
 44#define CTRL_DF18			(1 << 2)
 45#define CTRL_DF24			(1 << 1)
 46#define CTRL_RUN			(1 << 0)
 47
 48#define CTRL1_FIFO_CLEAR		(1 << 21)
 49#define CTRL1_SET_BYTE_PACKAGING(x)	(((x) & 0xf) << 16)
 50#define CTRL1_GET_BYTE_PACKAGING(x)	(((x) >> 16) & 0xf)
 51#define CTRL1_CUR_FRAME_DONE_IRQ_EN	(1 << 13)
 52#define CTRL1_CUR_FRAME_DONE_IRQ	(1 << 9)
 53
 54#define TRANSFER_COUNT_SET_VCOUNT(x)	(((x) & 0xffff) << 16)
 55#define TRANSFER_COUNT_GET_VCOUNT(x)	(((x) >> 16) & 0xffff)
 56#define TRANSFER_COUNT_SET_HCOUNT(x)	((x) & 0xffff)
 57#define TRANSFER_COUNT_GET_HCOUNT(x)	((x) & 0xffff)
 58
 59#define VDCTRL0_ENABLE_PRESENT		(1 << 28)
 60#define VDCTRL0_VSYNC_ACT_HIGH		(1 << 27)
 61#define VDCTRL0_HSYNC_ACT_HIGH		(1 << 26)
 62#define VDCTRL0_DOTCLK_ACT_FALLING	(1 << 25)
 63#define VDCTRL0_ENABLE_ACT_HIGH		(1 << 24)
 64#define VDCTRL0_VSYNC_PERIOD_UNIT	(1 << 21)
 65#define VDCTRL0_VSYNC_PULSE_WIDTH_UNIT	(1 << 20)
 66#define VDCTRL0_HALF_LINE		(1 << 19)
 67#define VDCTRL0_HALF_LINE_MODE		(1 << 18)
 68#define VDCTRL0_SET_VSYNC_PULSE_WIDTH(x) ((x) & 0x3ffff)
 69#define VDCTRL0_GET_VSYNC_PULSE_WIDTH(x) ((x) & 0x3ffff)
 70
 71#define VDCTRL2_SET_HSYNC_PERIOD(x)	((x) & 0x3ffff)
 72#define VDCTRL2_GET_HSYNC_PERIOD(x)	((x) & 0x3ffff)
 73
 74#define VDCTRL3_MUX_SYNC_SIGNALS	(1 << 29)
 75#define VDCTRL3_VSYNC_ONLY		(1 << 28)
 76#define SET_HOR_WAIT_CNT(x)		(((x) & 0xfff) << 16)
 77#define GET_HOR_WAIT_CNT(x)		(((x) >> 16) & 0xfff)
 78#define SET_VERT_WAIT_CNT(x)		((x) & 0xffff)
 79#define GET_VERT_WAIT_CNT(x)		((x) & 0xffff)
 80
 81#define VDCTRL4_SET_DOTCLK_DLY(x)	(((x) & 0x7) << 29) /* v4 only */
 82#define VDCTRL4_GET_DOTCLK_DLY(x)	(((x) >> 29) & 0x7) /* v4 only */
 83#define VDCTRL4_SYNC_SIGNALS_ON		(1 << 18)
 84#define SET_DOTCLK_H_VALID_DATA_CNT(x)	((x) & 0x3ffff)
 85
 86#define DEBUG0_HSYNC			(1 < 26)
 87#define DEBUG0_VSYNC			(1 < 25)
 88
 89#define MXSFB_MIN_XRES			120
 90#define MXSFB_MIN_YRES			120
 91#define MXSFB_MAX_XRES			0xffff
 92#define MXSFB_MAX_YRES			0xffff
 93
 94#define RED 0
 95#define GREEN 1
 96#define BLUE 2
 97#define TRANSP 3
 98
 99#define STMLCDIF_8BIT  1 /* pixel data bus to the display is of 8 bit width */
100#define STMLCDIF_16BIT 0 /* pixel data bus to the display is of 16 bit width */
101#define STMLCDIF_18BIT 2 /* pixel data bus to the display is of 18 bit width */
102#define STMLCDIF_24BIT 3 /* pixel data bus to the display is of 24 bit width */
103
104#define MXSFB_SYNC_DATA_ENABLE_HIGH_ACT	(1 << 6)
105#define MXSFB_SYNC_DOTCLK_FALLING_ACT	(1 << 7) /* negative edge sampling */
106
107#endif /* __MXSFB_REGS_H__ */