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1// SPDX-License-Identifier: GPL-2.0+
2#include <linux/clk.h>
3#include <linux/component.h>
4#include <linux/delay.h>
5#include <linux/io.h>
6#include <linux/mfd/syscon.h>
7#include <linux/module.h>
8#include <linux/of.h>
9#include <linux/platform_device.h>
10#include <linux/regmap.h>
11#include <linux/regulator/consumer.h>
12#include <video/mipi_display.h>
13
14#include <drm/drm_atomic_helper.h>
15#include <drm/drm_bridge.h>
16#include <drm/drm_device.h>
17#include <drm/drm_drv.h>
18#include <drm/drm_encoder.h>
19#include <drm/drm_mipi_dsi.h>
20#include <drm/drm_modeset_helper_vtables.h>
21#include <drm/drm_of.h>
22#include <drm/drm_panel.h>
23#include <drm/drm_print.h>
24#include <drm/drm_probe_helper.h>
25
26#include "mcde_drm.h"
27#include "mcde_dsi_regs.h"
28
29#define DSI_DEFAULT_LP_FREQ_HZ 19200000
30#define DSI_DEFAULT_HS_FREQ_HZ 420160000
31
32/* PRCMU DSI reset registers */
33#define PRCM_DSI_SW_RESET 0x324
34#define PRCM_DSI_SW_RESET_DSI0_SW_RESETN BIT(0)
35#define PRCM_DSI_SW_RESET_DSI1_SW_RESETN BIT(1)
36#define PRCM_DSI_SW_RESET_DSI2_SW_RESETN BIT(2)
37
38struct mcde_dsi {
39 struct device *dev;
40 struct mcde *mcde;
41 struct drm_bridge bridge;
42 struct drm_connector connector;
43 struct drm_panel *panel;
44 struct drm_bridge *bridge_out;
45 struct mipi_dsi_host dsi_host;
46 struct mipi_dsi_device *mdsi;
47 struct clk *hs_clk;
48 struct clk *lp_clk;
49 unsigned long hs_freq;
50 unsigned long lp_freq;
51 bool unused;
52
53 void __iomem *regs;
54 struct regmap *prcmu;
55};
56
57static inline struct mcde_dsi *bridge_to_mcde_dsi(struct drm_bridge *bridge)
58{
59 return container_of(bridge, struct mcde_dsi, bridge);
60}
61
62static inline struct mcde_dsi *host_to_mcde_dsi(struct mipi_dsi_host *h)
63{
64 return container_of(h, struct mcde_dsi, dsi_host);
65}
66
67static inline struct mcde_dsi *connector_to_mcde_dsi(struct drm_connector *c)
68{
69 return container_of(c, struct mcde_dsi, connector);
70}
71
72bool mcde_dsi_irq(struct mipi_dsi_device *mdsi)
73{
74 struct mcde_dsi *d;
75 u32 val;
76 bool te_received = false;
77
78 d = host_to_mcde_dsi(mdsi->host);
79
80 dev_dbg(d->dev, "%s called\n", __func__);
81
82 val = readl(d->regs + DSI_DIRECT_CMD_STS_FLAG);
83 if (val)
84 dev_dbg(d->dev, "DSI_DIRECT_CMD_STS_FLAG = %08x\n", val);
85 if (val & DSI_DIRECT_CMD_STS_WRITE_COMPLETED)
86 dev_dbg(d->dev, "direct command write completed\n");
87 if (val & DSI_DIRECT_CMD_STS_TE_RECEIVED) {
88 te_received = true;
89 dev_dbg(d->dev, "direct command TE received\n");
90 }
91 if (val & DSI_DIRECT_CMD_STS_ACKNOWLEDGE_WITH_ERR_RECEIVED)
92 dev_err(d->dev, "direct command ACK ERR received\n");
93 if (val & DSI_DIRECT_CMD_STS_READ_COMPLETED_WITH_ERR)
94 dev_err(d->dev, "direct command read ERR received\n");
95 /* Mask off the ACK value and clear status */
96 writel(val, d->regs + DSI_DIRECT_CMD_STS_CLR);
97
98 val = readl(d->regs + DSI_CMD_MODE_STS_FLAG);
99 if (val)
100 dev_dbg(d->dev, "DSI_CMD_MODE_STS_FLAG = %08x\n", val);
101 if (val & DSI_CMD_MODE_STS_ERR_NO_TE)
102 /* This happens all the time (safe to ignore) */
103 dev_dbg(d->dev, "CMD mode no TE\n");
104 if (val & DSI_CMD_MODE_STS_ERR_TE_MISS)
105 /* This happens all the time (safe to ignore) */
106 dev_dbg(d->dev, "CMD mode TE miss\n");
107 if (val & DSI_CMD_MODE_STS_ERR_SDI1_UNDERRUN)
108 dev_err(d->dev, "CMD mode SD1 underrun\n");
109 if (val & DSI_CMD_MODE_STS_ERR_SDI2_UNDERRUN)
110 dev_err(d->dev, "CMD mode SD2 underrun\n");
111 if (val & DSI_CMD_MODE_STS_ERR_UNWANTED_RD)
112 dev_err(d->dev, "CMD mode unwanted RD\n");
113 writel(val, d->regs + DSI_CMD_MODE_STS_CLR);
114
115 val = readl(d->regs + DSI_DIRECT_CMD_RD_STS_FLAG);
116 if (val)
117 dev_dbg(d->dev, "DSI_DIRECT_CMD_RD_STS_FLAG = %08x\n", val);
118 writel(val, d->regs + DSI_DIRECT_CMD_RD_STS_CLR);
119
120 val = readl(d->regs + DSI_TG_STS_FLAG);
121 if (val)
122 dev_dbg(d->dev, "DSI_TG_STS_FLAG = %08x\n", val);
123 writel(val, d->regs + DSI_TG_STS_CLR);
124
125 val = readl(d->regs + DSI_VID_MODE_STS_FLAG);
126 if (val)
127 dev_err(d->dev, "some video mode error status\n");
128 writel(val, d->regs + DSI_VID_MODE_STS_CLR);
129
130 return te_received;
131}
132
133static int mcde_dsi_host_attach(struct mipi_dsi_host *host,
134 struct mipi_dsi_device *mdsi)
135{
136 struct mcde_dsi *d = host_to_mcde_dsi(host);
137
138 if (mdsi->lanes < 1 || mdsi->lanes > 2) {
139 DRM_ERROR("dsi device params invalid, 1 or 2 lanes supported\n");
140 return -EINVAL;
141 }
142
143 dev_info(d->dev, "attached DSI device with %d lanes\n", mdsi->lanes);
144 /* MIPI_DSI_FMT_RGB88 etc */
145 dev_info(d->dev, "format %08x, %dbpp\n", mdsi->format,
146 mipi_dsi_pixel_format_to_bpp(mdsi->format));
147 dev_info(d->dev, "mode flags: %08lx\n", mdsi->mode_flags);
148
149 d->mdsi = mdsi;
150 if (d->mcde)
151 d->mcde->mdsi = mdsi;
152
153 return 0;
154}
155
156static int mcde_dsi_host_detach(struct mipi_dsi_host *host,
157 struct mipi_dsi_device *mdsi)
158{
159 struct mcde_dsi *d = host_to_mcde_dsi(host);
160
161 d->mdsi = NULL;
162 if (d->mcde)
163 d->mcde->mdsi = NULL;
164
165 return 0;
166}
167
168#define MCDE_DSI_HOST_IS_READ(type) \
169 ((type == MIPI_DSI_GENERIC_READ_REQUEST_0_PARAM) || \
170 (type == MIPI_DSI_GENERIC_READ_REQUEST_1_PARAM) || \
171 (type == MIPI_DSI_GENERIC_READ_REQUEST_2_PARAM) || \
172 (type == MIPI_DSI_DCS_READ))
173
174static ssize_t mcde_dsi_host_transfer(struct mipi_dsi_host *host,
175 const struct mipi_dsi_msg *msg)
176{
177 struct mcde_dsi *d = host_to_mcde_dsi(host);
178 const u32 loop_delay_us = 10; /* us */
179 const u8 *tx = msg->tx_buf;
180 u32 loop_counter;
181 size_t txlen = msg->tx_len;
182 size_t rxlen = msg->rx_len;
183 u32 val;
184 int ret;
185 int i;
186
187 if (txlen > 16) {
188 dev_err(d->dev,
189 "dunno how to write more than 16 bytes yet\n");
190 return -EIO;
191 }
192 if (rxlen > 4) {
193 dev_err(d->dev,
194 "dunno how to read more than 4 bytes yet\n");
195 return -EIO;
196 }
197
198 dev_dbg(d->dev,
199 "message to channel %d, write %zd bytes read %zd bytes\n",
200 msg->channel, txlen, rxlen);
201
202 /* Command "nature" */
203 if (MCDE_DSI_HOST_IS_READ(msg->type))
204 /* MCTL_MAIN_DATA_CTL already set up */
205 val = DSI_DIRECT_CMD_MAIN_SETTINGS_CMD_NAT_READ;
206 else
207 val = DSI_DIRECT_CMD_MAIN_SETTINGS_CMD_NAT_WRITE;
208 /*
209 * More than 2 bytes will not fit in a single packet, so it's
210 * time to set the "long not short" bit. One byte is used by
211 * the MIPI DCS command leaving just one byte for the payload
212 * in a short package.
213 */
214 if (mipi_dsi_packet_format_is_long(msg->type))
215 val |= DSI_DIRECT_CMD_MAIN_SETTINGS_CMD_LONGNOTSHORT;
216 val |= 0 << DSI_DIRECT_CMD_MAIN_SETTINGS_CMD_ID_SHIFT;
217 val |= txlen << DSI_DIRECT_CMD_MAIN_SETTINGS_CMD_SIZE_SHIFT;
218 val |= DSI_DIRECT_CMD_MAIN_SETTINGS_CMD_LP_EN;
219 val |= msg->type << DSI_DIRECT_CMD_MAIN_SETTINGS_CMD_HEAD_SHIFT;
220 writel(val, d->regs + DSI_DIRECT_CMD_MAIN_SETTINGS);
221
222 /* MIPI DCS command is part of the data */
223 if (txlen > 0) {
224 val = 0;
225 for (i = 0; i < 4 && i < txlen; i++)
226 val |= tx[i] << (i & 3) * 8;
227 }
228 writel(val, d->regs + DSI_DIRECT_CMD_WRDAT0);
229 if (txlen > 4) {
230 val = 0;
231 for (i = 0; i < 4 && (i + 4) < txlen; i++)
232 val |= tx[i + 4] << (i & 3) * 8;
233 writel(val, d->regs + DSI_DIRECT_CMD_WRDAT1);
234 }
235 if (txlen > 8) {
236 val = 0;
237 for (i = 0; i < 4 && (i + 8) < txlen; i++)
238 val |= tx[i + 8] << (i & 3) * 8;
239 writel(val, d->regs + DSI_DIRECT_CMD_WRDAT2);
240 }
241 if (txlen > 12) {
242 val = 0;
243 for (i = 0; i < 4 && (i + 12) < txlen; i++)
244 val |= tx[i + 12] << (i & 3) * 8;
245 writel(val, d->regs + DSI_DIRECT_CMD_WRDAT3);
246 }
247
248 writel(~0, d->regs + DSI_DIRECT_CMD_STS_CLR);
249 writel(~0, d->regs + DSI_CMD_MODE_STS_CLR);
250 /* Send command */
251 writel(1, d->regs + DSI_DIRECT_CMD_SEND);
252
253 loop_counter = 1000 * 1000 / loop_delay_us;
254 if (MCDE_DSI_HOST_IS_READ(msg->type)) {
255 /* Read command */
256 while (!(readl(d->regs + DSI_DIRECT_CMD_STS) &
257 (DSI_DIRECT_CMD_STS_READ_COMPLETED |
258 DSI_DIRECT_CMD_STS_READ_COMPLETED_WITH_ERR))
259 && --loop_counter)
260 usleep_range(loop_delay_us, (loop_delay_us * 3) / 2);
261 if (!loop_counter) {
262 dev_err(d->dev, "DSI read timeout!\n");
263 return -ETIME;
264 }
265 } else {
266 /* Writing only */
267 while (!(readl(d->regs + DSI_DIRECT_CMD_STS) &
268 DSI_DIRECT_CMD_STS_WRITE_COMPLETED)
269 && --loop_counter)
270 usleep_range(loop_delay_us, (loop_delay_us * 3) / 2);
271
272 if (!loop_counter) {
273 dev_err(d->dev, "DSI write timeout!\n");
274 return -ETIME;
275 }
276 }
277
278 val = readl(d->regs + DSI_DIRECT_CMD_STS);
279 if (val & DSI_DIRECT_CMD_STS_READ_COMPLETED_WITH_ERR) {
280 dev_err(d->dev, "read completed with error\n");
281 writel(1, d->regs + DSI_DIRECT_CMD_RD_INIT);
282 return -EIO;
283 }
284 if (val & DSI_DIRECT_CMD_STS_ACKNOWLEDGE_WITH_ERR_RECEIVED) {
285 val >>= DSI_DIRECT_CMD_STS_ACK_VAL_SHIFT;
286 dev_err(d->dev, "error during transmission: %04x\n",
287 val);
288 return -EIO;
289 }
290
291 if (!MCDE_DSI_HOST_IS_READ(msg->type)) {
292 /* Return number of bytes written */
293 ret = txlen;
294 } else {
295 /* OK this is a read command, get the response */
296 u32 rdsz;
297 u32 rddat;
298 u8 *rx = msg->rx_buf;
299
300 rdsz = readl(d->regs + DSI_DIRECT_CMD_RD_PROPERTY);
301 rdsz &= DSI_DIRECT_CMD_RD_PROPERTY_RD_SIZE_MASK;
302 rddat = readl(d->regs + DSI_DIRECT_CMD_RDDAT);
303 if (rdsz < rxlen) {
304 dev_err(d->dev, "read error, requested %zd got %d\n",
305 rxlen, rdsz);
306 return -EIO;
307 }
308 /* FIXME: read more than 4 bytes */
309 for (i = 0; i < 4 && i < rxlen; i++)
310 rx[i] = (rddat >> (i * 8)) & 0xff;
311 ret = rdsz;
312 }
313
314 writel(~0, d->regs + DSI_DIRECT_CMD_STS_CLR);
315 writel(~0, d->regs + DSI_CMD_MODE_STS_CLR);
316
317 return ret;
318}
319
320static const struct mipi_dsi_host_ops mcde_dsi_host_ops = {
321 .attach = mcde_dsi_host_attach,
322 .detach = mcde_dsi_host_detach,
323 .transfer = mcde_dsi_host_transfer,
324};
325
326/* This sends a direct (short) command to request TE */
327void mcde_dsi_te_request(struct mipi_dsi_device *mdsi)
328{
329 struct mcde_dsi *d;
330 u32 val;
331
332 d = host_to_mcde_dsi(mdsi->host);
333
334 /* Command "nature" TE request */
335 val = DSI_DIRECT_CMD_MAIN_SETTINGS_CMD_NAT_TE_REQ;
336 val |= 0 << DSI_DIRECT_CMD_MAIN_SETTINGS_CMD_ID_SHIFT;
337 val |= 2 << DSI_DIRECT_CMD_MAIN_SETTINGS_CMD_SIZE_SHIFT;
338 val |= DSI_DIRECT_CMD_MAIN_SETTINGS_CMD_LP_EN;
339 val |= DSI_DIRECT_CMD_MAIN_SETTINGS_CMD_HEAD_DCS_SHORT_WRITE_1 <<
340 DSI_DIRECT_CMD_MAIN_SETTINGS_CMD_HEAD_SHIFT;
341 writel(val, d->regs + DSI_DIRECT_CMD_MAIN_SETTINGS);
342
343 /* Clear TE reveived and error status bits and enables them */
344 writel(DSI_DIRECT_CMD_STS_CLR_TE_RECEIVED_CLR |
345 DSI_DIRECT_CMD_STS_CLR_ACKNOWLEDGE_WITH_ERR_RECEIVED_CLR,
346 d->regs + DSI_DIRECT_CMD_STS_CLR);
347 val = readl(d->regs + DSI_DIRECT_CMD_STS_CTL);
348 val |= DSI_DIRECT_CMD_STS_CTL_TE_RECEIVED_EN;
349 val |= DSI_DIRECT_CMD_STS_CTL_ACKNOWLEDGE_WITH_ERR_EN;
350 writel(val, d->regs + DSI_DIRECT_CMD_STS_CTL);
351
352 /* Clear and enable no TE or TE missing status */
353 writel(DSI_CMD_MODE_STS_CLR_ERR_NO_TE_CLR |
354 DSI_CMD_MODE_STS_CLR_ERR_TE_MISS_CLR,
355 d->regs + DSI_CMD_MODE_STS_CLR);
356 val = readl(d->regs + DSI_CMD_MODE_STS_CTL);
357 val |= DSI_CMD_MODE_STS_CTL_ERR_NO_TE_EN;
358 val |= DSI_CMD_MODE_STS_CTL_ERR_TE_MISS_EN;
359 writel(val, d->regs + DSI_CMD_MODE_STS_CTL);
360
361 /* Send this TE request command */
362 writel(1, d->regs + DSI_DIRECT_CMD_SEND);
363}
364
365static void mcde_dsi_setup_video_mode(struct mcde_dsi *d,
366 const struct drm_display_mode *mode)
367{
368 u8 bpp = mipi_dsi_pixel_format_to_bpp(d->mdsi->format);
369 u64 bpl;
370 u32 hfp;
371 u32 hbp;
372 u32 hsa;
373 u32 blkline_pck, line_duration;
374 u32 blkeol_pck, blkeol_duration;
375 u32 val;
376
377 val = 0;
378 if (d->mdsi->mode_flags & MIPI_DSI_MODE_VIDEO_BURST)
379 val |= DSI_VID_MAIN_CTL_BURST_MODE;
380 if (d->mdsi->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE) {
381 val |= DSI_VID_MAIN_CTL_SYNC_PULSE_ACTIVE;
382 val |= DSI_VID_MAIN_CTL_SYNC_PULSE_HORIZONTAL;
383 }
384 /* RGB header and pixel mode */
385 switch (d->mdsi->format) {
386 case MIPI_DSI_FMT_RGB565:
387 val |= MIPI_DSI_PACKED_PIXEL_STREAM_16 <<
388 DSI_VID_MAIN_CTL_HEADER_SHIFT;
389 val |= DSI_VID_MAIN_CTL_VID_PIXEL_MODE_16BITS;
390 break;
391 case MIPI_DSI_FMT_RGB666_PACKED:
392 val |= MIPI_DSI_PACKED_PIXEL_STREAM_18 <<
393 DSI_VID_MAIN_CTL_HEADER_SHIFT;
394 val |= DSI_VID_MAIN_CTL_VID_PIXEL_MODE_18BITS;
395 break;
396 case MIPI_DSI_FMT_RGB666:
397 val |= MIPI_DSI_PIXEL_STREAM_3BYTE_18
398 << DSI_VID_MAIN_CTL_HEADER_SHIFT;
399 val |= DSI_VID_MAIN_CTL_VID_PIXEL_MODE_18BITS_LOOSE;
400 break;
401 case MIPI_DSI_FMT_RGB888:
402 val |= MIPI_DSI_PACKED_PIXEL_STREAM_24 <<
403 DSI_VID_MAIN_CTL_HEADER_SHIFT;
404 val |= DSI_VID_MAIN_CTL_VID_PIXEL_MODE_24BITS;
405 break;
406 default:
407 dev_err(d->dev, "unknown pixel mode\n");
408 return;
409 }
410
411 /* TODO: TVG could be enabled here */
412
413 /* Send blanking packet */
414 val |= DSI_VID_MAIN_CTL_REG_BLKLINE_MODE_LP_0;
415 /* Send EOL packet */
416 val |= DSI_VID_MAIN_CTL_REG_BLKEOL_MODE_LP_0;
417 /* Recovery mode 1 */
418 val |= 1 << DSI_VID_MAIN_CTL_RECOVERY_MODE_SHIFT;
419 /* All other fields zero */
420 writel(val, d->regs + DSI_VID_MAIN_CTL);
421
422 /* Vertical frame parameters are pretty straight-forward */
423 val = mode->vdisplay << DSI_VID_VSIZE_VSA_LENGTH_SHIFT;
424 /* vertical front porch */
425 val |= (mode->vsync_start - mode->vdisplay)
426 << DSI_VID_VSIZE_VFP_LENGTH_SHIFT;
427 /* vertical sync active */
428 val |= (mode->vsync_end - mode->vsync_start)
429 << DSI_VID_VSIZE_VACT_LENGTH_SHIFT;
430 /* vertical back porch */
431 val |= (mode->vtotal - mode->vsync_end)
432 << DSI_VID_VSIZE_VBP_LENGTH_SHIFT;
433 writel(val, d->regs + DSI_VID_VSIZE);
434
435 /*
436 * Horizontal frame parameters:
437 * horizontal resolution is given in pixels and must be re-calculated
438 * into bytes since this is what the hardware expects.
439 *
440 * 6 + 2 is HFP header + checksum
441 */
442 hfp = (mode->hsync_start - mode->hdisplay) * bpp - 6 - 2;
443 if (d->mdsi->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE) {
444 /*
445 * 6 is HBP header + checksum
446 * 4 is RGB header + checksum
447 */
448 hbp = (mode->htotal - mode->hsync_end) * bpp - 4 - 6;
449 /*
450 * 6 is HBP header + checksum
451 * 4 is HSW packet bytes
452 * 4 is RGB header + checksum
453 */
454 hsa = (mode->hsync_end - mode->hsync_start) * bpp - 4 - 4 - 6;
455 } else {
456 /*
457 * HBP includes both back porch and sync
458 * 6 is HBP header + checksum
459 * 4 is HSW packet bytes
460 * 4 is RGB header + checksum
461 */
462 hbp = (mode->htotal - mode->hsync_start) * bpp - 4 - 4 - 6;
463 /* HSA is not considered in this mode and set to 0 */
464 hsa = 0;
465 }
466 dev_dbg(d->dev, "hfp: %u, hbp: %u, hsa: %u\n",
467 hfp, hbp, hsa);
468
469 /* Frame parameters: horizontal sync active */
470 val = hsa << DSI_VID_HSIZE1_HSA_LENGTH_SHIFT;
471 /* horizontal back porch */
472 val |= hbp << DSI_VID_HSIZE1_HBP_LENGTH_SHIFT;
473 /* horizontal front porch */
474 val |= hfp << DSI_VID_HSIZE1_HFP_LENGTH_SHIFT;
475 writel(val, d->regs + DSI_VID_HSIZE1);
476
477 /* RGB data length (bytes on one scanline) */
478 val = mode->hdisplay * (bpp / 8);
479 writel(val, d->regs + DSI_VID_HSIZE2);
480
481 /* TODO: further adjustments for TVG mode here */
482
483 /*
484 * EOL packet length from bits per line calculations: pixel clock
485 * is given in kHz, calculate the time between two pixels in
486 * picoseconds.
487 */
488 bpl = mode->clock * mode->htotal;
489 bpl *= (d->hs_freq / 8);
490 do_div(bpl, 1000000); /* microseconds */
491 do_div(bpl, 1000000); /* seconds */
492 bpl *= d->mdsi->lanes;
493 dev_dbg(d->dev, "calculated bytes per line: %llu\n", bpl);
494 /*
495 * 6 is header + checksum, header = 4 bytes, checksum = 2 bytes
496 * 4 is short packet for vsync/hsync
497 */
498 if (d->mdsi->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE) {
499 /* Fixme: isn't the hsync width in pixels? */
500 blkline_pck = bpl - (mode->hsync_end - mode->hsync_start) - 6;
501 val = blkline_pck << DSI_VID_BLKSIZE2_BLKLINE_PULSE_PCK_SHIFT;
502 writel(val, d->regs + DSI_VID_BLKSIZE2);
503 } else {
504 blkline_pck = bpl - 4 - 6;
505 val = blkline_pck << DSI_VID_BLKSIZE1_BLKLINE_EVENT_PCK_SHIFT;
506 writel(val, d->regs + DSI_VID_BLKSIZE1);
507 }
508
509 line_duration = (blkline_pck + 6) / d->mdsi->lanes;
510 dev_dbg(d->dev, "line duration %u\n", line_duration);
511 val = line_duration << DSI_VID_DPHY_TIME_REG_LINE_DURATION_SHIFT;
512 /*
513 * This is the time to perform LP->HS on D-PHY
514 * FIXME: nowhere to get this from: DT property on the DSI?
515 */
516 val |= 0 << DSI_VID_DPHY_TIME_REG_WAKEUP_TIME_SHIFT;
517 writel(val, d->regs + DSI_VID_DPHY_TIME);
518
519 /* Calculate block end of line */
520 blkeol_pck = bpl - mode->hdisplay * bpp - 6;
521 blkeol_duration = (blkeol_pck + 6) / d->mdsi->lanes;
522 dev_dbg(d->dev, "blkeol pck: %u, duration: %u\n",
523 blkeol_pck, blkeol_duration);
524
525 if (d->mdsi->mode_flags & MIPI_DSI_MODE_VIDEO_BURST) {
526 /* Set up EOL clock for burst mode */
527 val = readl(d->regs + DSI_VID_BLKSIZE1);
528 val |= blkeol_pck << DSI_VID_BLKSIZE1_BLKEOL_PCK_SHIFT;
529 writel(val, d->regs + DSI_VID_BLKSIZE1);
530 writel(blkeol_pck, d->regs + DSI_VID_VCA_SETTING2);
531
532 writel(blkeol_duration, d->regs + DSI_VID_PCK_TIME);
533 writel(blkeol_duration - 6, d->regs + DSI_VID_VCA_SETTING1);
534 }
535
536 /* Maximum line limit */
537 val = readl(d->regs + DSI_VID_VCA_SETTING2);
538 val |= blkline_pck <<
539 DSI_VID_VCA_SETTING2_EXACT_BURST_LIMIT_SHIFT;
540 writel(val, d->regs + DSI_VID_VCA_SETTING2);
541
542 /* Put IF1 into video mode */
543 val = readl(d->regs + DSI_MCTL_MAIN_DATA_CTL);
544 val |= DSI_MCTL_MAIN_DATA_CTL_IF1_MODE;
545 writel(val, d->regs + DSI_MCTL_MAIN_DATA_CTL);
546
547 /* Disable command mode on IF1 */
548 val = readl(d->regs + DSI_CMD_MODE_CTL);
549 val &= ~DSI_CMD_MODE_CTL_IF1_LP_EN;
550 writel(val, d->regs + DSI_CMD_MODE_CTL);
551
552 /* Enable some error interrupts */
553 val = readl(d->regs + DSI_VID_MODE_STS_CTL);
554 val |= DSI_VID_MODE_STS_CTL_ERR_MISSING_VSYNC;
555 val |= DSI_VID_MODE_STS_CTL_ERR_MISSING_DATA;
556 writel(val, d->regs + DSI_VID_MODE_STS_CTL);
557
558 /* Enable video mode */
559 val = readl(d->regs + DSI_MCTL_MAIN_DATA_CTL);
560 val |= DSI_MCTL_MAIN_DATA_CTL_VID_EN;
561 writel(val, d->regs + DSI_MCTL_MAIN_DATA_CTL);
562}
563
564static void mcde_dsi_start(struct mcde_dsi *d)
565{
566 unsigned long hs_freq;
567 u32 val;
568 int i;
569
570 /* No integration mode */
571 writel(0, d->regs + DSI_MCTL_INTEGRATION_MODE);
572
573 /* Enable the DSI port, from drivers/video/mcde/dsilink_v2.c */
574 val = DSI_MCTL_MAIN_DATA_CTL_LINK_EN |
575 DSI_MCTL_MAIN_DATA_CTL_BTA_EN |
576 DSI_MCTL_MAIN_DATA_CTL_READ_EN |
577 DSI_MCTL_MAIN_DATA_CTL_REG_TE_EN;
578 if (d->mdsi->mode_flags & MIPI_DSI_MODE_EOT_PACKET)
579 val |= DSI_MCTL_MAIN_DATA_CTL_HOST_EOT_GEN;
580 writel(val, d->regs + DSI_MCTL_MAIN_DATA_CTL);
581
582 /* Set a high command timeout, clear other fields */
583 val = 0x3ff << DSI_CMD_MODE_CTL_TE_TIMEOUT_SHIFT;
584 writel(val, d->regs + DSI_CMD_MODE_CTL);
585
586 /*
587 * UI_X4 is described as "unit interval times four"
588 * I guess since DSI packets are 4 bytes wide, one unit
589 * is one byte.
590 */
591 hs_freq = clk_get_rate(d->hs_clk);
592 hs_freq /= 1000000; /* MHz */
593 val = 4000 / hs_freq;
594 dev_dbg(d->dev, "UI value: %d\n", val);
595 val <<= DSI_MCTL_DPHY_STATIC_UI_X4_SHIFT;
596 val &= DSI_MCTL_DPHY_STATIC_UI_X4_MASK;
597 writel(val, d->regs + DSI_MCTL_DPHY_STATIC);
598
599 /*
600 * Enable clocking: 0x0f (something?) between each burst,
601 * enable the second lane if needed, enable continuous clock if
602 * needed, enable switch into ULPM (ultra-low power mode) on
603 * all the lines.
604 */
605 val = 0x0f << DSI_MCTL_MAIN_PHY_CTL_WAIT_BURST_TIME_SHIFT;
606 if (d->mdsi->lanes == 2)
607 val |= DSI_MCTL_MAIN_PHY_CTL_LANE2_EN;
608 if (!(d->mdsi->mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS))
609 val |= DSI_MCTL_MAIN_PHY_CTL_CLK_CONTINUOUS;
610 val |= DSI_MCTL_MAIN_PHY_CTL_CLK_ULPM_EN |
611 DSI_MCTL_MAIN_PHY_CTL_DAT1_ULPM_EN |
612 DSI_MCTL_MAIN_PHY_CTL_DAT2_ULPM_EN;
613 writel(val, d->regs + DSI_MCTL_MAIN_PHY_CTL);
614
615 val = (1 << DSI_MCTL_ULPOUT_TIME_CKLANE_ULPOUT_TIME_SHIFT) |
616 (1 << DSI_MCTL_ULPOUT_TIME_DATA_ULPOUT_TIME_SHIFT);
617 writel(val, d->regs + DSI_MCTL_ULPOUT_TIME);
618
619 writel(DSI_DPHY_LANES_TRIM_DPHY_SPECS_90_81B_0_90,
620 d->regs + DSI_DPHY_LANES_TRIM);
621
622 /* High PHY timeout */
623 val = (0x0f << DSI_MCTL_DPHY_TIMEOUT_CLK_DIV_SHIFT) |
624 (0x3fff << DSI_MCTL_DPHY_TIMEOUT_HSTX_TO_VAL_SHIFT) |
625 (0x3fff << DSI_MCTL_DPHY_TIMEOUT_LPRX_TO_VAL_SHIFT);
626 writel(val, d->regs + DSI_MCTL_DPHY_TIMEOUT);
627
628 val = DSI_MCTL_MAIN_EN_PLL_START |
629 DSI_MCTL_MAIN_EN_CKLANE_EN |
630 DSI_MCTL_MAIN_EN_DAT1_EN |
631 DSI_MCTL_MAIN_EN_IF1_EN;
632 if (d->mdsi->lanes == 2)
633 val |= DSI_MCTL_MAIN_EN_DAT2_EN;
634 writel(val, d->regs + DSI_MCTL_MAIN_EN);
635
636 /* Wait for the PLL to lock and the clock and data lines to come up */
637 i = 0;
638 val = DSI_MCTL_MAIN_STS_PLL_LOCK |
639 DSI_MCTL_MAIN_STS_CLKLANE_READY |
640 DSI_MCTL_MAIN_STS_DAT1_READY;
641 if (d->mdsi->lanes == 2)
642 val |= DSI_MCTL_MAIN_STS_DAT2_READY;
643 while ((readl(d->regs + DSI_MCTL_MAIN_STS) & val) != val) {
644 /* Sleep for a millisecond */
645 usleep_range(1000, 1500);
646 if (i++ == 100) {
647 dev_warn(d->dev, "DSI lanes did not start up\n");
648 return;
649 }
650 }
651
652 /* TODO needed? */
653
654 /* Command mode, clear IF1 ID */
655 val = readl(d->regs + DSI_CMD_MODE_CTL);
656 /*
657 * If we enable low-power mode here, with
658 * val |= DSI_CMD_MODE_CTL_IF1_LP_EN
659 * then display updates become really slow.
660 */
661 val &= ~DSI_CMD_MODE_CTL_IF1_ID_MASK;
662 writel(val, d->regs + DSI_CMD_MODE_CTL);
663
664 /* Wait for DSI PHY to initialize */
665 usleep_range(100, 200);
666 dev_info(d->dev, "DSI link enabled\n");
667}
668
669
670static void mcde_dsi_bridge_enable(struct drm_bridge *bridge)
671{
672 struct mcde_dsi *d = bridge_to_mcde_dsi(bridge);
673
674 dev_info(d->dev, "enable DSI master\n");
675};
676
677static void mcde_dsi_bridge_mode_set(struct drm_bridge *bridge,
678 const struct drm_display_mode *mode,
679 const struct drm_display_mode *adj)
680{
681 struct mcde_dsi *d = bridge_to_mcde_dsi(bridge);
682 unsigned long pixel_clock_hz = mode->clock * 1000;
683 unsigned long hs_freq, lp_freq;
684 u32 val;
685 int ret;
686
687 if (!d->mdsi) {
688 dev_err(d->dev, "no DSI device attached to encoder!\n");
689 return;
690 }
691
692 dev_info(d->dev, "set DSI master to %dx%d %lu Hz %s mode\n",
693 mode->hdisplay, mode->vdisplay, pixel_clock_hz,
694 (d->mdsi->mode_flags & MIPI_DSI_MODE_VIDEO) ? "VIDEO" : "CMD"
695 );
696
697 /* Copy maximum clock frequencies */
698 if (d->mdsi->lp_rate)
699 lp_freq = d->mdsi->lp_rate;
700 else
701 lp_freq = DSI_DEFAULT_LP_FREQ_HZ;
702 if (d->mdsi->hs_rate)
703 hs_freq = d->mdsi->hs_rate;
704 else
705 hs_freq = DSI_DEFAULT_HS_FREQ_HZ;
706
707 /* Enable LP (Low Power, Energy Save, ES) and HS (High Speed) clocks */
708 d->lp_freq = clk_round_rate(d->lp_clk, lp_freq);
709 ret = clk_set_rate(d->lp_clk, d->lp_freq);
710 if (ret)
711 dev_err(d->dev, "failed to set LP clock rate %lu Hz\n",
712 d->lp_freq);
713
714 d->hs_freq = clk_round_rate(d->hs_clk, hs_freq);
715 ret = clk_set_rate(d->hs_clk, d->hs_freq);
716 if (ret)
717 dev_err(d->dev, "failed to set HS clock rate %lu Hz\n",
718 d->hs_freq);
719
720 /* Start clocks */
721 ret = clk_prepare_enable(d->lp_clk);
722 if (ret)
723 dev_err(d->dev, "failed to enable LP clock\n");
724 else
725 dev_info(d->dev, "DSI LP clock rate %lu Hz\n",
726 d->lp_freq);
727 ret = clk_prepare_enable(d->hs_clk);
728 if (ret)
729 dev_err(d->dev, "failed to enable HS clock\n");
730 else
731 dev_info(d->dev, "DSI HS clock rate %lu Hz\n",
732 d->hs_freq);
733
734 if (d->mdsi->mode_flags & MIPI_DSI_MODE_VIDEO) {
735 mcde_dsi_setup_video_mode(d, mode);
736 } else {
737 /* Command mode, clear IF1 ID */
738 val = readl(d->regs + DSI_CMD_MODE_CTL);
739 /*
740 * If we enable low-power mode here with
741 * val |= DSI_CMD_MODE_CTL_IF1_LP_EN
742 * the display updates become really slow.
743 */
744 val &= ~DSI_CMD_MODE_CTL_IF1_ID_MASK;
745 writel(val, d->regs + DSI_CMD_MODE_CTL);
746 }
747}
748
749static void mcde_dsi_wait_for_command_mode_stop(struct mcde_dsi *d)
750{
751 u32 val;
752 int i;
753
754 /*
755 * Wait until we get out of command mode
756 * CSM = Command State Machine
757 */
758 i = 0;
759 val = DSI_CMD_MODE_STS_CSM_RUNNING;
760 while ((readl(d->regs + DSI_CMD_MODE_STS) & val) == val) {
761 /* Sleep for a millisecond */
762 usleep_range(1000, 2000);
763 if (i++ == 100) {
764 dev_warn(d->dev,
765 "could not get out of command mode\n");
766 return;
767 }
768 }
769}
770
771static void mcde_dsi_wait_for_video_mode_stop(struct mcde_dsi *d)
772{
773 u32 val;
774 int i;
775
776 /* Wait until we get out og video mode */
777 i = 0;
778 val = DSI_VID_MODE_STS_VSG_RUNNING;
779 while ((readl(d->regs + DSI_VID_MODE_STS) & val) == val) {
780 /* Sleep for a millisecond */
781 usleep_range(1000, 2000);
782 if (i++ == 100) {
783 dev_warn(d->dev,
784 "could not get out of video mode\n");
785 return;
786 }
787 }
788}
789
790static void mcde_dsi_bridge_disable(struct drm_bridge *bridge)
791{
792 struct mcde_dsi *d = bridge_to_mcde_dsi(bridge);
793 u32 val;
794
795 /* Disable all error interrupts */
796 writel(0, d->regs + DSI_VID_MODE_STS_CTL);
797
798 if (d->mdsi->mode_flags & MIPI_DSI_MODE_VIDEO) {
799 /* Stop video mode */
800 val = readl(d->regs + DSI_MCTL_MAIN_DATA_CTL);
801 val &= ~DSI_MCTL_MAIN_DATA_CTL_VID_EN;
802 writel(val, d->regs + DSI_MCTL_MAIN_DATA_CTL);
803 mcde_dsi_wait_for_video_mode_stop(d);
804 } else {
805 /* Stop command mode */
806 mcde_dsi_wait_for_command_mode_stop(d);
807 }
808
809 /* Stop clocks */
810 clk_disable_unprepare(d->hs_clk);
811 clk_disable_unprepare(d->lp_clk);
812}
813
814/*
815 * This connector needs no special handling, just use the default
816 * helpers for everything. It's pretty dummy.
817 */
818static const struct drm_connector_funcs mcde_dsi_connector_funcs = {
819 .reset = drm_atomic_helper_connector_reset,
820 .fill_modes = drm_helper_probe_single_connector_modes,
821 .destroy = drm_connector_cleanup,
822 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
823 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
824};
825
826static int mcde_dsi_get_modes(struct drm_connector *connector)
827{
828 struct mcde_dsi *d = connector_to_mcde_dsi(connector);
829
830 /* Just pass the question to the panel */
831 if (d->panel)
832 return drm_panel_get_modes(d->panel);
833
834 /* TODO: deal with bridges */
835
836 return 0;
837}
838
839static const struct drm_connector_helper_funcs
840mcde_dsi_connector_helper_funcs = {
841 .get_modes = mcde_dsi_get_modes,
842};
843
844static int mcde_dsi_bridge_attach(struct drm_bridge *bridge)
845{
846 struct mcde_dsi *d = bridge_to_mcde_dsi(bridge);
847 struct drm_device *drm = bridge->dev;
848 int ret;
849
850 drm_connector_helper_add(&d->connector,
851 &mcde_dsi_connector_helper_funcs);
852
853 if (!drm_core_check_feature(drm, DRIVER_ATOMIC)) {
854 dev_err(d->dev, "we need atomic updates\n");
855 return -ENOTSUPP;
856 }
857
858 ret = drm_connector_init(drm, &d->connector,
859 &mcde_dsi_connector_funcs,
860 DRM_MODE_CONNECTOR_DSI);
861 if (ret) {
862 dev_err(d->dev, "failed to initialize DSI bridge connector\n");
863 return ret;
864 }
865 d->connector.polled = DRM_CONNECTOR_POLL_CONNECT;
866 /* The encoder in the bridge attached to the DSI bridge */
867 drm_connector_attach_encoder(&d->connector, bridge->encoder);
868 /* Then we attach the DSI bridge to the output (panel etc) bridge */
869 ret = drm_bridge_attach(bridge->encoder, d->bridge_out, bridge);
870 if (ret) {
871 dev_err(d->dev, "failed to attach the DSI bridge\n");
872 return ret;
873 }
874 d->connector.status = connector_status_connected;
875
876 return 0;
877}
878
879static const struct drm_bridge_funcs mcde_dsi_bridge_funcs = {
880 .attach = mcde_dsi_bridge_attach,
881 .mode_set = mcde_dsi_bridge_mode_set,
882 .disable = mcde_dsi_bridge_disable,
883 .enable = mcde_dsi_bridge_enable,
884};
885
886static int mcde_dsi_bind(struct device *dev, struct device *master,
887 void *data)
888{
889 struct drm_device *drm = data;
890 struct mcde *mcde = drm->dev_private;
891 struct mcde_dsi *d = dev_get_drvdata(dev);
892 struct device_node *child;
893 struct drm_panel *panel = NULL;
894 struct drm_bridge *bridge = NULL;
895
896 if (!of_get_available_child_count(dev->of_node)) {
897 dev_info(dev, "unused DSI interface\n");
898 d->unused = true;
899 return 0;
900 }
901 d->mcde = mcde;
902 /* If the display attached before binding, set this up */
903 if (d->mdsi)
904 d->mcde->mdsi = d->mdsi;
905
906 /* Obtain the clocks */
907 d->hs_clk = devm_clk_get(dev, "hs");
908 if (IS_ERR(d->hs_clk)) {
909 dev_err(dev, "unable to get HS clock\n");
910 return PTR_ERR(d->hs_clk);
911 }
912
913 d->lp_clk = devm_clk_get(dev, "lp");
914 if (IS_ERR(d->lp_clk)) {
915 dev_err(dev, "unable to get LP clock\n");
916 return PTR_ERR(d->lp_clk);
917 }
918
919 /* Assert RESET through the PRCMU, active low */
920 /* FIXME: which DSI block? */
921 regmap_update_bits(d->prcmu, PRCM_DSI_SW_RESET,
922 PRCM_DSI_SW_RESET_DSI0_SW_RESETN, 0);
923
924 usleep_range(100, 200);
925
926 /* De-assert RESET again */
927 regmap_update_bits(d->prcmu, PRCM_DSI_SW_RESET,
928 PRCM_DSI_SW_RESET_DSI0_SW_RESETN,
929 PRCM_DSI_SW_RESET_DSI0_SW_RESETN);
930
931 /* Start up the hardware */
932 mcde_dsi_start(d);
933
934 /* Look for a panel as a child to this node */
935 for_each_available_child_of_node(dev->of_node, child) {
936 panel = of_drm_find_panel(child);
937 if (IS_ERR(panel)) {
938 dev_err(dev, "failed to find panel try bridge (%lu)\n",
939 PTR_ERR(panel));
940 bridge = of_drm_find_bridge(child);
941 if (IS_ERR(bridge)) {
942 dev_err(dev, "failed to find bridge (%lu)\n",
943 PTR_ERR(bridge));
944 return PTR_ERR(bridge);
945 }
946 }
947 }
948 if (panel) {
949 bridge = drm_panel_bridge_add(panel,
950 DRM_MODE_CONNECTOR_DSI);
951 if (IS_ERR(bridge)) {
952 dev_err(dev, "error adding panel bridge\n");
953 return PTR_ERR(bridge);
954 }
955 dev_info(dev, "connected to panel\n");
956 d->panel = panel;
957 } else if (bridge) {
958 /* TODO: AV8100 HDMI encoder goes here for example */
959 dev_info(dev, "connected to non-panel bridge (unsupported)\n");
960 return -ENODEV;
961 } else {
962 dev_err(dev, "no panel or bridge\n");
963 return -ENODEV;
964 }
965
966 d->bridge_out = bridge;
967
968 /* Create a bridge for this DSI channel */
969 d->bridge.funcs = &mcde_dsi_bridge_funcs;
970 d->bridge.of_node = dev->of_node;
971 drm_bridge_add(&d->bridge);
972
973 /* TODO: first come first serve, use a list */
974 mcde->bridge = &d->bridge;
975
976 dev_info(dev, "initialized MCDE DSI bridge\n");
977
978 return 0;
979}
980
981static void mcde_dsi_unbind(struct device *dev, struct device *master,
982 void *data)
983{
984 struct mcde_dsi *d = dev_get_drvdata(dev);
985
986 if (d->panel)
987 drm_panel_bridge_remove(d->bridge_out);
988 regmap_update_bits(d->prcmu, PRCM_DSI_SW_RESET,
989 PRCM_DSI_SW_RESET_DSI0_SW_RESETN, 0);
990}
991
992static const struct component_ops mcde_dsi_component_ops = {
993 .bind = mcde_dsi_bind,
994 .unbind = mcde_dsi_unbind,
995};
996
997static int mcde_dsi_probe(struct platform_device *pdev)
998{
999 struct device *dev = &pdev->dev;
1000 struct mcde_dsi *d;
1001 struct mipi_dsi_host *host;
1002 struct resource *res;
1003 u32 dsi_id;
1004 int ret;
1005
1006 d = devm_kzalloc(dev, sizeof(*d), GFP_KERNEL);
1007 if (!d)
1008 return -ENOMEM;
1009 d->dev = dev;
1010 platform_set_drvdata(pdev, d);
1011
1012 /* Get a handle on the PRCMU so we can do reset */
1013 d->prcmu =
1014 syscon_regmap_lookup_by_compatible("stericsson,db8500-prcmu");
1015 if (IS_ERR(d->prcmu)) {
1016 dev_err(dev, "no PRCMU regmap\n");
1017 return PTR_ERR(d->prcmu);
1018 }
1019
1020 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1021 d->regs = devm_ioremap_resource(dev, res);
1022 if (IS_ERR(d->regs)) {
1023 dev_err(dev, "no DSI regs\n");
1024 return PTR_ERR(d->regs);
1025 }
1026
1027 dsi_id = readl(d->regs + DSI_ID_REG);
1028 dev_info(dev, "HW revision 0x%08x\n", dsi_id);
1029
1030 host = &d->dsi_host;
1031 host->dev = dev;
1032 host->ops = &mcde_dsi_host_ops;
1033 ret = mipi_dsi_host_register(host);
1034 if (ret < 0) {
1035 dev_err(dev, "failed to register DSI host: %d\n", ret);
1036 return ret;
1037 }
1038 dev_info(dev, "registered DSI host\n");
1039
1040 platform_set_drvdata(pdev, d);
1041 return component_add(dev, &mcde_dsi_component_ops);
1042}
1043
1044static int mcde_dsi_remove(struct platform_device *pdev)
1045{
1046 struct mcde_dsi *d = platform_get_drvdata(pdev);
1047
1048 component_del(&pdev->dev, &mcde_dsi_component_ops);
1049 mipi_dsi_host_unregister(&d->dsi_host);
1050
1051 return 0;
1052}
1053
1054static const struct of_device_id mcde_dsi_of_match[] = {
1055 {
1056 .compatible = "ste,mcde-dsi",
1057 },
1058 {},
1059};
1060
1061struct platform_driver mcde_dsi_driver = {
1062 .driver = {
1063 .name = "mcde-dsi",
1064 .of_match_table = of_match_ptr(mcde_dsi_of_match),
1065 },
1066 .probe = mcde_dsi_probe,
1067 .remove = mcde_dsi_remove,
1068};