1/* SPDX-License-Identifier: GPL-2.0 */
  2#ifndef __DRM_MCDE_DISPLAY_REGS
  3#define __DRM_MCDE_DISPLAY_REGS
  4
  5/* PP (pixel processor) interrupts */
  6#define MCDE_IMSCPP 0x00000104
  7#define MCDE_RISPP 0x00000114
  8#define MCDE_MISPP 0x00000124
  9#define MCDE_SISPP 0x00000134
 10
 11#define MCDE_PP_VCMPA BIT(0)
 12#define MCDE_PP_VCMPB BIT(1)
 13#define MCDE_PP_VSCC0 BIT(2)
 14#define MCDE_PP_VSCC1 BIT(3)
 15#define MCDE_PP_VCMPC0 BIT(4)
 16#define MCDE_PP_VCMPC1 BIT(5)
 17#define MCDE_PP_ROTFD_A BIT(6)
 18#define MCDE_PP_ROTFD_B BIT(7)
 19
 20/* Overlay interrupts */
 21#define MCDE_IMSCOVL 0x00000108
 22#define MCDE_RISOVL 0x00000118
 23#define MCDE_MISOVL 0x00000128
 24#define MCDE_SISOVL 0x00000138
 25
 26/* Channel interrupts */
 27#define MCDE_IMSCCHNL 0x0000010C
 28#define MCDE_RISCHNL 0x0000011C
 29#define MCDE_MISCHNL 0x0000012C
 30#define MCDE_SISCHNL 0x0000013C
 31
 32/* X = 0..9 */
 33#define MCDE_EXTSRCXA0 0x00000200
 34#define MCDE_EXTSRCXA0_GROUPOFFSET 0x20
 35#define MCDE_EXTSRCXA0_BASEADDRESS0_SHIFT 3
 36#define MCDE_EXTSRCXA0_BASEADDRESS0_MASK 0xFFFFFFF8
 37
 38#define MCDE_EXTSRCXA1 0x00000204
 39#define MCDE_EXTSRCXA1_GROUPOFFSET 0x20
 40#define MCDE_EXTSRCXA1_BASEADDRESS1_SHIFT 3
 41#define MCDE_EXTSRCXA1_BASEADDRESS1_MASK 0xFFFFFFF8
 42
 43/* External sources 0..9 */
 44#define MCDE_EXTSRC0CONF 0x0000020C
 45#define MCDE_EXTSRC1CONF 0x0000022C
 46#define MCDE_EXTSRC2CONF 0x0000024C
 47#define MCDE_EXTSRC3CONF 0x0000026C
 48#define MCDE_EXTSRC4CONF 0x0000028C
 49#define MCDE_EXTSRC5CONF 0x000002AC
 50#define MCDE_EXTSRC6CONF 0x000002CC
 51#define MCDE_EXTSRC7CONF 0x000002EC
 52#define MCDE_EXTSRC8CONF 0x0000030C
 53#define MCDE_EXTSRC9CONF 0x0000032C
 54#define MCDE_EXTSRCXCONF_GROUPOFFSET 0x20
 55#define MCDE_EXTSRCXCONF_BUF_ID_SHIFT 0
 56#define MCDE_EXTSRCXCONF_BUF_ID_MASK 0x00000003
 57#define MCDE_EXTSRCXCONF_BUF_NB_SHIFT 2
 58#define MCDE_EXTSRCXCONF_BUF_NB_MASK 0x0000000C
 59#define MCDE_EXTSRCXCONF_PRI_OVLID_SHIFT 4
 60#define MCDE_EXTSRCXCONF_PRI_OVLID_MASK 0x000000F0
 61#define MCDE_EXTSRCXCONF_BPP_SHIFT 8
 62#define MCDE_EXTSRCXCONF_BPP_MASK 0x00000F00
 63#define MCDE_EXTSRCXCONF_BPP_1BPP_PAL 0
 64#define MCDE_EXTSRCXCONF_BPP_2BPP_PAL 1
 65#define MCDE_EXTSRCXCONF_BPP_4BPP_PAL 2
 66#define MCDE_EXTSRCXCONF_BPP_8BPP_PAL 3
 67#define MCDE_EXTSRCXCONF_BPP_RGB444 4
 68#define MCDE_EXTSRCXCONF_BPP_ARGB4444 5
 69#define MCDE_EXTSRCXCONF_BPP_IRGB1555 6
 70#define MCDE_EXTSRCXCONF_BPP_RGB565 7
 71#define MCDE_EXTSRCXCONF_BPP_RGB888 8
 72#define MCDE_EXTSRCXCONF_BPP_XRGB8888 9
 73#define MCDE_EXTSRCXCONF_BPP_ARGB8888 10
 74#define MCDE_EXTSRCXCONF_BPP_YCBCR422 11
 75#define MCDE_EXTSRCXCONF_BGR BIT(12)
 76#define MCDE_EXTSRCXCONF_BEBO BIT(13)
 77#define MCDE_EXTSRCXCONF_BEPO BIT(14)
 78#define MCDE_EXTSRCXCONF_TUNNELING_BUFFER_HEIGHT_SHIFT 16
 79#define MCDE_EXTSRCXCONF_TUNNELING_BUFFER_HEIGHT_MASK 0x0FFF0000
 80
 81/* External sources 0..9 */
 82#define MCDE_EXTSRC0CR 0x00000210
 83#define MCDE_EXTSRC1CR 0x00000230
 84#define MCDE_EXTSRC2CR 0x00000250
 85#define MCDE_EXTSRC3CR 0x00000270
 86#define MCDE_EXTSRC4CR 0x00000290
 87#define MCDE_EXTSRC5CR 0x000002B0
 88#define MCDE_EXTSRC6CR 0x000002D0
 89#define MCDE_EXTSRC7CR 0x000002F0
 90#define MCDE_EXTSRC8CR 0x00000310
 91#define MCDE_EXTSRC9CR 0x00000330
 92#define MCDE_EXTSRCXCR_SEL_MOD_SHIFT 0
 93#define MCDE_EXTSRCXCR_SEL_MOD_MASK 0x00000003
 94#define MCDE_EXTSRCXCR_SEL_MOD_EXTERNAL_SEL 0
 95#define MCDE_EXTSRCXCR_SEL_MOD_AUTO_TOGGLE 1
 96#define MCDE_EXTSRCXCR_SEL_MOD_SOFTWARE_SEL 2
 97#define MCDE_EXTSRCXCR_MULTIOVL_CTRL_PRIMARY BIT(2) /* 0 = all */
 98#define MCDE_EXTSRCXCR_FS_DIV_DISABLE BIT(3)
 99#define MCDE_EXTSRCXCR_FORCE_FS_DIV BIT(4)
100
101/* Only external source 6 has a second address register */
102#define MCDE_EXTSRC6A2 0x000002C8
103
104/* 6 overlays */
105#define MCDE_OVL0CR 0x00000400
106#define MCDE_OVL1CR 0x00000420
107#define MCDE_OVL2CR 0x00000440
108#define MCDE_OVL3CR 0x00000460
109#define MCDE_OVL4CR 0x00000480
110#define MCDE_OVL5CR 0x000004A0
111#define MCDE_OVLXCR_OVLEN BIT(0)
112#define MCDE_OVLXCR_COLCCTRL_DISABLED 0
113#define MCDE_OVLXCR_COLCCTRL_ENABLED_NO_SAT (1 << 1)
114#define MCDE_OVLXCR_COLCCTRL_ENABLED_SAT (2 << 1)
115#define MCDE_OVLXCR_CKEYGEN BIT(3)
116#define MCDE_OVLXCR_ALPHAPMEN BIT(4)
117#define MCDE_OVLXCR_OVLF BIT(5)
118#define MCDE_OVLXCR_OVLR BIT(6)
119#define MCDE_OVLXCR_OVLB BIT(7)
120#define MCDE_OVLXCR_FETCH_ROPC_SHIFT 8
121#define MCDE_OVLXCR_FETCH_ROPC_MASK 0x0000FF00
122#define MCDE_OVLXCR_STBPRIO_SHIFT 16
123#define MCDE_OVLXCR_STBPRIO_MASK 0x000F0000
124#define MCDE_OVLXCR_BURSTSIZE_SHIFT 20
125#define MCDE_OVLXCR_BURSTSIZE_MASK 0x00F00000
126#define MCDE_OVLXCR_BURSTSIZE_1W 0
127#define MCDE_OVLXCR_BURSTSIZE_2W 1
128#define MCDE_OVLXCR_BURSTSIZE_4W 2
129#define MCDE_OVLXCR_BURSTSIZE_8W 3
130#define MCDE_OVLXCR_BURSTSIZE_16W 4
131#define MCDE_OVLXCR_BURSTSIZE_HW_1W 8
132#define MCDE_OVLXCR_BURSTSIZE_HW_2W 9
133#define MCDE_OVLXCR_BURSTSIZE_HW_4W 10
134#define MCDE_OVLXCR_BURSTSIZE_HW_8W 11
135#define MCDE_OVLXCR_BURSTSIZE_HW_16W 12
136#define MCDE_OVLXCR_MAXOUTSTANDING_SHIFT 24
137#define MCDE_OVLXCR_MAXOUTSTANDING_MASK 0x0F000000
138#define MCDE_OVLXCR_MAXOUTSTANDING_1_REQ 0
139#define MCDE_OVLXCR_MAXOUTSTANDING_2_REQ 1
140#define MCDE_OVLXCR_MAXOUTSTANDING_4_REQ 2
141#define MCDE_OVLXCR_MAXOUTSTANDING_8_REQ 3
142#define MCDE_OVLXCR_MAXOUTSTANDING_16_REQ 4
143#define MCDE_OVLXCR_ROTBURSTSIZE_SHIFT 28
144#define MCDE_OVLXCR_ROTBURSTSIZE_MASK 0xF0000000
145#define MCDE_OVLXCR_ROTBURSTSIZE_1W 0
146#define MCDE_OVLXCR_ROTBURSTSIZE_2W 1
147#define MCDE_OVLXCR_ROTBURSTSIZE_4W 2
148#define MCDE_OVLXCR_ROTBURSTSIZE_8W 3
149#define MCDE_OVLXCR_ROTBURSTSIZE_16W 4
150#define MCDE_OVLXCR_ROTBURSTSIZE_HW_1W 8
151#define MCDE_OVLXCR_ROTBURSTSIZE_HW_2W 9
152#define MCDE_OVLXCR_ROTBURSTSIZE_HW_4W 10
153#define MCDE_OVLXCR_ROTBURSTSIZE_HW_8W 11
154#define MCDE_OVLXCR_ROTBURSTSIZE_HW_16W 12
155
156#define MCDE_OVL0CONF 0x00000404
157#define MCDE_OVL1CONF 0x00000424
158#define MCDE_OVL2CONF 0x00000444
159#define MCDE_OVL3CONF 0x00000464
160#define MCDE_OVL4CONF 0x00000484
161#define MCDE_OVL5CONF 0x000004A4
162#define MCDE_OVLXCONF_PPL_SHIFT 0
163#define MCDE_OVLXCONF_PPL_MASK 0x000007FF
164#define MCDE_OVLXCONF_EXTSRC_ID_SHIFT 11
165#define MCDE_OVLXCONF_EXTSRC_ID_MASK 0x00007800
166#define MCDE_OVLXCONF_LPF_SHIFT 16
167#define MCDE_OVLXCONF_LPF_MASK 0x07FF0000
168
169#define MCDE_OVL0CONF2 0x00000408
170#define MCDE_OVL1CONF2 0x00000428
171#define MCDE_OVL2CONF2 0x00000448
172#define MCDE_OVL3CONF2 0x00000468
173#define MCDE_OVL4CONF2 0x00000488
174#define MCDE_OVL5CONF2 0x000004A8
175#define MCDE_OVLXCONF2_BP_PER_PIXEL_ALPHA 0
176#define MCDE_OVLXCONF2_BP_CONSTANT_ALPHA BIT(0)
177#define MCDE_OVLXCONF2_ALPHAVALUE_SHIFT 1
178#define MCDE_OVLXCONF2_ALPHAVALUE_MASK 0x000001FE
179#define MCDE_OVLXCONF2_OPQ BIT(9)
180#define MCDE_OVLXCONF2_PIXOFF_SHIFT 10
181#define MCDE_OVLXCONF2_PIXOFF_MASK 0x0000FC00
182#define MCDE_OVLXCONF2_PIXELFETCHERWATERMARKLEVEL_SHIFT 16
183#define MCDE_OVLXCONF2_PIXELFETCHERWATERMARKLEVEL_MASK 0x1FFF0000
184
185#define MCDE_OVL0LJINC 0x0000040C
186#define MCDE_OVL1LJINC 0x0000042C
187#define MCDE_OVL2LJINC 0x0000044C
188#define MCDE_OVL3LJINC 0x0000046C
189#define MCDE_OVL4LJINC 0x0000048C
190#define MCDE_OVL5LJINC 0x000004AC
191
192#define MCDE_OVL0CROP 0x00000410
193#define MCDE_OVL1CROP 0x00000430
194#define MCDE_OVL2CROP 0x00000450
195#define MCDE_OVL3CROP 0x00000470
196#define MCDE_OVL4CROP 0x00000490
197#define MCDE_OVL5CROP 0x000004B0
198#define MCDE_OVLXCROP_TMRGN_SHIFT 0
199#define MCDE_OVLXCROP_TMRGN_MASK 0x003FFFFF
200#define MCDE_OVLXCROP_LMRGN_SHIFT 22
201#define MCDE_OVLXCROP_LMRGN_MASK 0xFFC00000
202
203#define MCDE_OVL0COMP 0x00000414
204#define MCDE_OVL1COMP 0x00000434
205#define MCDE_OVL2COMP 0x00000454
206#define MCDE_OVL3COMP 0x00000474
207#define MCDE_OVL4COMP 0x00000494
208#define MCDE_OVL5COMP 0x000004B4
209#define MCDE_OVLXCOMP_XPOS_SHIFT 0
210#define MCDE_OVLXCOMP_XPOS_MASK 0x000007FF
211#define MCDE_OVLXCOMP_CH_ID_SHIFT 11
212#define MCDE_OVLXCOMP_CH_ID_MASK 0x00007800
213#define MCDE_OVLXCOMP_YPOS_SHIFT 16
214#define MCDE_OVLXCOMP_YPOS_MASK 0x07FF0000
215#define MCDE_OVLXCOMP_Z_SHIFT 27
216#define MCDE_OVLXCOMP_Z_MASK 0x78000000
217
218#define MCDE_CRC 0x00000C00
219#define MCDE_CRC_C1EN BIT(2)
220#define MCDE_CRC_C2EN BIT(3)
221#define MCDE_CRC_SYCEN0 BIT(7)
222#define MCDE_CRC_SYCEN1 BIT(8)
223#define MCDE_CRC_SIZE1 BIT(9)
224#define MCDE_CRC_SIZE2 BIT(10)
225#define MCDE_CRC_YUVCONVC1EN BIT(15)
226#define MCDE_CRC_CS1EN BIT(16)
227#define MCDE_CRC_CS2EN BIT(17)
228#define MCDE_CRC_CS1POL BIT(19)
229#define MCDE_CRC_CS2POL BIT(20)
230#define MCDE_CRC_CD1POL BIT(21)
231#define MCDE_CRC_CD2POL BIT(22)
232#define MCDE_CRC_WR1POL BIT(23)
233#define MCDE_CRC_WR2POL BIT(24)
234#define MCDE_CRC_RD1POL BIT(25)
235#define MCDE_CRC_RD2POL BIT(26)
236#define MCDE_CRC_SYNCCTRL_SHIFT 29
237#define MCDE_CRC_SYNCCTRL_MASK 0x60000000
238#define MCDE_CRC_SYNCCTRL_NO_SYNC 0
239#define MCDE_CRC_SYNCCTRL_DBI0 1
240#define MCDE_CRC_SYNCCTRL_DBI1 2
241#define MCDE_CRC_SYNCCTRL_PING_PONG 3
242#define MCDE_CRC_CLAMPC1EN BIT(31)
243
244#define MCDE_VSCRC0 0x00000C5C
245#define MCDE_VSCRC1 0x00000C60
246#define MCDE_VSCRC_VSPMIN_MASK 0x00000FFF
247#define MCDE_VSCRC_VSPMAX_SHIFT 12
248#define MCDE_VSCRC_VSPMAX_MASK 0x00FFF000
249#define MCDE_VSCRC_VSPDIV_SHIFT 24
250#define MCDE_VSCRC_VSPDIV_MASK 0x07000000
251#define MCDE_VSCRC_VSPDIV_MCDECLK_DIV_1 0
252#define MCDE_VSCRC_VSPDIV_MCDECLK_DIV_2 1
253#define MCDE_VSCRC_VSPDIV_MCDECLK_DIV_4 2
254#define MCDE_VSCRC_VSPDIV_MCDECLK_DIV_8 3
255#define MCDE_VSCRC_VSPDIV_MCDECLK_DIV_16 4
256#define MCDE_VSCRC_VSPDIV_MCDECLK_DIV_32 5
257#define MCDE_VSCRC_VSPDIV_MCDECLK_DIV_64 6
258#define MCDE_VSCRC_VSPDIV_MCDECLK_DIV_128 7
259#define MCDE_VSCRC_VSPOL BIT(27) /* 0 active high, 1 active low */
260#define MCDE_VSCRC_VSSEL BIT(28) /* 0 VSYNC0, 1 VSYNC1 */
261#define MCDE_VSCRC_VSDBL BIT(29)
262
263/* Channel config 0..3 */
264#define MCDE_CHNL0CONF 0x00000600
265#define MCDE_CHNL1CONF 0x00000620
266#define MCDE_CHNL2CONF 0x00000640
267#define MCDE_CHNL3CONF 0x00000660
268#define MCDE_CHNLXCONF_PPL_SHIFT 0
269#define MCDE_CHNLXCONF_PPL_MASK 0x000007FF
270#define MCDE_CHNLXCONF_LPF_SHIFT 16
271#define MCDE_CHNLXCONF_LPF_MASK 0x07FF0000
272#define MCDE_MAX_WIDTH 2048
273
274/* Channel status 0..3 */
275#define MCDE_CHNL0STAT 0x00000604
276#define MCDE_CHNL1STAT 0x00000624
277#define MCDE_CHNL2STAT 0x00000644
278#define MCDE_CHNL3STAT 0x00000664
279#define MCDE_CHNLXSTAT_CHNLRD BIT(0)
280#define MCDE_CHNLXSTAT_CHNLA BIT(1)
281#define MCDE_CHNLXSTAT_CHNLBLBCKGND_EN BIT(16)
282#define MCDE_CHNLXSTAT_PPLX2_V422 BIT(17)
283#define MCDE_CHNLXSTAT_LPFX2_V422 BIT(18)
284
285/* Sync settings for channel 0..3 */
286#define MCDE_CHNL0SYNCHMOD 0x00000608
287#define MCDE_CHNL1SYNCHMOD 0x00000628
288#define MCDE_CHNL2SYNCHMOD 0x00000648
289#define MCDE_CHNL3SYNCHMOD 0x00000668
290
291#define MCDE_CHNLXSYNCHMOD_SRC_SYNCH_SHIFT 0
292#define MCDE_CHNLXSYNCHMOD_SRC_SYNCH_MASK 0x00000003
293#define MCDE_CHNLXSYNCHMOD_SRC_SYNCH_HARDWARE 0
294#define MCDE_CHNLXSYNCHMOD_SRC_SYNCH_NO_SYNCH 1
295#define MCDE_CHNLXSYNCHMOD_SRC_SYNCH_SOFTWARE 2
296#define MCDE_CHNLXSYNCHMOD_OUT_SYNCH_SRC_SHIFT 2
297#define MCDE_CHNLXSYNCHMOD_OUT_SYNCH_SRC_MASK 0x0000001C
298#define MCDE_CHNLXSYNCHMOD_OUT_SYNCH_SRC_FORMATTER 0
299#define MCDE_CHNLXSYNCHMOD_OUT_SYNCH_SRC_TE0 1
300#define MCDE_CHNLXSYNCHMOD_OUT_SYNCH_SRC_TE1 2
301
302/* Software sync triggers for channel 0..3 */
303#define MCDE_CHNL0SYNCHSW 0x0000060C
304#define MCDE_CHNL1SYNCHSW 0x0000062C
305#define MCDE_CHNL2SYNCHSW 0x0000064C
306#define MCDE_CHNL3SYNCHSW 0x0000066C
307#define MCDE_CHNLXSYNCHSW_SW_TRIG BIT(0)
308
309#define MCDE_CHNL0BCKGNDCOL 0x00000610
310#define MCDE_CHNL1BCKGNDCOL 0x00000630
311#define MCDE_CHNL2BCKGNDCOL 0x00000650
312#define MCDE_CHNL3BCKGNDCOL 0x00000670
313#define MCDE_CHNLXBCKGNDCOL_B_SHIFT 0
314#define MCDE_CHNLXBCKGNDCOL_B_MASK 0x000000FF
315#define MCDE_CHNLXBCKGNDCOL_G_SHIFT 8
316#define MCDE_CHNLXBCKGNDCOL_G_MASK 0x0000FF00
317#define MCDE_CHNLXBCKGNDCOL_R_SHIFT 16
318#define MCDE_CHNLXBCKGNDCOL_R_MASK 0x00FF0000
319
320#define MCDE_CHNL0MUXING 0x00000614
321#define MCDE_CHNL1MUXING 0x00000634
322#define MCDE_CHNL2MUXING 0x00000654
323#define MCDE_CHNL3MUXING 0x00000674
324#define MCDE_CHNLXMUXING_FIFO_ID_FIFO_A 0
325#define MCDE_CHNLXMUXING_FIFO_ID_FIFO_B 1
326#define MCDE_CHNLXMUXING_FIFO_ID_FIFO_C0 2
327#define MCDE_CHNLXMUXING_FIFO_ID_FIFO_C1 3
328
329/* Pixel processing control registers for channel A B,  */
330#define MCDE_CRA0 0x00000800
331#define MCDE_CRB0 0x00000A00
332#define MCDE_CRX0_FLOEN BIT(0)
333#define MCDE_CRX0_POWEREN BIT(1)
334#define MCDE_CRX0_BLENDEN BIT(2)
335#define MCDE_CRX0_AFLICKEN BIT(3)
336#define MCDE_CRX0_PALEN BIT(4)
337#define MCDE_CRX0_DITHEN BIT(5)
338#define MCDE_CRX0_GAMEN BIT(6)
339#define MCDE_CRX0_KEYCTRL_SHIFT 7
340#define MCDE_CRX0_KEYCTRL_MASK 0x00000380
341#define MCDE_CRX0_KEYCTRL_OFF 0
342#define MCDE_CRX0_KEYCTRL_ALPHA_RGB 1
343#define MCDE_CRX0_KEYCTRL_RGB 2
344#define MCDE_CRX0_KEYCTRL_FALPHA_FRGB 4
345#define MCDE_CRX0_KEYCTRL_FRGB 5
346#define MCDE_CRX0_BLENDCTRL BIT(10)
347#define MCDE_CRX0_FLICKMODE_SHIFT 11
348#define MCDE_CRX0_FLICKMODE_MASK 0x00001800
349#define MCDE_CRX0_FLICKMODE_FORCE_FILTER_0 0
350#define MCDE_CRX0_FLICKMODE_ADAPTIVE 1
351#define MCDE_CRX0_FLICKMODE_TEST_MODE 2
352#define MCDE_CRX0_FLOCKFORMAT_RGB BIT(13) /* 0 = YCVCR */
353#define MCDE_CRX0_PALMODE_GAMMA BIT(14) /* 0 = palette */
354#define MCDE_CRX0_OLEDEN BIT(15)
355#define MCDE_CRX0_ALPHABLEND_SHIFT 16
356#define MCDE_CRX0_ALPHABLEND_MASK 0x00FF0000
357#define MCDE_CRX0_ROTEN BIT(24)
358
359#define MCDE_CRA1 0x00000804
360#define MCDE_CRB1 0x00000A04
361#define MCDE_CRX1_PCD_SHIFT 0
362#define MCDE_CRX1_PCD_MASK 0x000003FF
363#define MCDE_CRX1_CLKSEL_SHIFT 10
364#define MCDE_CRX1_CLKSEL_MASK 0x00001C00
365#define MCDE_CRX1_CLKSEL_CLKPLL72 0
366#define MCDE_CRX1_CLKSEL_CLKPLL27 2
367#define MCDE_CRX1_CLKSEL_TV1CLK 3
368#define MCDE_CRX1_CLKSEL_TV2CLK 4
369#define MCDE_CRX1_CLKSEL_MCDECLK 5
370#define MCDE_CRX1_CDWIN_SHIFT 13
371#define MCDE_CRX1_CDWIN_MASK 0x0001E000
372#define MCDE_CRX1_CDWIN_8BPP_C1 0
373#define MCDE_CRX1_CDWIN_12BPP_C1 1
374#define MCDE_CRX1_CDWIN_12BPP_C2 2
375#define MCDE_CRX1_CDWIN_16BPP_C1 3
376#define MCDE_CRX1_CDWIN_16BPP_C2 4
377#define MCDE_CRX1_CDWIN_16BPP_C3 5
378#define MCDE_CRX1_CDWIN_18BPP_C1 6
379#define MCDE_CRX1_CDWIN_18BPP_C2 7
380#define MCDE_CRX1_CDWIN_24BPP 8
381#define MCDE_CRX1_OUTBPP_SHIFT 25
382#define MCDE_CRX1_OUTBPP_MASK 0x1E000000
383#define MCDE_CRX1_OUTBPP_MONO1 0
384#define MCDE_CRX1_OUTBPP_MONO2 1
385#define MCDE_CRX1_OUTBPP_MONO4 2
386#define MCDE_CRX1_OUTBPP_MONO8 3
387#define MCDE_CRX1_OUTBPP_8BPP 4
388#define MCDE_CRX1_OUTBPP_12BPP 5
389#define MCDE_CRX1_OUTBPP_15BPP 6
390#define MCDE_CRX1_OUTBPP_16BPP 7
391#define MCDE_CRX1_OUTBPP_18BPP 8
392#define MCDE_CRX1_OUTBPP_24BPP 9
393#define MCDE_CRX1_BCD BIT(29)
394#define MCDE_CRA1_CLKTYPE_TVXCLKSEL1 BIT(30) /* 0 = TVXCLKSEL1 */
395
396#define MCDE_COLKEYA 0x00000808
397#define MCDE_COLKEYB 0x00000A08
398
399#define MCDE_FCOLKEYA 0x0000080C
400#define MCDE_FCOLKEYB 0x00000A0C
401
402#define MCDE_RGBCONV1A 0x00000810
403#define MCDE_RGBCONV1B 0x00000A10
404
405#define MCDE_RGBCONV2A 0x00000814
406#define MCDE_RGBCONV2B 0x00000A14
407
408#define MCDE_RGBCONV3A 0x00000818
409#define MCDE_RGBCONV3B 0x00000A18
410
411#define MCDE_RGBCONV4A 0x0000081C
412#define MCDE_RGBCONV4B 0x00000A1C
413
414#define MCDE_RGBCONV5A 0x00000820
415#define MCDE_RGBCONV5B 0x00000A20
416
417#define MCDE_RGBCONV6A 0x00000824
418#define MCDE_RGBCONV6B 0x00000A24
419
420/* Rotation */
421#define MCDE_ROTACONF 0x0000087C
422#define MCDE_ROTBCONF 0x00000A7C
423
424#define MCDE_SYNCHCONFA 0x00000880
425#define MCDE_SYNCHCONFB 0x00000A80
426
427/* Channel A+B control registers */
428#define MCDE_CTRLA 0x00000884
429#define MCDE_CTRLB 0x00000A84
430#define MCDE_CTRLX_FIFOWTRMRK_SHIFT 0
431#define MCDE_CTRLX_FIFOWTRMRK_MASK 0x000003FF
432#define MCDE_CTRLX_FIFOEMPTY BIT(12)
433#define MCDE_CTRLX_FIFOFULL BIT(13)
434#define MCDE_CTRLX_FORMID_SHIFT 16
435#define MCDE_CTRLX_FORMID_MASK 0x00070000
436#define MCDE_CTRLX_FORMID_DSI0VID 0
437#define MCDE_CTRLX_FORMID_DSI0CMD 1
438#define MCDE_CTRLX_FORMID_DSI1VID 2
439#define MCDE_CTRLX_FORMID_DSI1CMD 3
440#define MCDE_CTRLX_FORMID_DSI2VID 4
441#define MCDE_CTRLX_FORMID_DSI2CMD 5
442#define MCDE_CTRLX_FORMID_DPIA 0
443#define MCDE_CTRLX_FORMID_DPIB 1
444#define MCDE_CTRLX_FORMTYPE_SHIFT 20
445#define MCDE_CTRLX_FORMTYPE_MASK 0x00700000
446#define MCDE_CTRLX_FORMTYPE_DPITV 0
447#define MCDE_CTRLX_FORMTYPE_DBI 1
448#define MCDE_CTRLX_FORMTYPE_DSI 2
449
450#define MCDE_DSIVID0CONF0 0x00000E00
451#define MCDE_DSICMD0CONF0 0x00000E20
452#define MCDE_DSIVID1CONF0 0x00000E40
453#define MCDE_DSICMD1CONF0 0x00000E60
454#define MCDE_DSIVID2CONF0 0x00000E80
455#define MCDE_DSICMD2CONF0 0x00000EA0
456#define MCDE_DSICONF0_BLANKING_SHIFT 0
457#define MCDE_DSICONF0_BLANKING_MASK 0x000000FF
458#define MCDE_DSICONF0_VID_MODE_CMD 0
459#define MCDE_DSICONF0_VID_MODE_VID BIT(12)
460#define MCDE_DSICONF0_CMD8 BIT(13)
461#define MCDE_DSICONF0_BIT_SWAP BIT(16)
462#define MCDE_DSICONF0_BYTE_SWAP BIT(17)
463#define MCDE_DSICONF0_DCSVID_NOTGEN BIT(18)
464#define MCDE_DSICONF0_PACKING_SHIFT 20
465#define MCDE_DSICONF0_PACKING_MASK 0x00700000
466#define MCDE_DSICONF0_PACKING_RGB565 0
467#define MCDE_DSICONF0_PACKING_RGB666 1
468#define MCDE_DSICONF0_PACKING_RGB666_PACKED 2
469#define MCDE_DSICONF0_PACKING_RGB888 3
470#define MCDE_DSICONF0_PACKING_HDTV 4
471
472#define MCDE_DSIVID0FRAME 0x00000E04
473#define MCDE_DSICMD0FRAME 0x00000E24
474#define MCDE_DSIVID1FRAME 0x00000E44
475#define MCDE_DSICMD1FRAME 0x00000E64
476#define MCDE_DSIVID2FRAME 0x00000E84
477#define MCDE_DSICMD2FRAME 0x00000EA4
478
479#define MCDE_DSIVID0PKT 0x00000E08
480#define MCDE_DSICMD0PKT 0x00000E28
481#define MCDE_DSIVID1PKT 0x00000E48
482#define MCDE_DSICMD1PKT 0x00000E68
483#define MCDE_DSIVID2PKT 0x00000E88
484#define MCDE_DSICMD2PKT 0x00000EA8
485
486#define MCDE_DSIVID0SYNC 0x00000E0C
487#define MCDE_DSICMD0SYNC 0x00000E2C
488#define MCDE_DSIVID1SYNC 0x00000E4C
489#define MCDE_DSICMD1SYNC 0x00000E6C
490#define MCDE_DSIVID2SYNC 0x00000E8C
491#define MCDE_DSICMD2SYNC 0x00000EAC
492
493#define MCDE_DSIVID0CMDW 0x00000E10
494#define MCDE_DSICMD0CMDW 0x00000E30
495#define MCDE_DSIVID1CMDW 0x00000E50
496#define MCDE_DSICMD1CMDW 0x00000E70
497#define MCDE_DSIVID2CMDW 0x00000E90
498#define MCDE_DSICMD2CMDW 0x00000EB0
499#define MCDE_DSIVIDXCMDW_CMDW_CONTINUE_SHIFT 0
500#define MCDE_DSIVIDXCMDW_CMDW_CONTINUE_MASK 0x0000FFFF
501#define MCDE_DSIVIDXCMDW_CMDW_START_SHIFT 16
502#define MCDE_DSIVIDXCMDW_CMDW_START_MASK 0xFFFF0000
503
504#define MCDE_DSIVID0DELAY0 0x00000E14
505#define MCDE_DSICMD0DELAY0 0x00000E34
506#define MCDE_DSIVID1DELAY0 0x00000E54
507#define MCDE_DSICMD1DELAY0 0x00000E74
508#define MCDE_DSIVID2DELAY0 0x00000E94
509#define MCDE_DSICMD2DELAY0 0x00000EB4
510
511#define MCDE_DSIVID0DELAY1 0x00000E18
512#define MCDE_DSICMD0DELAY1 0x00000E38
513#define MCDE_DSIVID1DELAY1 0x00000E58
514#define MCDE_DSICMD1DELAY1 0x00000E78
515#define MCDE_DSIVID2DELAY1 0x00000E98
516#define MCDE_DSICMD2DELAY1 0x00000EB8
517
518#endif /* __DRM_MCDE_DISPLAY_REGS */