1/*
  2 * SPDX-License-Identifier: MIT
  3 *
  4 * Copyright © 2017-2018 Intel Corporation
  5 */
  6
  7#ifndef __I915_PMU_H__
  8#define __I915_PMU_H__
  9
 10#include <linux/hrtimer.h>
 11#include <linux/perf_event.h>
 12#include <linux/spinlock_types.h>
 13#include <drm/i915_drm.h>
 14
 15struct drm_i915_private;
 16
 17enum {
 18	__I915_SAMPLE_FREQ_ACT = 0,
 19	__I915_SAMPLE_FREQ_REQ,
 20	__I915_SAMPLE_RC6,
 21	__I915_SAMPLE_RC6_ESTIMATED,
 22	__I915_NUM_PMU_SAMPLERS
 23};
 24
 25/**
 26 * How many different events we track in the global PMU mask.
 27 *
 28 * It is also used to know to needed number of event reference counters.
 29 */
 30#define I915_PMU_MASK_BITS \
 31	((1 << I915_PMU_SAMPLE_BITS) + \
 32	 (I915_PMU_LAST + 1 - __I915_PMU_OTHER(0)))
 33
 34#define I915_ENGINE_SAMPLE_COUNT (I915_SAMPLE_SEMA + 1)
 35
 36struct i915_pmu_sample {
 37	u64 cur;
 38};
 39
 40struct i915_pmu {
 41	/**
 42	 * @node: List node for CPU hotplug handling.
 43	 */
 44	struct hlist_node node;
 45	/**
 46	 * @base: PMU base.
 47	 */
 48	struct pmu base;
 49	/**
 50	 * @lock: Lock protecting enable mask and ref count handling.
 51	 */
 52	spinlock_t lock;
 53	/**
 54	 * @timer: Timer for internal i915 PMU sampling.
 55	 */
 56	struct hrtimer timer;
 57	/**
 58	 * @enable: Bitmask of all currently enabled events.
 59	 *
 60	 * Bits are derived from uAPI event numbers in a way that low 16 bits
 61	 * correspond to engine event _sample_ _type_ (I915_SAMPLE_QUEUED is
 62	 * bit 0), and higher bits correspond to other events (for instance
 63	 * I915_PMU_ACTUAL_FREQUENCY is bit 16 etc).
 64	 *
 65	 * In other words, low 16 bits are not per engine but per engine
 66	 * sampler type, while the upper bits are directly mapped to other
 67	 * event types.
 68	 */
 69	u64 enable;
 70
 71	/**
 72	 * @timer_last:
 73	 *
 74	 * Timestmap of the previous timer invocation.
 75	 */
 76	ktime_t timer_last;
 77
 78	/**
 79	 * @enable_count: Reference counts for the enabled events.
 80	 *
 81	 * Array indices are mapped in the same way as bits in the @enable field
 82	 * and they are used to control sampling on/off when multiple clients
 83	 * are using the PMU API.
 84	 */
 85	unsigned int enable_count[I915_PMU_MASK_BITS];
 86	/**
 87	 * @timer_enabled: Should the internal sampling timer be running.
 88	 */
 89	bool timer_enabled;
 90	/**
 91	 * @sample: Current and previous (raw) counters for sampling events.
 92	 *
 93	 * These counters are updated from the i915 PMU sampling timer.
 94	 *
 95	 * Only global counters are held here, while the per-engine ones are in
 96	 * struct intel_engine_cs.
 97	 */
 98	struct i915_pmu_sample sample[__I915_NUM_PMU_SAMPLERS];
 99	/**
100	 * @suspended_time_last: Cached suspend time from PM core.
101	 */
102	u64 suspended_time_last;
103	/**
104	 * @i915_attr: Memory block holding device attributes.
105	 */
106	void *i915_attr;
107	/**
108	 * @pmu_attr: Memory block holding device attributes.
109	 */
110	void *pmu_attr;
111};
112
113#ifdef CONFIG_PERF_EVENTS
114void i915_pmu_register(struct drm_i915_private *i915);
115void i915_pmu_unregister(struct drm_i915_private *i915);
116void i915_pmu_gt_parked(struct drm_i915_private *i915);
117void i915_pmu_gt_unparked(struct drm_i915_private *i915);
118#else
119static inline void i915_pmu_register(struct drm_i915_private *i915) {}
120static inline void i915_pmu_unregister(struct drm_i915_private *i915) {}
121static inline void i915_pmu_gt_parked(struct drm_i915_private *i915) {}
122static inline void i915_pmu_gt_unparked(struct drm_i915_private *i915) {}
123#endif
124
125#endif