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1// SPDX-License-Identifier: GPL-2.0-only
2/**************************************************************************
3 * Copyright (c) 2011, Intel Corporation.
4 * All Rights Reserved.
5 *
6 **************************************************************************/
7
8#include <linux/backlight.h>
9#include <linux/delay.h>
10#include <linux/dmi.h>
11#include <linux/module.h>
12
13#include <asm/intel-mid.h>
14#include <asm/intel_scu_ipc.h>
15
16#include <drm/drm.h>
17
18#include "intel_bios.h"
19#include "mid_bios.h"
20#include "psb_drv.h"
21#include "psb_intel_reg.h"
22#include "psb_reg.h"
23
24static int oaktrail_output_init(struct drm_device *dev)
25{
26 struct drm_psb_private *dev_priv = dev->dev_private;
27 if (dev_priv->iLVDS_enable)
28 oaktrail_lvds_init(dev, &dev_priv->mode_dev);
29 else
30 dev_err(dev->dev, "DSI is not supported\n");
31 if (dev_priv->hdmi_priv)
32 oaktrail_hdmi_init(dev, &dev_priv->mode_dev);
33
34 psb_intel_sdvo_init(dev, SDVOB);
35
36 return 0;
37}
38
39/*
40 * Provide the low level interfaces for the Moorestown backlight
41 */
42
43#ifdef CONFIG_BACKLIGHT_CLASS_DEVICE
44
45#define MRST_BLC_MAX_PWM_REG_FREQ 0xFFFF
46#define BLC_PWM_PRECISION_FACTOR 100 /* 10000000 */
47#define BLC_PWM_FREQ_CALC_CONSTANT 32
48#define MHz 1000000
49#define BLC_ADJUSTMENT_MAX 100
50
51static struct backlight_device *oaktrail_backlight_device;
52static int oaktrail_brightness;
53
54static int oaktrail_set_brightness(struct backlight_device *bd)
55{
56 struct drm_device *dev = bl_get_data(oaktrail_backlight_device);
57 struct drm_psb_private *dev_priv = dev->dev_private;
58 int level = bd->props.brightness;
59 u32 blc_pwm_ctl;
60 u32 max_pwm_blc;
61
62 /* Percentage 1-100% being valid */
63 if (level < 1)
64 level = 1;
65
66 if (gma_power_begin(dev, 0)) {
67 /* Calculate and set the brightness value */
68 max_pwm_blc = REG_READ(BLC_PWM_CTL) >> 16;
69 blc_pwm_ctl = level * max_pwm_blc / 100;
70
71 /* Adjust the backlight level with the percent in
72 * dev_priv->blc_adj1;
73 */
74 blc_pwm_ctl = blc_pwm_ctl * dev_priv->blc_adj1;
75 blc_pwm_ctl = blc_pwm_ctl / 100;
76
77 /* Adjust the backlight level with the percent in
78 * dev_priv->blc_adj2;
79 */
80 blc_pwm_ctl = blc_pwm_ctl * dev_priv->blc_adj2;
81 blc_pwm_ctl = blc_pwm_ctl / 100;
82
83 /* force PWM bit on */
84 REG_WRITE(BLC_PWM_CTL2, (0x80000000 | REG_READ(BLC_PWM_CTL2)));
85 REG_WRITE(BLC_PWM_CTL, (max_pwm_blc << 16) | blc_pwm_ctl);
86 gma_power_end(dev);
87 }
88 oaktrail_brightness = level;
89 return 0;
90}
91
92static int oaktrail_get_brightness(struct backlight_device *bd)
93{
94 /* return locally cached var instead of HW read (due to DPST etc.) */
95 /* FIXME: ideally return actual value in case firmware fiddled with
96 it */
97 return oaktrail_brightness;
98}
99
100static int device_backlight_init(struct drm_device *dev)
101{
102 struct drm_psb_private *dev_priv = dev->dev_private;
103 unsigned long core_clock;
104 u16 bl_max_freq;
105 uint32_t value;
106 uint32_t blc_pwm_precision_factor;
107
108 dev_priv->blc_adj1 = BLC_ADJUSTMENT_MAX;
109 dev_priv->blc_adj2 = BLC_ADJUSTMENT_MAX;
110 bl_max_freq = 256;
111 /* this needs to be set elsewhere */
112 blc_pwm_precision_factor = BLC_PWM_PRECISION_FACTOR;
113
114 core_clock = dev_priv->core_freq;
115
116 value = (core_clock * MHz) / BLC_PWM_FREQ_CALC_CONSTANT;
117 value *= blc_pwm_precision_factor;
118 value /= bl_max_freq;
119 value /= blc_pwm_precision_factor;
120
121 if (value > (unsigned long long)MRST_BLC_MAX_PWM_REG_FREQ)
122 return -ERANGE;
123
124 if (gma_power_begin(dev, false)) {
125 REG_WRITE(BLC_PWM_CTL2, (0x80000000 | REG_READ(BLC_PWM_CTL2)));
126 REG_WRITE(BLC_PWM_CTL, value | (value << 16));
127 gma_power_end(dev);
128 }
129 return 0;
130}
131
132static const struct backlight_ops oaktrail_ops = {
133 .get_brightness = oaktrail_get_brightness,
134 .update_status = oaktrail_set_brightness,
135};
136
137static int oaktrail_backlight_init(struct drm_device *dev)
138{
139 struct drm_psb_private *dev_priv = dev->dev_private;
140 int ret;
141 struct backlight_properties props;
142
143 memset(&props, 0, sizeof(struct backlight_properties));
144 props.max_brightness = 100;
145 props.type = BACKLIGHT_PLATFORM;
146
147 oaktrail_backlight_device = backlight_device_register("oaktrail-bl",
148 NULL, (void *)dev, &oaktrail_ops, &props);
149
150 if (IS_ERR(oaktrail_backlight_device))
151 return PTR_ERR(oaktrail_backlight_device);
152
153 ret = device_backlight_init(dev);
154 if (ret < 0) {
155 backlight_device_unregister(oaktrail_backlight_device);
156 return ret;
157 }
158 oaktrail_backlight_device->props.brightness = 100;
159 oaktrail_backlight_device->props.max_brightness = 100;
160 backlight_update_status(oaktrail_backlight_device);
161 dev_priv->backlight_device = oaktrail_backlight_device;
162 return 0;
163}
164
165#endif
166
167/*
168 * Provide the Moorestown specific chip logic and low level methods
169 * for power management
170 */
171
172/**
173 * oaktrail_save_display_registers - save registers lost on suspend
174 * @dev: our DRM device
175 *
176 * Save the state we need in order to be able to restore the interface
177 * upon resume from suspend
178 */
179static int oaktrail_save_display_registers(struct drm_device *dev)
180{
181 struct drm_psb_private *dev_priv = dev->dev_private;
182 struct psb_save_area *regs = &dev_priv->regs;
183 struct psb_pipe *p = ®s->pipe[0];
184 int i;
185 u32 pp_stat;
186
187 /* Display arbitration control + watermarks */
188 regs->psb.saveDSPARB = PSB_RVDC32(DSPARB);
189 regs->psb.saveDSPFW1 = PSB_RVDC32(DSPFW1);
190 regs->psb.saveDSPFW2 = PSB_RVDC32(DSPFW2);
191 regs->psb.saveDSPFW3 = PSB_RVDC32(DSPFW3);
192 regs->psb.saveDSPFW4 = PSB_RVDC32(DSPFW4);
193 regs->psb.saveDSPFW5 = PSB_RVDC32(DSPFW5);
194 regs->psb.saveDSPFW6 = PSB_RVDC32(DSPFW6);
195 regs->psb.saveCHICKENBIT = PSB_RVDC32(DSPCHICKENBIT);
196
197 /* Pipe & plane A info */
198 p->conf = PSB_RVDC32(PIPEACONF);
199 p->src = PSB_RVDC32(PIPEASRC);
200 p->fp0 = PSB_RVDC32(MRST_FPA0);
201 p->fp1 = PSB_RVDC32(MRST_FPA1);
202 p->dpll = PSB_RVDC32(MRST_DPLL_A);
203 p->htotal = PSB_RVDC32(HTOTAL_A);
204 p->hblank = PSB_RVDC32(HBLANK_A);
205 p->hsync = PSB_RVDC32(HSYNC_A);
206 p->vtotal = PSB_RVDC32(VTOTAL_A);
207 p->vblank = PSB_RVDC32(VBLANK_A);
208 p->vsync = PSB_RVDC32(VSYNC_A);
209 regs->psb.saveBCLRPAT_A = PSB_RVDC32(BCLRPAT_A);
210 p->cntr = PSB_RVDC32(DSPACNTR);
211 p->stride = PSB_RVDC32(DSPASTRIDE);
212 p->addr = PSB_RVDC32(DSPABASE);
213 p->surf = PSB_RVDC32(DSPASURF);
214 p->linoff = PSB_RVDC32(DSPALINOFF);
215 p->tileoff = PSB_RVDC32(DSPATILEOFF);
216
217 /* Save cursor regs */
218 regs->psb.saveDSPACURSOR_CTRL = PSB_RVDC32(CURACNTR);
219 regs->psb.saveDSPACURSOR_BASE = PSB_RVDC32(CURABASE);
220 regs->psb.saveDSPACURSOR_POS = PSB_RVDC32(CURAPOS);
221
222 /* Save palette (gamma) */
223 for (i = 0; i < 256; i++)
224 p->palette[i] = PSB_RVDC32(PALETTE_A + (i << 2));
225
226 if (dev_priv->hdmi_priv)
227 oaktrail_hdmi_save(dev);
228
229 /* Save performance state */
230 regs->psb.savePERF_MODE = PSB_RVDC32(MRST_PERF_MODE);
231
232 /* LVDS state */
233 regs->psb.savePP_CONTROL = PSB_RVDC32(PP_CONTROL);
234 regs->psb.savePFIT_PGM_RATIOS = PSB_RVDC32(PFIT_PGM_RATIOS);
235 regs->psb.savePFIT_AUTO_RATIOS = PSB_RVDC32(PFIT_AUTO_RATIOS);
236 regs->saveBLC_PWM_CTL = PSB_RVDC32(BLC_PWM_CTL);
237 regs->saveBLC_PWM_CTL2 = PSB_RVDC32(BLC_PWM_CTL2);
238 regs->psb.saveLVDS = PSB_RVDC32(LVDS);
239 regs->psb.savePFIT_CONTROL = PSB_RVDC32(PFIT_CONTROL);
240 regs->psb.savePP_ON_DELAYS = PSB_RVDC32(LVDSPP_ON);
241 regs->psb.savePP_OFF_DELAYS = PSB_RVDC32(LVDSPP_OFF);
242 regs->psb.savePP_DIVISOR = PSB_RVDC32(PP_CYCLE);
243
244 /* HW overlay */
245 regs->psb.saveOV_OVADD = PSB_RVDC32(OV_OVADD);
246 regs->psb.saveOV_OGAMC0 = PSB_RVDC32(OV_OGAMC0);
247 regs->psb.saveOV_OGAMC1 = PSB_RVDC32(OV_OGAMC1);
248 regs->psb.saveOV_OGAMC2 = PSB_RVDC32(OV_OGAMC2);
249 regs->psb.saveOV_OGAMC3 = PSB_RVDC32(OV_OGAMC3);
250 regs->psb.saveOV_OGAMC4 = PSB_RVDC32(OV_OGAMC4);
251 regs->psb.saveOV_OGAMC5 = PSB_RVDC32(OV_OGAMC5);
252
253 /* DPST registers */
254 regs->psb.saveHISTOGRAM_INT_CONTROL_REG =
255 PSB_RVDC32(HISTOGRAM_INT_CONTROL);
256 regs->psb.saveHISTOGRAM_LOGIC_CONTROL_REG =
257 PSB_RVDC32(HISTOGRAM_LOGIC_CONTROL);
258 regs->psb.savePWM_CONTROL_LOGIC = PSB_RVDC32(PWM_CONTROL_LOGIC);
259
260 if (dev_priv->iLVDS_enable) {
261 /* Shut down the panel */
262 PSB_WVDC32(0, PP_CONTROL);
263
264 do {
265 pp_stat = PSB_RVDC32(PP_STATUS);
266 } while (pp_stat & 0x80000000);
267
268 /* Turn off the plane */
269 PSB_WVDC32(0x58000000, DSPACNTR);
270 /* Trigger the plane disable */
271 PSB_WVDC32(0, DSPASURF);
272
273 /* Wait ~4 ticks */
274 msleep(4);
275
276 /* Turn off pipe */
277 PSB_WVDC32(0x0, PIPEACONF);
278 /* Wait ~8 ticks */
279 msleep(8);
280
281 /* Turn off PLLs */
282 PSB_WVDC32(0, MRST_DPLL_A);
283 }
284 return 0;
285}
286
287/**
288 * oaktrail_restore_display_registers - restore lost register state
289 * @dev: our DRM device
290 *
291 * Restore register state that was lost during suspend and resume.
292 */
293static int oaktrail_restore_display_registers(struct drm_device *dev)
294{
295 struct drm_psb_private *dev_priv = dev->dev_private;
296 struct psb_save_area *regs = &dev_priv->regs;
297 struct psb_pipe *p = ®s->pipe[0];
298 u32 pp_stat;
299 int i;
300
301 /* Display arbitration + watermarks */
302 PSB_WVDC32(regs->psb.saveDSPARB, DSPARB);
303 PSB_WVDC32(regs->psb.saveDSPFW1, DSPFW1);
304 PSB_WVDC32(regs->psb.saveDSPFW2, DSPFW2);
305 PSB_WVDC32(regs->psb.saveDSPFW3, DSPFW3);
306 PSB_WVDC32(regs->psb.saveDSPFW4, DSPFW4);
307 PSB_WVDC32(regs->psb.saveDSPFW5, DSPFW5);
308 PSB_WVDC32(regs->psb.saveDSPFW6, DSPFW6);
309 PSB_WVDC32(regs->psb.saveCHICKENBIT, DSPCHICKENBIT);
310
311 /* Make sure VGA plane is off. it initializes to on after reset!*/
312 PSB_WVDC32(0x80000000, VGACNTRL);
313
314 /* set the plls */
315 PSB_WVDC32(p->fp0, MRST_FPA0);
316 PSB_WVDC32(p->fp1, MRST_FPA1);
317
318 /* Actually enable it */
319 PSB_WVDC32(p->dpll, MRST_DPLL_A);
320 udelay(150);
321
322 /* Restore mode */
323 PSB_WVDC32(p->htotal, HTOTAL_A);
324 PSB_WVDC32(p->hblank, HBLANK_A);
325 PSB_WVDC32(p->hsync, HSYNC_A);
326 PSB_WVDC32(p->vtotal, VTOTAL_A);
327 PSB_WVDC32(p->vblank, VBLANK_A);
328 PSB_WVDC32(p->vsync, VSYNC_A);
329 PSB_WVDC32(p->src, PIPEASRC);
330 PSB_WVDC32(regs->psb.saveBCLRPAT_A, BCLRPAT_A);
331
332 /* Restore performance mode*/
333 PSB_WVDC32(regs->psb.savePERF_MODE, MRST_PERF_MODE);
334
335 /* Enable the pipe*/
336 if (dev_priv->iLVDS_enable)
337 PSB_WVDC32(p->conf, PIPEACONF);
338
339 /* Set up the plane*/
340 PSB_WVDC32(p->linoff, DSPALINOFF);
341 PSB_WVDC32(p->stride, DSPASTRIDE);
342 PSB_WVDC32(p->tileoff, DSPATILEOFF);
343
344 /* Enable the plane */
345 PSB_WVDC32(p->cntr, DSPACNTR);
346 PSB_WVDC32(p->surf, DSPASURF);
347
348 /* Enable Cursor A */
349 PSB_WVDC32(regs->psb.saveDSPACURSOR_CTRL, CURACNTR);
350 PSB_WVDC32(regs->psb.saveDSPACURSOR_POS, CURAPOS);
351 PSB_WVDC32(regs->psb.saveDSPACURSOR_BASE, CURABASE);
352
353 /* Restore palette (gamma) */
354 for (i = 0; i < 256; i++)
355 PSB_WVDC32(p->palette[i], PALETTE_A + (i << 2));
356
357 if (dev_priv->hdmi_priv)
358 oaktrail_hdmi_restore(dev);
359
360 if (dev_priv->iLVDS_enable) {
361 PSB_WVDC32(regs->saveBLC_PWM_CTL2, BLC_PWM_CTL2);
362 PSB_WVDC32(regs->psb.saveLVDS, LVDS); /*port 61180h*/
363 PSB_WVDC32(regs->psb.savePFIT_CONTROL, PFIT_CONTROL);
364 PSB_WVDC32(regs->psb.savePFIT_PGM_RATIOS, PFIT_PGM_RATIOS);
365 PSB_WVDC32(regs->psb.savePFIT_AUTO_RATIOS, PFIT_AUTO_RATIOS);
366 PSB_WVDC32(regs->saveBLC_PWM_CTL, BLC_PWM_CTL);
367 PSB_WVDC32(regs->psb.savePP_ON_DELAYS, LVDSPP_ON);
368 PSB_WVDC32(regs->psb.savePP_OFF_DELAYS, LVDSPP_OFF);
369 PSB_WVDC32(regs->psb.savePP_DIVISOR, PP_CYCLE);
370 PSB_WVDC32(regs->psb.savePP_CONTROL, PP_CONTROL);
371 }
372
373 /* Wait for cycle delay */
374 do {
375 pp_stat = PSB_RVDC32(PP_STATUS);
376 } while (pp_stat & 0x08000000);
377
378 /* Wait for panel power up */
379 do {
380 pp_stat = PSB_RVDC32(PP_STATUS);
381 } while (pp_stat & 0x10000000);
382
383 /* Restore HW overlay */
384 PSB_WVDC32(regs->psb.saveOV_OVADD, OV_OVADD);
385 PSB_WVDC32(regs->psb.saveOV_OGAMC0, OV_OGAMC0);
386 PSB_WVDC32(regs->psb.saveOV_OGAMC1, OV_OGAMC1);
387 PSB_WVDC32(regs->psb.saveOV_OGAMC2, OV_OGAMC2);
388 PSB_WVDC32(regs->psb.saveOV_OGAMC3, OV_OGAMC3);
389 PSB_WVDC32(regs->psb.saveOV_OGAMC4, OV_OGAMC4);
390 PSB_WVDC32(regs->psb.saveOV_OGAMC5, OV_OGAMC5);
391
392 /* DPST registers */
393 PSB_WVDC32(regs->psb.saveHISTOGRAM_INT_CONTROL_REG,
394 HISTOGRAM_INT_CONTROL);
395 PSB_WVDC32(regs->psb.saveHISTOGRAM_LOGIC_CONTROL_REG,
396 HISTOGRAM_LOGIC_CONTROL);
397 PSB_WVDC32(regs->psb.savePWM_CONTROL_LOGIC, PWM_CONTROL_LOGIC);
398
399 return 0;
400}
401
402/**
403 * oaktrail_power_down - power down the display island
404 * @dev: our DRM device
405 *
406 * Power down the display interface of our device
407 */
408static int oaktrail_power_down(struct drm_device *dev)
409{
410 struct drm_psb_private *dev_priv = dev->dev_private;
411 u32 pwr_mask ;
412 u32 pwr_sts;
413
414 pwr_mask = PSB_PWRGT_DISPLAY_MASK;
415 outl(pwr_mask, dev_priv->ospm_base + PSB_PM_SSC);
416
417 while (true) {
418 pwr_sts = inl(dev_priv->ospm_base + PSB_PM_SSS);
419 if ((pwr_sts & pwr_mask) == pwr_mask)
420 break;
421 else
422 udelay(10);
423 }
424 return 0;
425}
426
427/*
428 * oaktrail_power_up
429 *
430 * Restore power to the specified island(s) (powergating)
431 */
432static int oaktrail_power_up(struct drm_device *dev)
433{
434 struct drm_psb_private *dev_priv = dev->dev_private;
435 u32 pwr_mask = PSB_PWRGT_DISPLAY_MASK;
436 u32 pwr_sts, pwr_cnt;
437
438 pwr_cnt = inl(dev_priv->ospm_base + PSB_PM_SSC);
439 pwr_cnt &= ~pwr_mask;
440 outl(pwr_cnt, (dev_priv->ospm_base + PSB_PM_SSC));
441
442 while (true) {
443 pwr_sts = inl(dev_priv->ospm_base + PSB_PM_SSS);
444 if ((pwr_sts & pwr_mask) == 0)
445 break;
446 else
447 udelay(10);
448 }
449 return 0;
450}
451
452/* Oaktrail */
453static const struct psb_offset oaktrail_regmap[2] = {
454 {
455 .fp0 = MRST_FPA0,
456 .fp1 = MRST_FPA1,
457 .cntr = DSPACNTR,
458 .conf = PIPEACONF,
459 .src = PIPEASRC,
460 .dpll = MRST_DPLL_A,
461 .htotal = HTOTAL_A,
462 .hblank = HBLANK_A,
463 .hsync = HSYNC_A,
464 .vtotal = VTOTAL_A,
465 .vblank = VBLANK_A,
466 .vsync = VSYNC_A,
467 .stride = DSPASTRIDE,
468 .size = DSPASIZE,
469 .pos = DSPAPOS,
470 .surf = DSPASURF,
471 .addr = MRST_DSPABASE,
472 .base = MRST_DSPABASE,
473 .status = PIPEASTAT,
474 .linoff = DSPALINOFF,
475 .tileoff = DSPATILEOFF,
476 .palette = PALETTE_A,
477 },
478 {
479 .fp0 = FPB0,
480 .fp1 = FPB1,
481 .cntr = DSPBCNTR,
482 .conf = PIPEBCONF,
483 .src = PIPEBSRC,
484 .dpll = DPLL_B,
485 .htotal = HTOTAL_B,
486 .hblank = HBLANK_B,
487 .hsync = HSYNC_B,
488 .vtotal = VTOTAL_B,
489 .vblank = VBLANK_B,
490 .vsync = VSYNC_B,
491 .stride = DSPBSTRIDE,
492 .size = DSPBSIZE,
493 .pos = DSPBPOS,
494 .surf = DSPBSURF,
495 .addr = DSPBBASE,
496 .base = DSPBBASE,
497 .status = PIPEBSTAT,
498 .linoff = DSPBLINOFF,
499 .tileoff = DSPBTILEOFF,
500 .palette = PALETTE_B,
501 },
502};
503
504static int oaktrail_chip_setup(struct drm_device *dev)
505{
506 struct drm_psb_private *dev_priv = dev->dev_private;
507 int ret;
508
509 if (pci_enable_msi(dev->pdev))
510 dev_warn(dev->dev, "Enabling MSI failed!\n");
511
512 dev_priv->regmap = oaktrail_regmap;
513
514 ret = mid_chip_setup(dev);
515 if (ret < 0)
516 return ret;
517 if (!dev_priv->has_gct) {
518 /* Now pull the BIOS data */
519 psb_intel_opregion_init(dev);
520 psb_intel_init_bios(dev);
521 }
522 gma_intel_setup_gmbus(dev);
523 oaktrail_hdmi_setup(dev);
524 return 0;
525}
526
527static void oaktrail_teardown(struct drm_device *dev)
528{
529 struct drm_psb_private *dev_priv = dev->dev_private;
530
531 gma_intel_teardown_gmbus(dev);
532 oaktrail_hdmi_teardown(dev);
533 if (!dev_priv->has_gct)
534 psb_intel_destroy_bios(dev);
535}
536
537const struct psb_ops oaktrail_chip_ops = {
538 .name = "Oaktrail",
539 .accel_2d = 1,
540 .pipes = 2,
541 .crtcs = 2,
542 .hdmi_mask = (1 << 1),
543 .lvds_mask = (1 << 0),
544 .sdvo_mask = (1 << 1),
545 .cursor_needs_phys = 0,
546 .sgx_offset = MRST_SGX_OFFSET,
547
548 .chip_setup = oaktrail_chip_setup,
549 .chip_teardown = oaktrail_teardown,
550 .crtc_helper = &oaktrail_helper_funcs,
551 .crtc_funcs = &psb_intel_crtc_funcs,
552
553 .output_init = oaktrail_output_init,
554
555#ifdef CONFIG_BACKLIGHT_CLASS_DEVICE
556 .backlight_init = oaktrail_backlight_init,
557#endif
558
559 .save_regs = oaktrail_save_display_registers,
560 .restore_regs = oaktrail_restore_display_registers,
561 .save_crtc = gma_crtc_save,
562 .restore_crtc = gma_crtc_restore,
563 .power_down = oaktrail_power_down,
564 .power_up = oaktrail_power_up,
565
566 .i2c_bus = 1,
567};