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1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Samsung SoC MIPI DSI Master driver.
4 *
5 * Copyright (c) 2014 Samsung Electronics Co., Ltd
6 *
7 * Contacts: Tomasz Figa <t.figa@samsung.com>
8*/
9
10#include <linux/clk.h>
11#include <linux/delay.h>
12#include <linux/component.h>
13#include <linux/gpio/consumer.h>
14#include <linux/irq.h>
15#include <linux/of_device.h>
16#include <linux/of_gpio.h>
17#include <linux/of_graph.h>
18#include <linux/phy/phy.h>
19#include <linux/regulator/consumer.h>
20
21#include <asm/unaligned.h>
22
23#include <video/mipi_display.h>
24#include <video/videomode.h>
25
26#include <drm/drm_atomic_helper.h>
27#include <drm/drm_fb_helper.h>
28#include <drm/drm_mipi_dsi.h>
29#include <drm/drm_panel.h>
30#include <drm/drm_print.h>
31#include <drm/drm_probe_helper.h>
32
33#include "exynos_drm_crtc.h"
34#include "exynos_drm_drv.h"
35
36/* returns true iff both arguments logically differs */
37#define NEQV(a, b) (!(a) ^ !(b))
38
39/* DSIM_STATUS */
40#define DSIM_STOP_STATE_DAT(x) (((x) & 0xf) << 0)
41#define DSIM_STOP_STATE_CLK (1 << 8)
42#define DSIM_TX_READY_HS_CLK (1 << 10)
43#define DSIM_PLL_STABLE (1 << 31)
44
45/* DSIM_SWRST */
46#define DSIM_FUNCRST (1 << 16)
47#define DSIM_SWRST (1 << 0)
48
49/* DSIM_TIMEOUT */
50#define DSIM_LPDR_TIMEOUT(x) ((x) << 0)
51#define DSIM_BTA_TIMEOUT(x) ((x) << 16)
52
53/* DSIM_CLKCTRL */
54#define DSIM_ESC_PRESCALER(x) (((x) & 0xffff) << 0)
55#define DSIM_ESC_PRESCALER_MASK (0xffff << 0)
56#define DSIM_LANE_ESC_CLK_EN_CLK (1 << 19)
57#define DSIM_LANE_ESC_CLK_EN_DATA(x) (((x) & 0xf) << 20)
58#define DSIM_LANE_ESC_CLK_EN_DATA_MASK (0xf << 20)
59#define DSIM_BYTE_CLKEN (1 << 24)
60#define DSIM_BYTE_CLK_SRC(x) (((x) & 0x3) << 25)
61#define DSIM_BYTE_CLK_SRC_MASK (0x3 << 25)
62#define DSIM_PLL_BYPASS (1 << 27)
63#define DSIM_ESC_CLKEN (1 << 28)
64#define DSIM_TX_REQUEST_HSCLK (1 << 31)
65
66/* DSIM_CONFIG */
67#define DSIM_LANE_EN_CLK (1 << 0)
68#define DSIM_LANE_EN(x) (((x) & 0xf) << 1)
69#define DSIM_NUM_OF_DATA_LANE(x) (((x) & 0x3) << 5)
70#define DSIM_SUB_PIX_FORMAT(x) (((x) & 0x7) << 8)
71#define DSIM_MAIN_PIX_FORMAT_MASK (0x7 << 12)
72#define DSIM_MAIN_PIX_FORMAT_RGB888 (0x7 << 12)
73#define DSIM_MAIN_PIX_FORMAT_RGB666 (0x6 << 12)
74#define DSIM_MAIN_PIX_FORMAT_RGB666_P (0x5 << 12)
75#define DSIM_MAIN_PIX_FORMAT_RGB565 (0x4 << 12)
76#define DSIM_SUB_VC (((x) & 0x3) << 16)
77#define DSIM_MAIN_VC (((x) & 0x3) << 18)
78#define DSIM_HSA_MODE (1 << 20)
79#define DSIM_HBP_MODE (1 << 21)
80#define DSIM_HFP_MODE (1 << 22)
81#define DSIM_HSE_MODE (1 << 23)
82#define DSIM_AUTO_MODE (1 << 24)
83#define DSIM_VIDEO_MODE (1 << 25)
84#define DSIM_BURST_MODE (1 << 26)
85#define DSIM_SYNC_INFORM (1 << 27)
86#define DSIM_EOT_DISABLE (1 << 28)
87#define DSIM_MFLUSH_VS (1 << 29)
88/* This flag is valid only for exynos3250/3472/5260/5430 */
89#define DSIM_CLKLANE_STOP (1 << 30)
90
91/* DSIM_ESCMODE */
92#define DSIM_TX_TRIGGER_RST (1 << 4)
93#define DSIM_TX_LPDT_LP (1 << 6)
94#define DSIM_CMD_LPDT_LP (1 << 7)
95#define DSIM_FORCE_BTA (1 << 16)
96#define DSIM_FORCE_STOP_STATE (1 << 20)
97#define DSIM_STOP_STATE_CNT(x) (((x) & 0x7ff) << 21)
98#define DSIM_STOP_STATE_CNT_MASK (0x7ff << 21)
99
100/* DSIM_MDRESOL */
101#define DSIM_MAIN_STAND_BY (1 << 31)
102#define DSIM_MAIN_VRESOL(x, num_bits) (((x) & ((1 << (num_bits)) - 1)) << 16)
103#define DSIM_MAIN_HRESOL(x, num_bits) (((x) & ((1 << (num_bits)) - 1)) << 0)
104
105/* DSIM_MVPORCH */
106#define DSIM_CMD_ALLOW(x) ((x) << 28)
107#define DSIM_STABLE_VFP(x) ((x) << 16)
108#define DSIM_MAIN_VBP(x) ((x) << 0)
109#define DSIM_CMD_ALLOW_MASK (0xf << 28)
110#define DSIM_STABLE_VFP_MASK (0x7ff << 16)
111#define DSIM_MAIN_VBP_MASK (0x7ff << 0)
112
113/* DSIM_MHPORCH */
114#define DSIM_MAIN_HFP(x) ((x) << 16)
115#define DSIM_MAIN_HBP(x) ((x) << 0)
116#define DSIM_MAIN_HFP_MASK ((0xffff) << 16)
117#define DSIM_MAIN_HBP_MASK ((0xffff) << 0)
118
119/* DSIM_MSYNC */
120#define DSIM_MAIN_VSA(x) ((x) << 22)
121#define DSIM_MAIN_HSA(x) ((x) << 0)
122#define DSIM_MAIN_VSA_MASK ((0x3ff) << 22)
123#define DSIM_MAIN_HSA_MASK ((0xffff) << 0)
124
125/* DSIM_SDRESOL */
126#define DSIM_SUB_STANDY(x) ((x) << 31)
127#define DSIM_SUB_VRESOL(x) ((x) << 16)
128#define DSIM_SUB_HRESOL(x) ((x) << 0)
129#define DSIM_SUB_STANDY_MASK ((0x1) << 31)
130#define DSIM_SUB_VRESOL_MASK ((0x7ff) << 16)
131#define DSIM_SUB_HRESOL_MASK ((0x7ff) << 0)
132
133/* DSIM_INTSRC */
134#define DSIM_INT_PLL_STABLE (1 << 31)
135#define DSIM_INT_SW_RST_RELEASE (1 << 30)
136#define DSIM_INT_SFR_FIFO_EMPTY (1 << 29)
137#define DSIM_INT_SFR_HDR_FIFO_EMPTY (1 << 28)
138#define DSIM_INT_BTA (1 << 25)
139#define DSIM_INT_FRAME_DONE (1 << 24)
140#define DSIM_INT_RX_TIMEOUT (1 << 21)
141#define DSIM_INT_BTA_TIMEOUT (1 << 20)
142#define DSIM_INT_RX_DONE (1 << 18)
143#define DSIM_INT_RX_TE (1 << 17)
144#define DSIM_INT_RX_ACK (1 << 16)
145#define DSIM_INT_RX_ECC_ERR (1 << 15)
146#define DSIM_INT_RX_CRC_ERR (1 << 14)
147
148/* DSIM_FIFOCTRL */
149#define DSIM_RX_DATA_FULL (1 << 25)
150#define DSIM_RX_DATA_EMPTY (1 << 24)
151#define DSIM_SFR_HEADER_FULL (1 << 23)
152#define DSIM_SFR_HEADER_EMPTY (1 << 22)
153#define DSIM_SFR_PAYLOAD_FULL (1 << 21)
154#define DSIM_SFR_PAYLOAD_EMPTY (1 << 20)
155#define DSIM_I80_HEADER_FULL (1 << 19)
156#define DSIM_I80_HEADER_EMPTY (1 << 18)
157#define DSIM_I80_PAYLOAD_FULL (1 << 17)
158#define DSIM_I80_PAYLOAD_EMPTY (1 << 16)
159#define DSIM_SD_HEADER_FULL (1 << 15)
160#define DSIM_SD_HEADER_EMPTY (1 << 14)
161#define DSIM_SD_PAYLOAD_FULL (1 << 13)
162#define DSIM_SD_PAYLOAD_EMPTY (1 << 12)
163#define DSIM_MD_HEADER_FULL (1 << 11)
164#define DSIM_MD_HEADER_EMPTY (1 << 10)
165#define DSIM_MD_PAYLOAD_FULL (1 << 9)
166#define DSIM_MD_PAYLOAD_EMPTY (1 << 8)
167#define DSIM_RX_FIFO (1 << 4)
168#define DSIM_SFR_FIFO (1 << 3)
169#define DSIM_I80_FIFO (1 << 2)
170#define DSIM_SD_FIFO (1 << 1)
171#define DSIM_MD_FIFO (1 << 0)
172
173/* DSIM_PHYACCHR */
174#define DSIM_AFC_EN (1 << 14)
175#define DSIM_AFC_CTL(x) (((x) & 0x7) << 5)
176
177/* DSIM_PLLCTRL */
178#define DSIM_FREQ_BAND(x) ((x) << 24)
179#define DSIM_PLL_EN (1 << 23)
180#define DSIM_PLL_P(x) ((x) << 13)
181#define DSIM_PLL_M(x) ((x) << 4)
182#define DSIM_PLL_S(x) ((x) << 1)
183
184/* DSIM_PHYCTRL */
185#define DSIM_PHYCTRL_ULPS_EXIT(x) (((x) & 0x1ff) << 0)
186#define DSIM_PHYCTRL_B_DPHYCTL_VREG_LP (1 << 30)
187#define DSIM_PHYCTRL_B_DPHYCTL_SLEW_UP (1 << 14)
188
189/* DSIM_PHYTIMING */
190#define DSIM_PHYTIMING_LPX(x) ((x) << 8)
191#define DSIM_PHYTIMING_HS_EXIT(x) ((x) << 0)
192
193/* DSIM_PHYTIMING1 */
194#define DSIM_PHYTIMING1_CLK_PREPARE(x) ((x) << 24)
195#define DSIM_PHYTIMING1_CLK_ZERO(x) ((x) << 16)
196#define DSIM_PHYTIMING1_CLK_POST(x) ((x) << 8)
197#define DSIM_PHYTIMING1_CLK_TRAIL(x) ((x) << 0)
198
199/* DSIM_PHYTIMING2 */
200#define DSIM_PHYTIMING2_HS_PREPARE(x) ((x) << 16)
201#define DSIM_PHYTIMING2_HS_ZERO(x) ((x) << 8)
202#define DSIM_PHYTIMING2_HS_TRAIL(x) ((x) << 0)
203
204#define DSI_MAX_BUS_WIDTH 4
205#define DSI_NUM_VIRTUAL_CHANNELS 4
206#define DSI_TX_FIFO_SIZE 2048
207#define DSI_RX_FIFO_SIZE 256
208#define DSI_XFER_TIMEOUT_MS 100
209#define DSI_RX_FIFO_EMPTY 0x30800002
210
211#define OLD_SCLK_MIPI_CLK_NAME "pll_clk"
212
213static char *clk_names[5] = { "bus_clk", "sclk_mipi",
214 "phyclk_mipidphy0_bitclkdiv8", "phyclk_mipidphy0_rxclkesc0",
215 "sclk_rgb_vclk_to_dsim0" };
216
217enum exynos_dsi_transfer_type {
218 EXYNOS_DSI_TX,
219 EXYNOS_DSI_RX,
220};
221
222struct exynos_dsi_transfer {
223 struct list_head list;
224 struct completion completed;
225 int result;
226 struct mipi_dsi_packet packet;
227 u16 flags;
228 u16 tx_done;
229
230 u8 *rx_payload;
231 u16 rx_len;
232 u16 rx_done;
233};
234
235#define DSIM_STATE_ENABLED BIT(0)
236#define DSIM_STATE_INITIALIZED BIT(1)
237#define DSIM_STATE_CMD_LPM BIT(2)
238#define DSIM_STATE_VIDOUT_AVAILABLE BIT(3)
239
240struct exynos_dsi_driver_data {
241 const unsigned int *reg_ofs;
242 unsigned int plltmr_reg;
243 unsigned int has_freqband:1;
244 unsigned int has_clklane_stop:1;
245 unsigned int num_clks;
246 unsigned int max_freq;
247 unsigned int wait_for_reset;
248 unsigned int num_bits_resol;
249 const unsigned int *reg_values;
250};
251
252struct exynos_dsi {
253 struct drm_encoder encoder;
254 struct mipi_dsi_host dsi_host;
255 struct drm_connector connector;
256 struct drm_panel *panel;
257 struct drm_bridge *out_bridge;
258 struct device *dev;
259
260 void __iomem *reg_base;
261 struct phy *phy;
262 struct clk **clks;
263 struct regulator_bulk_data supplies[2];
264 int irq;
265 int te_gpio;
266
267 u32 pll_clk_rate;
268 u32 burst_clk_rate;
269 u32 esc_clk_rate;
270 u32 lanes;
271 u32 mode_flags;
272 u32 format;
273
274 int state;
275 struct drm_property *brightness;
276 struct completion completed;
277
278 spinlock_t transfer_lock; /* protects transfer_list */
279 struct list_head transfer_list;
280
281 const struct exynos_dsi_driver_data *driver_data;
282 struct device_node *in_bridge_node;
283};
284
285#define host_to_dsi(host) container_of(host, struct exynos_dsi, dsi_host)
286#define connector_to_dsi(c) container_of(c, struct exynos_dsi, connector)
287
288static inline struct exynos_dsi *encoder_to_dsi(struct drm_encoder *e)
289{
290 return container_of(e, struct exynos_dsi, encoder);
291}
292
293enum reg_idx {
294 DSIM_STATUS_REG, /* Status register */
295 DSIM_SWRST_REG, /* Software reset register */
296 DSIM_CLKCTRL_REG, /* Clock control register */
297 DSIM_TIMEOUT_REG, /* Time out register */
298 DSIM_CONFIG_REG, /* Configuration register */
299 DSIM_ESCMODE_REG, /* Escape mode register */
300 DSIM_MDRESOL_REG,
301 DSIM_MVPORCH_REG, /* Main display Vporch register */
302 DSIM_MHPORCH_REG, /* Main display Hporch register */
303 DSIM_MSYNC_REG, /* Main display sync area register */
304 DSIM_INTSRC_REG, /* Interrupt source register */
305 DSIM_INTMSK_REG, /* Interrupt mask register */
306 DSIM_PKTHDR_REG, /* Packet Header FIFO register */
307 DSIM_PAYLOAD_REG, /* Payload FIFO register */
308 DSIM_RXFIFO_REG, /* Read FIFO register */
309 DSIM_FIFOCTRL_REG, /* FIFO status and control register */
310 DSIM_PLLCTRL_REG, /* PLL control register */
311 DSIM_PHYCTRL_REG,
312 DSIM_PHYTIMING_REG,
313 DSIM_PHYTIMING1_REG,
314 DSIM_PHYTIMING2_REG,
315 NUM_REGS
316};
317
318static inline void exynos_dsi_write(struct exynos_dsi *dsi, enum reg_idx idx,
319 u32 val)
320{
321
322 writel(val, dsi->reg_base + dsi->driver_data->reg_ofs[idx]);
323}
324
325static inline u32 exynos_dsi_read(struct exynos_dsi *dsi, enum reg_idx idx)
326{
327 return readl(dsi->reg_base + dsi->driver_data->reg_ofs[idx]);
328}
329
330static const unsigned int exynos_reg_ofs[] = {
331 [DSIM_STATUS_REG] = 0x00,
332 [DSIM_SWRST_REG] = 0x04,
333 [DSIM_CLKCTRL_REG] = 0x08,
334 [DSIM_TIMEOUT_REG] = 0x0c,
335 [DSIM_CONFIG_REG] = 0x10,
336 [DSIM_ESCMODE_REG] = 0x14,
337 [DSIM_MDRESOL_REG] = 0x18,
338 [DSIM_MVPORCH_REG] = 0x1c,
339 [DSIM_MHPORCH_REG] = 0x20,
340 [DSIM_MSYNC_REG] = 0x24,
341 [DSIM_INTSRC_REG] = 0x2c,
342 [DSIM_INTMSK_REG] = 0x30,
343 [DSIM_PKTHDR_REG] = 0x34,
344 [DSIM_PAYLOAD_REG] = 0x38,
345 [DSIM_RXFIFO_REG] = 0x3c,
346 [DSIM_FIFOCTRL_REG] = 0x44,
347 [DSIM_PLLCTRL_REG] = 0x4c,
348 [DSIM_PHYCTRL_REG] = 0x5c,
349 [DSIM_PHYTIMING_REG] = 0x64,
350 [DSIM_PHYTIMING1_REG] = 0x68,
351 [DSIM_PHYTIMING2_REG] = 0x6c,
352};
353
354static const unsigned int exynos5433_reg_ofs[] = {
355 [DSIM_STATUS_REG] = 0x04,
356 [DSIM_SWRST_REG] = 0x0C,
357 [DSIM_CLKCTRL_REG] = 0x10,
358 [DSIM_TIMEOUT_REG] = 0x14,
359 [DSIM_CONFIG_REG] = 0x18,
360 [DSIM_ESCMODE_REG] = 0x1C,
361 [DSIM_MDRESOL_REG] = 0x20,
362 [DSIM_MVPORCH_REG] = 0x24,
363 [DSIM_MHPORCH_REG] = 0x28,
364 [DSIM_MSYNC_REG] = 0x2C,
365 [DSIM_INTSRC_REG] = 0x34,
366 [DSIM_INTMSK_REG] = 0x38,
367 [DSIM_PKTHDR_REG] = 0x3C,
368 [DSIM_PAYLOAD_REG] = 0x40,
369 [DSIM_RXFIFO_REG] = 0x44,
370 [DSIM_FIFOCTRL_REG] = 0x4C,
371 [DSIM_PLLCTRL_REG] = 0x94,
372 [DSIM_PHYCTRL_REG] = 0xA4,
373 [DSIM_PHYTIMING_REG] = 0xB4,
374 [DSIM_PHYTIMING1_REG] = 0xB8,
375 [DSIM_PHYTIMING2_REG] = 0xBC,
376};
377
378enum reg_value_idx {
379 RESET_TYPE,
380 PLL_TIMER,
381 STOP_STATE_CNT,
382 PHYCTRL_ULPS_EXIT,
383 PHYCTRL_VREG_LP,
384 PHYCTRL_SLEW_UP,
385 PHYTIMING_LPX,
386 PHYTIMING_HS_EXIT,
387 PHYTIMING_CLK_PREPARE,
388 PHYTIMING_CLK_ZERO,
389 PHYTIMING_CLK_POST,
390 PHYTIMING_CLK_TRAIL,
391 PHYTIMING_HS_PREPARE,
392 PHYTIMING_HS_ZERO,
393 PHYTIMING_HS_TRAIL
394};
395
396static const unsigned int reg_values[] = {
397 [RESET_TYPE] = DSIM_SWRST,
398 [PLL_TIMER] = 500,
399 [STOP_STATE_CNT] = 0xf,
400 [PHYCTRL_ULPS_EXIT] = DSIM_PHYCTRL_ULPS_EXIT(0x0af),
401 [PHYCTRL_VREG_LP] = 0,
402 [PHYCTRL_SLEW_UP] = 0,
403 [PHYTIMING_LPX] = DSIM_PHYTIMING_LPX(0x06),
404 [PHYTIMING_HS_EXIT] = DSIM_PHYTIMING_HS_EXIT(0x0b),
405 [PHYTIMING_CLK_PREPARE] = DSIM_PHYTIMING1_CLK_PREPARE(0x07),
406 [PHYTIMING_CLK_ZERO] = DSIM_PHYTIMING1_CLK_ZERO(0x27),
407 [PHYTIMING_CLK_POST] = DSIM_PHYTIMING1_CLK_POST(0x0d),
408 [PHYTIMING_CLK_TRAIL] = DSIM_PHYTIMING1_CLK_TRAIL(0x08),
409 [PHYTIMING_HS_PREPARE] = DSIM_PHYTIMING2_HS_PREPARE(0x09),
410 [PHYTIMING_HS_ZERO] = DSIM_PHYTIMING2_HS_ZERO(0x0d),
411 [PHYTIMING_HS_TRAIL] = DSIM_PHYTIMING2_HS_TRAIL(0x0b),
412};
413
414static const unsigned int exynos5422_reg_values[] = {
415 [RESET_TYPE] = DSIM_SWRST,
416 [PLL_TIMER] = 500,
417 [STOP_STATE_CNT] = 0xf,
418 [PHYCTRL_ULPS_EXIT] = DSIM_PHYCTRL_ULPS_EXIT(0xaf),
419 [PHYCTRL_VREG_LP] = 0,
420 [PHYCTRL_SLEW_UP] = 0,
421 [PHYTIMING_LPX] = DSIM_PHYTIMING_LPX(0x08),
422 [PHYTIMING_HS_EXIT] = DSIM_PHYTIMING_HS_EXIT(0x0d),
423 [PHYTIMING_CLK_PREPARE] = DSIM_PHYTIMING1_CLK_PREPARE(0x09),
424 [PHYTIMING_CLK_ZERO] = DSIM_PHYTIMING1_CLK_ZERO(0x30),
425 [PHYTIMING_CLK_POST] = DSIM_PHYTIMING1_CLK_POST(0x0e),
426 [PHYTIMING_CLK_TRAIL] = DSIM_PHYTIMING1_CLK_TRAIL(0x0a),
427 [PHYTIMING_HS_PREPARE] = DSIM_PHYTIMING2_HS_PREPARE(0x0c),
428 [PHYTIMING_HS_ZERO] = DSIM_PHYTIMING2_HS_ZERO(0x11),
429 [PHYTIMING_HS_TRAIL] = DSIM_PHYTIMING2_HS_TRAIL(0x0d),
430};
431
432static const unsigned int exynos5433_reg_values[] = {
433 [RESET_TYPE] = DSIM_FUNCRST,
434 [PLL_TIMER] = 22200,
435 [STOP_STATE_CNT] = 0xa,
436 [PHYCTRL_ULPS_EXIT] = DSIM_PHYCTRL_ULPS_EXIT(0x190),
437 [PHYCTRL_VREG_LP] = DSIM_PHYCTRL_B_DPHYCTL_VREG_LP,
438 [PHYCTRL_SLEW_UP] = DSIM_PHYCTRL_B_DPHYCTL_SLEW_UP,
439 [PHYTIMING_LPX] = DSIM_PHYTIMING_LPX(0x07),
440 [PHYTIMING_HS_EXIT] = DSIM_PHYTIMING_HS_EXIT(0x0c),
441 [PHYTIMING_CLK_PREPARE] = DSIM_PHYTIMING1_CLK_PREPARE(0x09),
442 [PHYTIMING_CLK_ZERO] = DSIM_PHYTIMING1_CLK_ZERO(0x2d),
443 [PHYTIMING_CLK_POST] = DSIM_PHYTIMING1_CLK_POST(0x0e),
444 [PHYTIMING_CLK_TRAIL] = DSIM_PHYTIMING1_CLK_TRAIL(0x09),
445 [PHYTIMING_HS_PREPARE] = DSIM_PHYTIMING2_HS_PREPARE(0x0b),
446 [PHYTIMING_HS_ZERO] = DSIM_PHYTIMING2_HS_ZERO(0x10),
447 [PHYTIMING_HS_TRAIL] = DSIM_PHYTIMING2_HS_TRAIL(0x0c),
448};
449
450static const struct exynos_dsi_driver_data exynos3_dsi_driver_data = {
451 .reg_ofs = exynos_reg_ofs,
452 .plltmr_reg = 0x50,
453 .has_freqband = 1,
454 .has_clklane_stop = 1,
455 .num_clks = 2,
456 .max_freq = 1000,
457 .wait_for_reset = 1,
458 .num_bits_resol = 11,
459 .reg_values = reg_values,
460};
461
462static const struct exynos_dsi_driver_data exynos4_dsi_driver_data = {
463 .reg_ofs = exynos_reg_ofs,
464 .plltmr_reg = 0x50,
465 .has_freqband = 1,
466 .has_clklane_stop = 1,
467 .num_clks = 2,
468 .max_freq = 1000,
469 .wait_for_reset = 1,
470 .num_bits_resol = 11,
471 .reg_values = reg_values,
472};
473
474static const struct exynos_dsi_driver_data exynos5_dsi_driver_data = {
475 .reg_ofs = exynos_reg_ofs,
476 .plltmr_reg = 0x58,
477 .num_clks = 2,
478 .max_freq = 1000,
479 .wait_for_reset = 1,
480 .num_bits_resol = 11,
481 .reg_values = reg_values,
482};
483
484static const struct exynos_dsi_driver_data exynos5433_dsi_driver_data = {
485 .reg_ofs = exynos5433_reg_ofs,
486 .plltmr_reg = 0xa0,
487 .has_clklane_stop = 1,
488 .num_clks = 5,
489 .max_freq = 1500,
490 .wait_for_reset = 0,
491 .num_bits_resol = 12,
492 .reg_values = exynos5433_reg_values,
493};
494
495static const struct exynos_dsi_driver_data exynos5422_dsi_driver_data = {
496 .reg_ofs = exynos5433_reg_ofs,
497 .plltmr_reg = 0xa0,
498 .has_clklane_stop = 1,
499 .num_clks = 2,
500 .max_freq = 1500,
501 .wait_for_reset = 1,
502 .num_bits_resol = 12,
503 .reg_values = exynos5422_reg_values,
504};
505
506static const struct of_device_id exynos_dsi_of_match[] = {
507 { .compatible = "samsung,exynos3250-mipi-dsi",
508 .data = &exynos3_dsi_driver_data },
509 { .compatible = "samsung,exynos4210-mipi-dsi",
510 .data = &exynos4_dsi_driver_data },
511 { .compatible = "samsung,exynos5410-mipi-dsi",
512 .data = &exynos5_dsi_driver_data },
513 { .compatible = "samsung,exynos5422-mipi-dsi",
514 .data = &exynos5422_dsi_driver_data },
515 { .compatible = "samsung,exynos5433-mipi-dsi",
516 .data = &exynos5433_dsi_driver_data },
517 { }
518};
519
520static void exynos_dsi_wait_for_reset(struct exynos_dsi *dsi)
521{
522 if (wait_for_completion_timeout(&dsi->completed, msecs_to_jiffies(300)))
523 return;
524
525 dev_err(dsi->dev, "timeout waiting for reset\n");
526}
527
528static void exynos_dsi_reset(struct exynos_dsi *dsi)
529{
530 u32 reset_val = dsi->driver_data->reg_values[RESET_TYPE];
531
532 reinit_completion(&dsi->completed);
533 exynos_dsi_write(dsi, DSIM_SWRST_REG, reset_val);
534}
535
536#ifndef MHZ
537#define MHZ (1000*1000)
538#endif
539
540static unsigned long exynos_dsi_pll_find_pms(struct exynos_dsi *dsi,
541 unsigned long fin, unsigned long fout, u8 *p, u16 *m, u8 *s)
542{
543 const struct exynos_dsi_driver_data *driver_data = dsi->driver_data;
544 unsigned long best_freq = 0;
545 u32 min_delta = 0xffffffff;
546 u8 p_min, p_max;
547 u8 _p, uninitialized_var(best_p);
548 u16 _m, uninitialized_var(best_m);
549 u8 _s, uninitialized_var(best_s);
550
551 p_min = DIV_ROUND_UP(fin, (12 * MHZ));
552 p_max = fin / (6 * MHZ);
553
554 for (_p = p_min; _p <= p_max; ++_p) {
555 for (_s = 0; _s <= 5; ++_s) {
556 u64 tmp;
557 u32 delta;
558
559 tmp = (u64)fout * (_p << _s);
560 do_div(tmp, fin);
561 _m = tmp;
562 if (_m < 41 || _m > 125)
563 continue;
564
565 tmp = (u64)_m * fin;
566 do_div(tmp, _p);
567 if (tmp < 500 * MHZ ||
568 tmp > driver_data->max_freq * MHZ)
569 continue;
570
571 tmp = (u64)_m * fin;
572 do_div(tmp, _p << _s);
573
574 delta = abs(fout - tmp);
575 if (delta < min_delta) {
576 best_p = _p;
577 best_m = _m;
578 best_s = _s;
579 min_delta = delta;
580 best_freq = tmp;
581 }
582 }
583 }
584
585 if (best_freq) {
586 *p = best_p;
587 *m = best_m;
588 *s = best_s;
589 }
590
591 return best_freq;
592}
593
594static unsigned long exynos_dsi_set_pll(struct exynos_dsi *dsi,
595 unsigned long freq)
596{
597 const struct exynos_dsi_driver_data *driver_data = dsi->driver_data;
598 unsigned long fin, fout;
599 int timeout;
600 u8 p, s;
601 u16 m;
602 u32 reg;
603
604 fin = dsi->pll_clk_rate;
605 fout = exynos_dsi_pll_find_pms(dsi, fin, freq, &p, &m, &s);
606 if (!fout) {
607 dev_err(dsi->dev,
608 "failed to find PLL PMS for requested frequency\n");
609 return 0;
610 }
611 dev_dbg(dsi->dev, "PLL freq %lu, (p %d, m %d, s %d)\n", fout, p, m, s);
612
613 writel(driver_data->reg_values[PLL_TIMER],
614 dsi->reg_base + driver_data->plltmr_reg);
615
616 reg = DSIM_PLL_EN | DSIM_PLL_P(p) | DSIM_PLL_M(m) | DSIM_PLL_S(s);
617
618 if (driver_data->has_freqband) {
619 static const unsigned long freq_bands[] = {
620 100 * MHZ, 120 * MHZ, 160 * MHZ, 200 * MHZ,
621 270 * MHZ, 320 * MHZ, 390 * MHZ, 450 * MHZ,
622 510 * MHZ, 560 * MHZ, 640 * MHZ, 690 * MHZ,
623 770 * MHZ, 870 * MHZ, 950 * MHZ,
624 };
625 int band;
626
627 for (band = 0; band < ARRAY_SIZE(freq_bands); ++band)
628 if (fout < freq_bands[band])
629 break;
630
631 dev_dbg(dsi->dev, "band %d\n", band);
632
633 reg |= DSIM_FREQ_BAND(band);
634 }
635
636 exynos_dsi_write(dsi, DSIM_PLLCTRL_REG, reg);
637
638 timeout = 1000;
639 do {
640 if (timeout-- == 0) {
641 dev_err(dsi->dev, "PLL failed to stabilize\n");
642 return 0;
643 }
644 reg = exynos_dsi_read(dsi, DSIM_STATUS_REG);
645 } while ((reg & DSIM_PLL_STABLE) == 0);
646
647 return fout;
648}
649
650static int exynos_dsi_enable_clock(struct exynos_dsi *dsi)
651{
652 unsigned long hs_clk, byte_clk, esc_clk;
653 unsigned long esc_div;
654 u32 reg;
655
656 hs_clk = exynos_dsi_set_pll(dsi, dsi->burst_clk_rate);
657 if (!hs_clk) {
658 dev_err(dsi->dev, "failed to configure DSI PLL\n");
659 return -EFAULT;
660 }
661
662 byte_clk = hs_clk / 8;
663 esc_div = DIV_ROUND_UP(byte_clk, dsi->esc_clk_rate);
664 esc_clk = byte_clk / esc_div;
665
666 if (esc_clk > 20 * MHZ) {
667 ++esc_div;
668 esc_clk = byte_clk / esc_div;
669 }
670
671 dev_dbg(dsi->dev, "hs_clk = %lu, byte_clk = %lu, esc_clk = %lu\n",
672 hs_clk, byte_clk, esc_clk);
673
674 reg = exynos_dsi_read(dsi, DSIM_CLKCTRL_REG);
675 reg &= ~(DSIM_ESC_PRESCALER_MASK | DSIM_LANE_ESC_CLK_EN_CLK
676 | DSIM_LANE_ESC_CLK_EN_DATA_MASK | DSIM_PLL_BYPASS
677 | DSIM_BYTE_CLK_SRC_MASK);
678 reg |= DSIM_ESC_CLKEN | DSIM_BYTE_CLKEN
679 | DSIM_ESC_PRESCALER(esc_div)
680 | DSIM_LANE_ESC_CLK_EN_CLK
681 | DSIM_LANE_ESC_CLK_EN_DATA(BIT(dsi->lanes) - 1)
682 | DSIM_BYTE_CLK_SRC(0)
683 | DSIM_TX_REQUEST_HSCLK;
684 exynos_dsi_write(dsi, DSIM_CLKCTRL_REG, reg);
685
686 return 0;
687}
688
689static void exynos_dsi_set_phy_ctrl(struct exynos_dsi *dsi)
690{
691 const struct exynos_dsi_driver_data *driver_data = dsi->driver_data;
692 const unsigned int *reg_values = driver_data->reg_values;
693 u32 reg;
694
695 if (driver_data->has_freqband)
696 return;
697
698 /* B D-PHY: D-PHY Master & Slave Analog Block control */
699 reg = reg_values[PHYCTRL_ULPS_EXIT] | reg_values[PHYCTRL_VREG_LP] |
700 reg_values[PHYCTRL_SLEW_UP];
701 exynos_dsi_write(dsi, DSIM_PHYCTRL_REG, reg);
702
703 /*
704 * T LPX: Transmitted length of any Low-Power state period
705 * T HS-EXIT: Time that the transmitter drives LP-11 following a HS
706 * burst
707 */
708 reg = reg_values[PHYTIMING_LPX] | reg_values[PHYTIMING_HS_EXIT];
709 exynos_dsi_write(dsi, DSIM_PHYTIMING_REG, reg);
710
711 /*
712 * T CLK-PREPARE: Time that the transmitter drives the Clock Lane LP-00
713 * Line state immediately before the HS-0 Line state starting the
714 * HS transmission
715 * T CLK-ZERO: Time that the transmitter drives the HS-0 state prior to
716 * transmitting the Clock.
717 * T CLK_POST: Time that the transmitter continues to send HS clock
718 * after the last associated Data Lane has transitioned to LP Mode
719 * Interval is defined as the period from the end of T HS-TRAIL to
720 * the beginning of T CLK-TRAIL
721 * T CLK-TRAIL: Time that the transmitter drives the HS-0 state after
722 * the last payload clock bit of a HS transmission burst
723 */
724 reg = reg_values[PHYTIMING_CLK_PREPARE] |
725 reg_values[PHYTIMING_CLK_ZERO] |
726 reg_values[PHYTIMING_CLK_POST] |
727 reg_values[PHYTIMING_CLK_TRAIL];
728
729 exynos_dsi_write(dsi, DSIM_PHYTIMING1_REG, reg);
730
731 /*
732 * T HS-PREPARE: Time that the transmitter drives the Data Lane LP-00
733 * Line state immediately before the HS-0 Line state starting the
734 * HS transmission
735 * T HS-ZERO: Time that the transmitter drives the HS-0 state prior to
736 * transmitting the Sync sequence.
737 * T HS-TRAIL: Time that the transmitter drives the flipped differential
738 * state after last payload data bit of a HS transmission burst
739 */
740 reg = reg_values[PHYTIMING_HS_PREPARE] | reg_values[PHYTIMING_HS_ZERO] |
741 reg_values[PHYTIMING_HS_TRAIL];
742 exynos_dsi_write(dsi, DSIM_PHYTIMING2_REG, reg);
743}
744
745static void exynos_dsi_disable_clock(struct exynos_dsi *dsi)
746{
747 u32 reg;
748
749 reg = exynos_dsi_read(dsi, DSIM_CLKCTRL_REG);
750 reg &= ~(DSIM_LANE_ESC_CLK_EN_CLK | DSIM_LANE_ESC_CLK_EN_DATA_MASK
751 | DSIM_ESC_CLKEN | DSIM_BYTE_CLKEN);
752 exynos_dsi_write(dsi, DSIM_CLKCTRL_REG, reg);
753
754 reg = exynos_dsi_read(dsi, DSIM_PLLCTRL_REG);
755 reg &= ~DSIM_PLL_EN;
756 exynos_dsi_write(dsi, DSIM_PLLCTRL_REG, reg);
757}
758
759static void exynos_dsi_enable_lane(struct exynos_dsi *dsi, u32 lane)
760{
761 u32 reg = exynos_dsi_read(dsi, DSIM_CONFIG_REG);
762 reg |= (DSIM_NUM_OF_DATA_LANE(dsi->lanes - 1) | DSIM_LANE_EN_CLK |
763 DSIM_LANE_EN(lane));
764 exynos_dsi_write(dsi, DSIM_CONFIG_REG, reg);
765}
766
767static int exynos_dsi_init_link(struct exynos_dsi *dsi)
768{
769 const struct exynos_dsi_driver_data *driver_data = dsi->driver_data;
770 int timeout;
771 u32 reg;
772 u32 lanes_mask;
773
774 /* Initialize FIFO pointers */
775 reg = exynos_dsi_read(dsi, DSIM_FIFOCTRL_REG);
776 reg &= ~0x1f;
777 exynos_dsi_write(dsi, DSIM_FIFOCTRL_REG, reg);
778
779 usleep_range(9000, 11000);
780
781 reg |= 0x1f;
782 exynos_dsi_write(dsi, DSIM_FIFOCTRL_REG, reg);
783 usleep_range(9000, 11000);
784
785 /* DSI configuration */
786 reg = 0;
787
788 /*
789 * The first bit of mode_flags specifies display configuration.
790 * If this bit is set[= MIPI_DSI_MODE_VIDEO], dsi will support video
791 * mode, otherwise it will support command mode.
792 */
793 if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO) {
794 reg |= DSIM_VIDEO_MODE;
795
796 /*
797 * The user manual describes that following bits are ignored in
798 * command mode.
799 */
800 if (!(dsi->mode_flags & MIPI_DSI_MODE_VSYNC_FLUSH))
801 reg |= DSIM_MFLUSH_VS;
802 if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE)
803 reg |= DSIM_SYNC_INFORM;
804 if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_BURST)
805 reg |= DSIM_BURST_MODE;
806 if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_AUTO_VERT)
807 reg |= DSIM_AUTO_MODE;
808 if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_HSE)
809 reg |= DSIM_HSE_MODE;
810 if (!(dsi->mode_flags & MIPI_DSI_MODE_VIDEO_HFP))
811 reg |= DSIM_HFP_MODE;
812 if (!(dsi->mode_flags & MIPI_DSI_MODE_VIDEO_HBP))
813 reg |= DSIM_HBP_MODE;
814 if (!(dsi->mode_flags & MIPI_DSI_MODE_VIDEO_HSA))
815 reg |= DSIM_HSA_MODE;
816 }
817
818 if (!(dsi->mode_flags & MIPI_DSI_MODE_EOT_PACKET))
819 reg |= DSIM_EOT_DISABLE;
820
821 switch (dsi->format) {
822 case MIPI_DSI_FMT_RGB888:
823 reg |= DSIM_MAIN_PIX_FORMAT_RGB888;
824 break;
825 case MIPI_DSI_FMT_RGB666:
826 reg |= DSIM_MAIN_PIX_FORMAT_RGB666;
827 break;
828 case MIPI_DSI_FMT_RGB666_PACKED:
829 reg |= DSIM_MAIN_PIX_FORMAT_RGB666_P;
830 break;
831 case MIPI_DSI_FMT_RGB565:
832 reg |= DSIM_MAIN_PIX_FORMAT_RGB565;
833 break;
834 default:
835 dev_err(dsi->dev, "invalid pixel format\n");
836 return -EINVAL;
837 }
838
839 /*
840 * Use non-continuous clock mode if the periparal wants and
841 * host controller supports
842 *
843 * In non-continous clock mode, host controller will turn off
844 * the HS clock between high-speed transmissions to reduce
845 * power consumption.
846 */
847 if (driver_data->has_clklane_stop &&
848 dsi->mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS) {
849 reg |= DSIM_CLKLANE_STOP;
850 }
851 exynos_dsi_write(dsi, DSIM_CONFIG_REG, reg);
852
853 lanes_mask = BIT(dsi->lanes) - 1;
854 exynos_dsi_enable_lane(dsi, lanes_mask);
855
856 /* Check clock and data lane state are stop state */
857 timeout = 100;
858 do {
859 if (timeout-- == 0) {
860 dev_err(dsi->dev, "waiting for bus lanes timed out\n");
861 return -EFAULT;
862 }
863
864 reg = exynos_dsi_read(dsi, DSIM_STATUS_REG);
865 if ((reg & DSIM_STOP_STATE_DAT(lanes_mask))
866 != DSIM_STOP_STATE_DAT(lanes_mask))
867 continue;
868 } while (!(reg & (DSIM_STOP_STATE_CLK | DSIM_TX_READY_HS_CLK)));
869
870 reg = exynos_dsi_read(dsi, DSIM_ESCMODE_REG);
871 reg &= ~DSIM_STOP_STATE_CNT_MASK;
872 reg |= DSIM_STOP_STATE_CNT(driver_data->reg_values[STOP_STATE_CNT]);
873 exynos_dsi_write(dsi, DSIM_ESCMODE_REG, reg);
874
875 reg = DSIM_BTA_TIMEOUT(0xff) | DSIM_LPDR_TIMEOUT(0xffff);
876 exynos_dsi_write(dsi, DSIM_TIMEOUT_REG, reg);
877
878 return 0;
879}
880
881static void exynos_dsi_set_display_mode(struct exynos_dsi *dsi)
882{
883 struct drm_display_mode *m = &dsi->encoder.crtc->state->adjusted_mode;
884 unsigned int num_bits_resol = dsi->driver_data->num_bits_resol;
885 u32 reg;
886
887 if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO) {
888 reg = DSIM_CMD_ALLOW(0xf)
889 | DSIM_STABLE_VFP(m->vsync_start - m->vdisplay)
890 | DSIM_MAIN_VBP(m->vtotal - m->vsync_end);
891 exynos_dsi_write(dsi, DSIM_MVPORCH_REG, reg);
892
893 reg = DSIM_MAIN_HFP(m->hsync_start - m->hdisplay)
894 | DSIM_MAIN_HBP(m->htotal - m->hsync_end);
895 exynos_dsi_write(dsi, DSIM_MHPORCH_REG, reg);
896
897 reg = DSIM_MAIN_VSA(m->vsync_end - m->vsync_start)
898 | DSIM_MAIN_HSA(m->hsync_end - m->hsync_start);
899 exynos_dsi_write(dsi, DSIM_MSYNC_REG, reg);
900 }
901 reg = DSIM_MAIN_HRESOL(m->hdisplay, num_bits_resol) |
902 DSIM_MAIN_VRESOL(m->vdisplay, num_bits_resol);
903
904 exynos_dsi_write(dsi, DSIM_MDRESOL_REG, reg);
905
906 dev_dbg(dsi->dev, "LCD size = %dx%d\n", m->hdisplay, m->vdisplay);
907}
908
909static void exynos_dsi_set_display_enable(struct exynos_dsi *dsi, bool enable)
910{
911 u32 reg;
912
913 reg = exynos_dsi_read(dsi, DSIM_MDRESOL_REG);
914 if (enable)
915 reg |= DSIM_MAIN_STAND_BY;
916 else
917 reg &= ~DSIM_MAIN_STAND_BY;
918 exynos_dsi_write(dsi, DSIM_MDRESOL_REG, reg);
919}
920
921static int exynos_dsi_wait_for_hdr_fifo(struct exynos_dsi *dsi)
922{
923 int timeout = 2000;
924
925 do {
926 u32 reg = exynos_dsi_read(dsi, DSIM_FIFOCTRL_REG);
927
928 if (!(reg & DSIM_SFR_HEADER_FULL))
929 return 0;
930
931 if (!cond_resched())
932 usleep_range(950, 1050);
933 } while (--timeout);
934
935 return -ETIMEDOUT;
936}
937
938static void exynos_dsi_set_cmd_lpm(struct exynos_dsi *dsi, bool lpm)
939{
940 u32 v = exynos_dsi_read(dsi, DSIM_ESCMODE_REG);
941
942 if (lpm)
943 v |= DSIM_CMD_LPDT_LP;
944 else
945 v &= ~DSIM_CMD_LPDT_LP;
946
947 exynos_dsi_write(dsi, DSIM_ESCMODE_REG, v);
948}
949
950static void exynos_dsi_force_bta(struct exynos_dsi *dsi)
951{
952 u32 v = exynos_dsi_read(dsi, DSIM_ESCMODE_REG);
953 v |= DSIM_FORCE_BTA;
954 exynos_dsi_write(dsi, DSIM_ESCMODE_REG, v);
955}
956
957static void exynos_dsi_send_to_fifo(struct exynos_dsi *dsi,
958 struct exynos_dsi_transfer *xfer)
959{
960 struct device *dev = dsi->dev;
961 struct mipi_dsi_packet *pkt = &xfer->packet;
962 const u8 *payload = pkt->payload + xfer->tx_done;
963 u16 length = pkt->payload_length - xfer->tx_done;
964 bool first = !xfer->tx_done;
965 u32 reg;
966
967 dev_dbg(dev, "< xfer %pK: tx len %u, done %u, rx len %u, done %u\n",
968 xfer, length, xfer->tx_done, xfer->rx_len, xfer->rx_done);
969
970 if (length > DSI_TX_FIFO_SIZE)
971 length = DSI_TX_FIFO_SIZE;
972
973 xfer->tx_done += length;
974
975 /* Send payload */
976 while (length >= 4) {
977 reg = get_unaligned_le32(payload);
978 exynos_dsi_write(dsi, DSIM_PAYLOAD_REG, reg);
979 payload += 4;
980 length -= 4;
981 }
982
983 reg = 0;
984 switch (length) {
985 case 3:
986 reg |= payload[2] << 16;
987 /* Fall through */
988 case 2:
989 reg |= payload[1] << 8;
990 /* Fall through */
991 case 1:
992 reg |= payload[0];
993 exynos_dsi_write(dsi, DSIM_PAYLOAD_REG, reg);
994 break;
995 }
996
997 /* Send packet header */
998 if (!first)
999 return;
1000
1001 reg = get_unaligned_le32(pkt->header);
1002 if (exynos_dsi_wait_for_hdr_fifo(dsi)) {
1003 dev_err(dev, "waiting for header FIFO timed out\n");
1004 return;
1005 }
1006
1007 if (NEQV(xfer->flags & MIPI_DSI_MSG_USE_LPM,
1008 dsi->state & DSIM_STATE_CMD_LPM)) {
1009 exynos_dsi_set_cmd_lpm(dsi, xfer->flags & MIPI_DSI_MSG_USE_LPM);
1010 dsi->state ^= DSIM_STATE_CMD_LPM;
1011 }
1012
1013 exynos_dsi_write(dsi, DSIM_PKTHDR_REG, reg);
1014
1015 if (xfer->flags & MIPI_DSI_MSG_REQ_ACK)
1016 exynos_dsi_force_bta(dsi);
1017}
1018
1019static void exynos_dsi_read_from_fifo(struct exynos_dsi *dsi,
1020 struct exynos_dsi_transfer *xfer)
1021{
1022 u8 *payload = xfer->rx_payload + xfer->rx_done;
1023 bool first = !xfer->rx_done;
1024 struct device *dev = dsi->dev;
1025 u16 length;
1026 u32 reg;
1027
1028 if (first) {
1029 reg = exynos_dsi_read(dsi, DSIM_RXFIFO_REG);
1030
1031 switch (reg & 0x3f) {
1032 case MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_2BYTE:
1033 case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_2BYTE:
1034 if (xfer->rx_len >= 2) {
1035 payload[1] = reg >> 16;
1036 ++xfer->rx_done;
1037 }
1038 /* Fall through */
1039 case MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_1BYTE:
1040 case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_1BYTE:
1041 payload[0] = reg >> 8;
1042 ++xfer->rx_done;
1043 xfer->rx_len = xfer->rx_done;
1044 xfer->result = 0;
1045 goto clear_fifo;
1046 case MIPI_DSI_RX_ACKNOWLEDGE_AND_ERROR_REPORT:
1047 dev_err(dev, "DSI Error Report: 0x%04x\n",
1048 (reg >> 8) & 0xffff);
1049 xfer->result = 0;
1050 goto clear_fifo;
1051 }
1052
1053 length = (reg >> 8) & 0xffff;
1054 if (length > xfer->rx_len) {
1055 dev_err(dev,
1056 "response too long (%u > %u bytes), stripping\n",
1057 xfer->rx_len, length);
1058 length = xfer->rx_len;
1059 } else if (length < xfer->rx_len)
1060 xfer->rx_len = length;
1061 }
1062
1063 length = xfer->rx_len - xfer->rx_done;
1064 xfer->rx_done += length;
1065
1066 /* Receive payload */
1067 while (length >= 4) {
1068 reg = exynos_dsi_read(dsi, DSIM_RXFIFO_REG);
1069 payload[0] = (reg >> 0) & 0xff;
1070 payload[1] = (reg >> 8) & 0xff;
1071 payload[2] = (reg >> 16) & 0xff;
1072 payload[3] = (reg >> 24) & 0xff;
1073 payload += 4;
1074 length -= 4;
1075 }
1076
1077 if (length) {
1078 reg = exynos_dsi_read(dsi, DSIM_RXFIFO_REG);
1079 switch (length) {
1080 case 3:
1081 payload[2] = (reg >> 16) & 0xff;
1082 /* Fall through */
1083 case 2:
1084 payload[1] = (reg >> 8) & 0xff;
1085 /* Fall through */
1086 case 1:
1087 payload[0] = reg & 0xff;
1088 }
1089 }
1090
1091 if (xfer->rx_done == xfer->rx_len)
1092 xfer->result = 0;
1093
1094clear_fifo:
1095 length = DSI_RX_FIFO_SIZE / 4;
1096 do {
1097 reg = exynos_dsi_read(dsi, DSIM_RXFIFO_REG);
1098 if (reg == DSI_RX_FIFO_EMPTY)
1099 break;
1100 } while (--length);
1101}
1102
1103static void exynos_dsi_transfer_start(struct exynos_dsi *dsi)
1104{
1105 unsigned long flags;
1106 struct exynos_dsi_transfer *xfer;
1107 bool start = false;
1108
1109again:
1110 spin_lock_irqsave(&dsi->transfer_lock, flags);
1111
1112 if (list_empty(&dsi->transfer_list)) {
1113 spin_unlock_irqrestore(&dsi->transfer_lock, flags);
1114 return;
1115 }
1116
1117 xfer = list_first_entry(&dsi->transfer_list,
1118 struct exynos_dsi_transfer, list);
1119
1120 spin_unlock_irqrestore(&dsi->transfer_lock, flags);
1121
1122 if (xfer->packet.payload_length &&
1123 xfer->tx_done == xfer->packet.payload_length)
1124 /* waiting for RX */
1125 return;
1126
1127 exynos_dsi_send_to_fifo(dsi, xfer);
1128
1129 if (xfer->packet.payload_length || xfer->rx_len)
1130 return;
1131
1132 xfer->result = 0;
1133 complete(&xfer->completed);
1134
1135 spin_lock_irqsave(&dsi->transfer_lock, flags);
1136
1137 list_del_init(&xfer->list);
1138 start = !list_empty(&dsi->transfer_list);
1139
1140 spin_unlock_irqrestore(&dsi->transfer_lock, flags);
1141
1142 if (start)
1143 goto again;
1144}
1145
1146static bool exynos_dsi_transfer_finish(struct exynos_dsi *dsi)
1147{
1148 struct exynos_dsi_transfer *xfer;
1149 unsigned long flags;
1150 bool start = true;
1151
1152 spin_lock_irqsave(&dsi->transfer_lock, flags);
1153
1154 if (list_empty(&dsi->transfer_list)) {
1155 spin_unlock_irqrestore(&dsi->transfer_lock, flags);
1156 return false;
1157 }
1158
1159 xfer = list_first_entry(&dsi->transfer_list,
1160 struct exynos_dsi_transfer, list);
1161
1162 spin_unlock_irqrestore(&dsi->transfer_lock, flags);
1163
1164 dev_dbg(dsi->dev,
1165 "> xfer %pK, tx_len %zu, tx_done %u, rx_len %u, rx_done %u\n",
1166 xfer, xfer->packet.payload_length, xfer->tx_done, xfer->rx_len,
1167 xfer->rx_done);
1168
1169 if (xfer->tx_done != xfer->packet.payload_length)
1170 return true;
1171
1172 if (xfer->rx_done != xfer->rx_len)
1173 exynos_dsi_read_from_fifo(dsi, xfer);
1174
1175 if (xfer->rx_done != xfer->rx_len)
1176 return true;
1177
1178 spin_lock_irqsave(&dsi->transfer_lock, flags);
1179
1180 list_del_init(&xfer->list);
1181 start = !list_empty(&dsi->transfer_list);
1182
1183 spin_unlock_irqrestore(&dsi->transfer_lock, flags);
1184
1185 if (!xfer->rx_len)
1186 xfer->result = 0;
1187 complete(&xfer->completed);
1188
1189 return start;
1190}
1191
1192static void exynos_dsi_remove_transfer(struct exynos_dsi *dsi,
1193 struct exynos_dsi_transfer *xfer)
1194{
1195 unsigned long flags;
1196 bool start;
1197
1198 spin_lock_irqsave(&dsi->transfer_lock, flags);
1199
1200 if (!list_empty(&dsi->transfer_list) &&
1201 xfer == list_first_entry(&dsi->transfer_list,
1202 struct exynos_dsi_transfer, list)) {
1203 list_del_init(&xfer->list);
1204 start = !list_empty(&dsi->transfer_list);
1205 spin_unlock_irqrestore(&dsi->transfer_lock, flags);
1206 if (start)
1207 exynos_dsi_transfer_start(dsi);
1208 return;
1209 }
1210
1211 list_del_init(&xfer->list);
1212
1213 spin_unlock_irqrestore(&dsi->transfer_lock, flags);
1214}
1215
1216static int exynos_dsi_transfer(struct exynos_dsi *dsi,
1217 struct exynos_dsi_transfer *xfer)
1218{
1219 unsigned long flags;
1220 bool stopped;
1221
1222 xfer->tx_done = 0;
1223 xfer->rx_done = 0;
1224 xfer->result = -ETIMEDOUT;
1225 init_completion(&xfer->completed);
1226
1227 spin_lock_irqsave(&dsi->transfer_lock, flags);
1228
1229 stopped = list_empty(&dsi->transfer_list);
1230 list_add_tail(&xfer->list, &dsi->transfer_list);
1231
1232 spin_unlock_irqrestore(&dsi->transfer_lock, flags);
1233
1234 if (stopped)
1235 exynos_dsi_transfer_start(dsi);
1236
1237 wait_for_completion_timeout(&xfer->completed,
1238 msecs_to_jiffies(DSI_XFER_TIMEOUT_MS));
1239 if (xfer->result == -ETIMEDOUT) {
1240 struct mipi_dsi_packet *pkt = &xfer->packet;
1241 exynos_dsi_remove_transfer(dsi, xfer);
1242 dev_err(dsi->dev, "xfer timed out: %*ph %*ph\n", 4, pkt->header,
1243 (int)pkt->payload_length, pkt->payload);
1244 return -ETIMEDOUT;
1245 }
1246
1247 /* Also covers hardware timeout condition */
1248 return xfer->result;
1249}
1250
1251static irqreturn_t exynos_dsi_irq(int irq, void *dev_id)
1252{
1253 struct exynos_dsi *dsi = dev_id;
1254 u32 status;
1255
1256 status = exynos_dsi_read(dsi, DSIM_INTSRC_REG);
1257 if (!status) {
1258 static unsigned long int j;
1259 if (printk_timed_ratelimit(&j, 500))
1260 dev_warn(dsi->dev, "spurious interrupt\n");
1261 return IRQ_HANDLED;
1262 }
1263 exynos_dsi_write(dsi, DSIM_INTSRC_REG, status);
1264
1265 if (status & DSIM_INT_SW_RST_RELEASE) {
1266 u32 mask = ~(DSIM_INT_RX_DONE | DSIM_INT_SFR_FIFO_EMPTY |
1267 DSIM_INT_SFR_HDR_FIFO_EMPTY | DSIM_INT_RX_ECC_ERR |
1268 DSIM_INT_SW_RST_RELEASE);
1269 exynos_dsi_write(dsi, DSIM_INTMSK_REG, mask);
1270 complete(&dsi->completed);
1271 return IRQ_HANDLED;
1272 }
1273
1274 if (!(status & (DSIM_INT_RX_DONE | DSIM_INT_SFR_FIFO_EMPTY |
1275 DSIM_INT_PLL_STABLE)))
1276 return IRQ_HANDLED;
1277
1278 if (exynos_dsi_transfer_finish(dsi))
1279 exynos_dsi_transfer_start(dsi);
1280
1281 return IRQ_HANDLED;
1282}
1283
1284static irqreturn_t exynos_dsi_te_irq_handler(int irq, void *dev_id)
1285{
1286 struct exynos_dsi *dsi = (struct exynos_dsi *)dev_id;
1287 struct drm_encoder *encoder = &dsi->encoder;
1288
1289 if (dsi->state & DSIM_STATE_VIDOUT_AVAILABLE)
1290 exynos_drm_crtc_te_handler(encoder->crtc);
1291
1292 return IRQ_HANDLED;
1293}
1294
1295static void exynos_dsi_enable_irq(struct exynos_dsi *dsi)
1296{
1297 enable_irq(dsi->irq);
1298
1299 if (gpio_is_valid(dsi->te_gpio))
1300 enable_irq(gpio_to_irq(dsi->te_gpio));
1301}
1302
1303static void exynos_dsi_disable_irq(struct exynos_dsi *dsi)
1304{
1305 if (gpio_is_valid(dsi->te_gpio))
1306 disable_irq(gpio_to_irq(dsi->te_gpio));
1307
1308 disable_irq(dsi->irq);
1309}
1310
1311static int exynos_dsi_init(struct exynos_dsi *dsi)
1312{
1313 const struct exynos_dsi_driver_data *driver_data = dsi->driver_data;
1314
1315 exynos_dsi_reset(dsi);
1316 exynos_dsi_enable_irq(dsi);
1317
1318 if (driver_data->reg_values[RESET_TYPE] == DSIM_FUNCRST)
1319 exynos_dsi_enable_lane(dsi, BIT(dsi->lanes) - 1);
1320
1321 exynos_dsi_enable_clock(dsi);
1322 if (driver_data->wait_for_reset)
1323 exynos_dsi_wait_for_reset(dsi);
1324 exynos_dsi_set_phy_ctrl(dsi);
1325 exynos_dsi_init_link(dsi);
1326
1327 return 0;
1328}
1329
1330static int exynos_dsi_register_te_irq(struct exynos_dsi *dsi,
1331 struct device *panel)
1332{
1333 int ret;
1334 int te_gpio_irq;
1335
1336 dsi->te_gpio = of_get_named_gpio(panel->of_node, "te-gpios", 0);
1337 if (dsi->te_gpio == -ENOENT)
1338 return 0;
1339
1340 if (!gpio_is_valid(dsi->te_gpio)) {
1341 ret = dsi->te_gpio;
1342 dev_err(dsi->dev, "cannot get te-gpios, %d\n", ret);
1343 goto out;
1344 }
1345
1346 ret = gpio_request(dsi->te_gpio, "te_gpio");
1347 if (ret) {
1348 dev_err(dsi->dev, "gpio request failed with %d\n", ret);
1349 goto out;
1350 }
1351
1352 te_gpio_irq = gpio_to_irq(dsi->te_gpio);
1353 irq_set_status_flags(te_gpio_irq, IRQ_NOAUTOEN);
1354
1355 ret = request_threaded_irq(te_gpio_irq, exynos_dsi_te_irq_handler, NULL,
1356 IRQF_TRIGGER_RISING, "TE", dsi);
1357 if (ret) {
1358 dev_err(dsi->dev, "request interrupt failed with %d\n", ret);
1359 gpio_free(dsi->te_gpio);
1360 goto out;
1361 }
1362
1363out:
1364 return ret;
1365}
1366
1367static void exynos_dsi_unregister_te_irq(struct exynos_dsi *dsi)
1368{
1369 if (gpio_is_valid(dsi->te_gpio)) {
1370 free_irq(gpio_to_irq(dsi->te_gpio), dsi);
1371 gpio_free(dsi->te_gpio);
1372 dsi->te_gpio = -ENOENT;
1373 }
1374}
1375
1376static void exynos_dsi_enable(struct drm_encoder *encoder)
1377{
1378 struct exynos_dsi *dsi = encoder_to_dsi(encoder);
1379 int ret;
1380
1381 if (dsi->state & DSIM_STATE_ENABLED)
1382 return;
1383
1384 pm_runtime_get_sync(dsi->dev);
1385 dsi->state |= DSIM_STATE_ENABLED;
1386
1387 if (dsi->panel) {
1388 ret = drm_panel_prepare(dsi->panel);
1389 if (ret < 0)
1390 goto err_put_sync;
1391 } else {
1392 drm_bridge_pre_enable(dsi->out_bridge);
1393 }
1394
1395 exynos_dsi_set_display_mode(dsi);
1396 exynos_dsi_set_display_enable(dsi, true);
1397
1398 if (dsi->panel) {
1399 ret = drm_panel_enable(dsi->panel);
1400 if (ret < 0)
1401 goto err_display_disable;
1402 } else {
1403 drm_bridge_enable(dsi->out_bridge);
1404 }
1405
1406 dsi->state |= DSIM_STATE_VIDOUT_AVAILABLE;
1407 return;
1408
1409err_display_disable:
1410 exynos_dsi_set_display_enable(dsi, false);
1411 drm_panel_unprepare(dsi->panel);
1412
1413err_put_sync:
1414 dsi->state &= ~DSIM_STATE_ENABLED;
1415 pm_runtime_put(dsi->dev);
1416}
1417
1418static void exynos_dsi_disable(struct drm_encoder *encoder)
1419{
1420 struct exynos_dsi *dsi = encoder_to_dsi(encoder);
1421
1422 if (!(dsi->state & DSIM_STATE_ENABLED))
1423 return;
1424
1425 dsi->state &= ~DSIM_STATE_VIDOUT_AVAILABLE;
1426
1427 drm_panel_disable(dsi->panel);
1428 drm_bridge_disable(dsi->out_bridge);
1429 exynos_dsi_set_display_enable(dsi, false);
1430 drm_panel_unprepare(dsi->panel);
1431 drm_bridge_post_disable(dsi->out_bridge);
1432 dsi->state &= ~DSIM_STATE_ENABLED;
1433 pm_runtime_put_sync(dsi->dev);
1434}
1435
1436static enum drm_connector_status
1437exynos_dsi_detect(struct drm_connector *connector, bool force)
1438{
1439 return connector->status;
1440}
1441
1442static void exynos_dsi_connector_destroy(struct drm_connector *connector)
1443{
1444 drm_connector_unregister(connector);
1445 drm_connector_cleanup(connector);
1446 connector->dev = NULL;
1447}
1448
1449static const struct drm_connector_funcs exynos_dsi_connector_funcs = {
1450 .detect = exynos_dsi_detect,
1451 .fill_modes = drm_helper_probe_single_connector_modes,
1452 .destroy = exynos_dsi_connector_destroy,
1453 .reset = drm_atomic_helper_connector_reset,
1454 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
1455 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
1456};
1457
1458static int exynos_dsi_get_modes(struct drm_connector *connector)
1459{
1460 struct exynos_dsi *dsi = connector_to_dsi(connector);
1461
1462 if (dsi->panel)
1463 return dsi->panel->funcs->get_modes(dsi->panel);
1464
1465 return 0;
1466}
1467
1468static const struct drm_connector_helper_funcs exynos_dsi_connector_helper_funcs = {
1469 .get_modes = exynos_dsi_get_modes,
1470};
1471
1472static int exynos_dsi_create_connector(struct drm_encoder *encoder)
1473{
1474 struct exynos_dsi *dsi = encoder_to_dsi(encoder);
1475 struct drm_connector *connector = &dsi->connector;
1476 struct drm_device *drm = encoder->dev;
1477 int ret;
1478
1479 connector->polled = DRM_CONNECTOR_POLL_HPD;
1480
1481 ret = drm_connector_init(drm, connector, &exynos_dsi_connector_funcs,
1482 DRM_MODE_CONNECTOR_DSI);
1483 if (ret) {
1484 DRM_DEV_ERROR(dsi->dev,
1485 "Failed to initialize connector with drm\n");
1486 return ret;
1487 }
1488
1489 connector->status = connector_status_disconnected;
1490 drm_connector_helper_add(connector, &exynos_dsi_connector_helper_funcs);
1491 drm_connector_attach_encoder(connector, encoder);
1492 if (!drm->registered)
1493 return 0;
1494
1495 connector->funcs->reset(connector);
1496 drm_fb_helper_add_one_connector(drm->fb_helper, connector);
1497 drm_connector_register(connector);
1498 return 0;
1499}
1500
1501static const struct drm_encoder_helper_funcs exynos_dsi_encoder_helper_funcs = {
1502 .enable = exynos_dsi_enable,
1503 .disable = exynos_dsi_disable,
1504};
1505
1506static const struct drm_encoder_funcs exynos_dsi_encoder_funcs = {
1507 .destroy = drm_encoder_cleanup,
1508};
1509
1510MODULE_DEVICE_TABLE(of, exynos_dsi_of_match);
1511
1512static int exynos_dsi_host_attach(struct mipi_dsi_host *host,
1513 struct mipi_dsi_device *device)
1514{
1515 struct exynos_dsi *dsi = host_to_dsi(host);
1516 struct drm_encoder *encoder = &dsi->encoder;
1517 struct drm_device *drm = encoder->dev;
1518 struct drm_bridge *out_bridge;
1519
1520 out_bridge = of_drm_find_bridge(device->dev.of_node);
1521 if (out_bridge) {
1522 drm_bridge_attach(encoder, out_bridge, NULL);
1523 dsi->out_bridge = out_bridge;
1524 encoder->bridge = NULL;
1525 } else {
1526 int ret = exynos_dsi_create_connector(encoder);
1527
1528 if (ret) {
1529 DRM_DEV_ERROR(dsi->dev,
1530 "failed to create connector ret = %d\n",
1531 ret);
1532 drm_encoder_cleanup(encoder);
1533 return ret;
1534 }
1535
1536 dsi->panel = of_drm_find_panel(device->dev.of_node);
1537 if (IS_ERR(dsi->panel)) {
1538 dsi->panel = NULL;
1539 } else {
1540 drm_panel_attach(dsi->panel, &dsi->connector);
1541 dsi->connector.status = connector_status_connected;
1542 }
1543 }
1544
1545 /*
1546 * This is a temporary solution and should be made by more generic way.
1547 *
1548 * If attached panel device is for command mode one, dsi should register
1549 * TE interrupt handler.
1550 */
1551 if (!(device->mode_flags & MIPI_DSI_MODE_VIDEO)) {
1552 int ret = exynos_dsi_register_te_irq(dsi, &device->dev);
1553 if (ret)
1554 return ret;
1555 }
1556
1557 mutex_lock(&drm->mode_config.mutex);
1558
1559 dsi->lanes = device->lanes;
1560 dsi->format = device->format;
1561 dsi->mode_flags = device->mode_flags;
1562 exynos_drm_crtc_get_by_type(drm, EXYNOS_DISPLAY_TYPE_LCD)->i80_mode =
1563 !(dsi->mode_flags & MIPI_DSI_MODE_VIDEO);
1564
1565 mutex_unlock(&drm->mode_config.mutex);
1566
1567 if (drm->mode_config.poll_enabled)
1568 drm_kms_helper_hotplug_event(drm);
1569
1570 return 0;
1571}
1572
1573static int exynos_dsi_host_detach(struct mipi_dsi_host *host,
1574 struct mipi_dsi_device *device)
1575{
1576 struct exynos_dsi *dsi = host_to_dsi(host);
1577 struct drm_device *drm = dsi->encoder.dev;
1578
1579 if (dsi->panel) {
1580 mutex_lock(&drm->mode_config.mutex);
1581 exynos_dsi_disable(&dsi->encoder);
1582 drm_panel_detach(dsi->panel);
1583 dsi->panel = NULL;
1584 dsi->connector.status = connector_status_disconnected;
1585 mutex_unlock(&drm->mode_config.mutex);
1586 } else {
1587 if (dsi->out_bridge->funcs->detach)
1588 dsi->out_bridge->funcs->detach(dsi->out_bridge);
1589 dsi->out_bridge = NULL;
1590 }
1591
1592 if (drm->mode_config.poll_enabled)
1593 drm_kms_helper_hotplug_event(drm);
1594
1595 exynos_dsi_unregister_te_irq(dsi);
1596
1597 return 0;
1598}
1599
1600static ssize_t exynos_dsi_host_transfer(struct mipi_dsi_host *host,
1601 const struct mipi_dsi_msg *msg)
1602{
1603 struct exynos_dsi *dsi = host_to_dsi(host);
1604 struct exynos_dsi_transfer xfer;
1605 int ret;
1606
1607 if (!(dsi->state & DSIM_STATE_ENABLED))
1608 return -EINVAL;
1609
1610 if (!(dsi->state & DSIM_STATE_INITIALIZED)) {
1611 ret = exynos_dsi_init(dsi);
1612 if (ret)
1613 return ret;
1614 dsi->state |= DSIM_STATE_INITIALIZED;
1615 }
1616
1617 ret = mipi_dsi_create_packet(&xfer.packet, msg);
1618 if (ret < 0)
1619 return ret;
1620
1621 xfer.rx_len = msg->rx_len;
1622 xfer.rx_payload = msg->rx_buf;
1623 xfer.flags = msg->flags;
1624
1625 ret = exynos_dsi_transfer(dsi, &xfer);
1626 return (ret < 0) ? ret : xfer.rx_done;
1627}
1628
1629static const struct mipi_dsi_host_ops exynos_dsi_ops = {
1630 .attach = exynos_dsi_host_attach,
1631 .detach = exynos_dsi_host_detach,
1632 .transfer = exynos_dsi_host_transfer,
1633};
1634
1635static int exynos_dsi_of_read_u32(const struct device_node *np,
1636 const char *propname, u32 *out_value)
1637{
1638 int ret = of_property_read_u32(np, propname, out_value);
1639
1640 if (ret < 0)
1641 pr_err("%pOF: failed to get '%s' property\n", np, propname);
1642
1643 return ret;
1644}
1645
1646enum {
1647 DSI_PORT_IN,
1648 DSI_PORT_OUT
1649};
1650
1651static int exynos_dsi_parse_dt(struct exynos_dsi *dsi)
1652{
1653 struct device *dev = dsi->dev;
1654 struct device_node *node = dev->of_node;
1655 int ret;
1656
1657 ret = exynos_dsi_of_read_u32(node, "samsung,pll-clock-frequency",
1658 &dsi->pll_clk_rate);
1659 if (ret < 0)
1660 return ret;
1661
1662 ret = exynos_dsi_of_read_u32(node, "samsung,burst-clock-frequency",
1663 &dsi->burst_clk_rate);
1664 if (ret < 0)
1665 return ret;
1666
1667 ret = exynos_dsi_of_read_u32(node, "samsung,esc-clock-frequency",
1668 &dsi->esc_clk_rate);
1669 if (ret < 0)
1670 return ret;
1671
1672 dsi->in_bridge_node = of_graph_get_remote_node(node, DSI_PORT_IN, 0);
1673
1674 return 0;
1675}
1676
1677static int exynos_dsi_bind(struct device *dev, struct device *master,
1678 void *data)
1679{
1680 struct drm_encoder *encoder = dev_get_drvdata(dev);
1681 struct exynos_dsi *dsi = encoder_to_dsi(encoder);
1682 struct drm_device *drm_dev = data;
1683 struct drm_bridge *in_bridge;
1684 int ret;
1685
1686 drm_encoder_init(drm_dev, encoder, &exynos_dsi_encoder_funcs,
1687 DRM_MODE_ENCODER_TMDS, NULL);
1688
1689 drm_encoder_helper_add(encoder, &exynos_dsi_encoder_helper_funcs);
1690
1691 ret = exynos_drm_set_possible_crtcs(encoder, EXYNOS_DISPLAY_TYPE_LCD);
1692 if (ret < 0)
1693 return ret;
1694
1695 if (dsi->in_bridge_node) {
1696 in_bridge = of_drm_find_bridge(dsi->in_bridge_node);
1697 if (in_bridge)
1698 drm_bridge_attach(encoder, in_bridge, NULL);
1699 }
1700
1701 return mipi_dsi_host_register(&dsi->dsi_host);
1702}
1703
1704static void exynos_dsi_unbind(struct device *dev, struct device *master,
1705 void *data)
1706{
1707 struct drm_encoder *encoder = dev_get_drvdata(dev);
1708 struct exynos_dsi *dsi = encoder_to_dsi(encoder);
1709
1710 exynos_dsi_disable(encoder);
1711
1712 mipi_dsi_host_unregister(&dsi->dsi_host);
1713}
1714
1715static const struct component_ops exynos_dsi_component_ops = {
1716 .bind = exynos_dsi_bind,
1717 .unbind = exynos_dsi_unbind,
1718};
1719
1720static int exynos_dsi_probe(struct platform_device *pdev)
1721{
1722 struct device *dev = &pdev->dev;
1723 struct resource *res;
1724 struct exynos_dsi *dsi;
1725 int ret, i;
1726
1727 dsi = devm_kzalloc(dev, sizeof(*dsi), GFP_KERNEL);
1728 if (!dsi)
1729 return -ENOMEM;
1730
1731 /* To be checked as invalid one */
1732 dsi->te_gpio = -ENOENT;
1733
1734 init_completion(&dsi->completed);
1735 spin_lock_init(&dsi->transfer_lock);
1736 INIT_LIST_HEAD(&dsi->transfer_list);
1737
1738 dsi->dsi_host.ops = &exynos_dsi_ops;
1739 dsi->dsi_host.dev = dev;
1740
1741 dsi->dev = dev;
1742 dsi->driver_data = of_device_get_match_data(dev);
1743
1744 ret = exynos_dsi_parse_dt(dsi);
1745 if (ret)
1746 return ret;
1747
1748 dsi->supplies[0].supply = "vddcore";
1749 dsi->supplies[1].supply = "vddio";
1750 ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(dsi->supplies),
1751 dsi->supplies);
1752 if (ret) {
1753 dev_info(dev, "failed to get regulators: %d\n", ret);
1754 return -EPROBE_DEFER;
1755 }
1756
1757 dsi->clks = devm_kcalloc(dev,
1758 dsi->driver_data->num_clks, sizeof(*dsi->clks),
1759 GFP_KERNEL);
1760 if (!dsi->clks)
1761 return -ENOMEM;
1762
1763 for (i = 0; i < dsi->driver_data->num_clks; i++) {
1764 dsi->clks[i] = devm_clk_get(dev, clk_names[i]);
1765 if (IS_ERR(dsi->clks[i])) {
1766 if (strcmp(clk_names[i], "sclk_mipi") == 0) {
1767 strcpy(clk_names[i], OLD_SCLK_MIPI_CLK_NAME);
1768 i--;
1769 continue;
1770 }
1771
1772 dev_info(dev, "failed to get the clock: %s\n",
1773 clk_names[i]);
1774 return PTR_ERR(dsi->clks[i]);
1775 }
1776 }
1777
1778 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1779 dsi->reg_base = devm_ioremap_resource(dev, res);
1780 if (IS_ERR(dsi->reg_base)) {
1781 dev_err(dev, "failed to remap io region\n");
1782 return PTR_ERR(dsi->reg_base);
1783 }
1784
1785 dsi->phy = devm_phy_get(dev, "dsim");
1786 if (IS_ERR(dsi->phy)) {
1787 dev_info(dev, "failed to get dsim phy\n");
1788 return PTR_ERR(dsi->phy);
1789 }
1790
1791 dsi->irq = platform_get_irq(pdev, 0);
1792 if (dsi->irq < 0) {
1793 dev_err(dev, "failed to request dsi irq resource\n");
1794 return dsi->irq;
1795 }
1796
1797 irq_set_status_flags(dsi->irq, IRQ_NOAUTOEN);
1798 ret = devm_request_threaded_irq(dev, dsi->irq, NULL,
1799 exynos_dsi_irq, IRQF_ONESHOT,
1800 dev_name(dev), dsi);
1801 if (ret) {
1802 dev_err(dev, "failed to request dsi irq\n");
1803 return ret;
1804 }
1805
1806 platform_set_drvdata(pdev, &dsi->encoder);
1807
1808 pm_runtime_enable(dev);
1809
1810 return component_add(dev, &exynos_dsi_component_ops);
1811}
1812
1813static int exynos_dsi_remove(struct platform_device *pdev)
1814{
1815 struct exynos_dsi *dsi = platform_get_drvdata(pdev);
1816
1817 of_node_put(dsi->in_bridge_node);
1818
1819 pm_runtime_disable(&pdev->dev);
1820
1821 component_del(&pdev->dev, &exynos_dsi_component_ops);
1822
1823 return 0;
1824}
1825
1826static int __maybe_unused exynos_dsi_suspend(struct device *dev)
1827{
1828 struct drm_encoder *encoder = dev_get_drvdata(dev);
1829 struct exynos_dsi *dsi = encoder_to_dsi(encoder);
1830 const struct exynos_dsi_driver_data *driver_data = dsi->driver_data;
1831 int ret, i;
1832
1833 usleep_range(10000, 20000);
1834
1835 if (dsi->state & DSIM_STATE_INITIALIZED) {
1836 dsi->state &= ~DSIM_STATE_INITIALIZED;
1837
1838 exynos_dsi_disable_clock(dsi);
1839
1840 exynos_dsi_disable_irq(dsi);
1841 }
1842
1843 dsi->state &= ~DSIM_STATE_CMD_LPM;
1844
1845 phy_power_off(dsi->phy);
1846
1847 for (i = driver_data->num_clks - 1; i > -1; i--)
1848 clk_disable_unprepare(dsi->clks[i]);
1849
1850 ret = regulator_bulk_disable(ARRAY_SIZE(dsi->supplies), dsi->supplies);
1851 if (ret < 0)
1852 dev_err(dsi->dev, "cannot disable regulators %d\n", ret);
1853
1854 return 0;
1855}
1856
1857static int __maybe_unused exynos_dsi_resume(struct device *dev)
1858{
1859 struct drm_encoder *encoder = dev_get_drvdata(dev);
1860 struct exynos_dsi *dsi = encoder_to_dsi(encoder);
1861 const struct exynos_dsi_driver_data *driver_data = dsi->driver_data;
1862 int ret, i;
1863
1864 ret = regulator_bulk_enable(ARRAY_SIZE(dsi->supplies), dsi->supplies);
1865 if (ret < 0) {
1866 dev_err(dsi->dev, "cannot enable regulators %d\n", ret);
1867 return ret;
1868 }
1869
1870 for (i = 0; i < driver_data->num_clks; i++) {
1871 ret = clk_prepare_enable(dsi->clks[i]);
1872 if (ret < 0)
1873 goto err_clk;
1874 }
1875
1876 ret = phy_power_on(dsi->phy);
1877 if (ret < 0) {
1878 dev_err(dsi->dev, "cannot enable phy %d\n", ret);
1879 goto err_clk;
1880 }
1881
1882 return 0;
1883
1884err_clk:
1885 while (--i > -1)
1886 clk_disable_unprepare(dsi->clks[i]);
1887 regulator_bulk_disable(ARRAY_SIZE(dsi->supplies), dsi->supplies);
1888
1889 return ret;
1890}
1891
1892static const struct dev_pm_ops exynos_dsi_pm_ops = {
1893 SET_RUNTIME_PM_OPS(exynos_dsi_suspend, exynos_dsi_resume, NULL)
1894 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
1895 pm_runtime_force_resume)
1896};
1897
1898struct platform_driver dsi_driver = {
1899 .probe = exynos_dsi_probe,
1900 .remove = exynos_dsi_remove,
1901 .driver = {
1902 .name = "exynos-dsi",
1903 .owner = THIS_MODULE,
1904 .pm = &exynos_dsi_pm_ops,
1905 .of_match_table = exynos_dsi_of_match,
1906 },
1907};
1908
1909MODULE_AUTHOR("Tomasz Figa <t.figa@samsung.com>");
1910MODULE_AUTHOR("Andrzej Hajda <a.hajda@samsung.com>");
1911MODULE_DESCRIPTION("Samsung SoC MIPI DSI Master");
1912MODULE_LICENSE("GPL v2");