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1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright (c) 2016, Fuzhou Rockchip Electronics Co., Ltd
4 * Copyright (C) STMicroelectronics SA 2017
5 *
6 * Modified by Philippe Cornu <philippe.cornu@st.com>
7 * This generic Synopsys DesignWare MIPI DSI host driver is based on the
8 * Rockchip version from rockchip/dw-mipi-dsi.c with phy & bridge APIs.
9 */
10
11#include <linux/clk.h>
12#include <linux/component.h>
13#include <linux/debugfs.h>
14#include <linux/iopoll.h>
15#include <linux/module.h>
16#include <linux/of_device.h>
17#include <linux/pm_runtime.h>
18#include <linux/reset.h>
19
20#include <video/mipi_display.h>
21
22#include <drm/bridge/dw_mipi_dsi.h>
23#include <drm/drm_atomic_helper.h>
24#include <drm/drm_bridge.h>
25#include <drm/drm_crtc.h>
26#include <drm/drm_mipi_dsi.h>
27#include <drm/drm_modes.h>
28#include <drm/drm_of.h>
29#include <drm/drm_print.h>
30#include <drm/drm_probe_helper.h>
31
32#define HWVER_131 0x31333100 /* IP version 1.31 */
33
34#define DSI_VERSION 0x00
35#define VERSION GENMASK(31, 8)
36
37#define DSI_PWR_UP 0x04
38#define RESET 0
39#define POWERUP BIT(0)
40
41#define DSI_CLKMGR_CFG 0x08
42#define TO_CLK_DIVISION(div) (((div) & 0xff) << 8)
43#define TX_ESC_CLK_DIVISION(div) ((div) & 0xff)
44
45#define DSI_DPI_VCID 0x0c
46#define DPI_VCID(vcid) ((vcid) & 0x3)
47
48#define DSI_DPI_COLOR_CODING 0x10
49#define LOOSELY18_EN BIT(8)
50#define DPI_COLOR_CODING_16BIT_1 0x0
51#define DPI_COLOR_CODING_16BIT_2 0x1
52#define DPI_COLOR_CODING_16BIT_3 0x2
53#define DPI_COLOR_CODING_18BIT_1 0x3
54#define DPI_COLOR_CODING_18BIT_2 0x4
55#define DPI_COLOR_CODING_24BIT 0x5
56
57#define DSI_DPI_CFG_POL 0x14
58#define COLORM_ACTIVE_LOW BIT(4)
59#define SHUTD_ACTIVE_LOW BIT(3)
60#define HSYNC_ACTIVE_LOW BIT(2)
61#define VSYNC_ACTIVE_LOW BIT(1)
62#define DATAEN_ACTIVE_LOW BIT(0)
63
64#define DSI_DPI_LP_CMD_TIM 0x18
65#define OUTVACT_LPCMD_TIME(p) (((p) & 0xff) << 16)
66#define INVACT_LPCMD_TIME(p) ((p) & 0xff)
67
68#define DSI_DBI_VCID 0x1c
69#define DSI_DBI_CFG 0x20
70#define DSI_DBI_PARTITIONING_EN 0x24
71#define DSI_DBI_CMDSIZE 0x28
72
73#define DSI_PCKHDL_CFG 0x2c
74#define CRC_RX_EN BIT(4)
75#define ECC_RX_EN BIT(3)
76#define BTA_EN BIT(2)
77#define EOTP_RX_EN BIT(1)
78#define EOTP_TX_EN BIT(0)
79
80#define DSI_GEN_VCID 0x30
81
82#define DSI_MODE_CFG 0x34
83#define ENABLE_VIDEO_MODE 0
84#define ENABLE_CMD_MODE BIT(0)
85
86#define DSI_VID_MODE_CFG 0x38
87#define ENABLE_LOW_POWER (0x3f << 8)
88#define ENABLE_LOW_POWER_MASK (0x3f << 8)
89#define VID_MODE_TYPE_NON_BURST_SYNC_PULSES 0x0
90#define VID_MODE_TYPE_NON_BURST_SYNC_EVENTS 0x1
91#define VID_MODE_TYPE_BURST 0x2
92#define VID_MODE_TYPE_MASK 0x3
93#define VID_MODE_VPG_ENABLE BIT(16)
94#define VID_MODE_VPG_HORIZONTAL BIT(24)
95
96#define DSI_VID_PKT_SIZE 0x3c
97#define VID_PKT_SIZE(p) ((p) & 0x3fff)
98
99#define DSI_VID_NUM_CHUNKS 0x40
100#define VID_NUM_CHUNKS(c) ((c) & 0x1fff)
101
102#define DSI_VID_NULL_SIZE 0x44
103#define VID_NULL_SIZE(b) ((b) & 0x1fff)
104
105#define DSI_VID_HSA_TIME 0x48
106#define DSI_VID_HBP_TIME 0x4c
107#define DSI_VID_HLINE_TIME 0x50
108#define DSI_VID_VSA_LINES 0x54
109#define DSI_VID_VBP_LINES 0x58
110#define DSI_VID_VFP_LINES 0x5c
111#define DSI_VID_VACTIVE_LINES 0x60
112#define DSI_EDPI_CMD_SIZE 0x64
113
114#define DSI_CMD_MODE_CFG 0x68
115#define MAX_RD_PKT_SIZE_LP BIT(24)
116#define DCS_LW_TX_LP BIT(19)
117#define DCS_SR_0P_TX_LP BIT(18)
118#define DCS_SW_1P_TX_LP BIT(17)
119#define DCS_SW_0P_TX_LP BIT(16)
120#define GEN_LW_TX_LP BIT(14)
121#define GEN_SR_2P_TX_LP BIT(13)
122#define GEN_SR_1P_TX_LP BIT(12)
123#define GEN_SR_0P_TX_LP BIT(11)
124#define GEN_SW_2P_TX_LP BIT(10)
125#define GEN_SW_1P_TX_LP BIT(9)
126#define GEN_SW_0P_TX_LP BIT(8)
127#define ACK_RQST_EN BIT(1)
128#define TEAR_FX_EN BIT(0)
129
130#define CMD_MODE_ALL_LP (MAX_RD_PKT_SIZE_LP | \
131 DCS_LW_TX_LP | \
132 DCS_SR_0P_TX_LP | \
133 DCS_SW_1P_TX_LP | \
134 DCS_SW_0P_TX_LP | \
135 GEN_LW_TX_LP | \
136 GEN_SR_2P_TX_LP | \
137 GEN_SR_1P_TX_LP | \
138 GEN_SR_0P_TX_LP | \
139 GEN_SW_2P_TX_LP | \
140 GEN_SW_1P_TX_LP | \
141 GEN_SW_0P_TX_LP)
142
143#define DSI_GEN_HDR 0x6c
144#define DSI_GEN_PLD_DATA 0x70
145
146#define DSI_CMD_PKT_STATUS 0x74
147#define GEN_RD_CMD_BUSY BIT(6)
148#define GEN_PLD_R_FULL BIT(5)
149#define GEN_PLD_R_EMPTY BIT(4)
150#define GEN_PLD_W_FULL BIT(3)
151#define GEN_PLD_W_EMPTY BIT(2)
152#define GEN_CMD_FULL BIT(1)
153#define GEN_CMD_EMPTY BIT(0)
154
155#define DSI_TO_CNT_CFG 0x78
156#define HSTX_TO_CNT(p) (((p) & 0xffff) << 16)
157#define LPRX_TO_CNT(p) ((p) & 0xffff)
158
159#define DSI_HS_RD_TO_CNT 0x7c
160#define DSI_LP_RD_TO_CNT 0x80
161#define DSI_HS_WR_TO_CNT 0x84
162#define DSI_LP_WR_TO_CNT 0x88
163#define DSI_BTA_TO_CNT 0x8c
164
165#define DSI_LPCLK_CTRL 0x94
166#define AUTO_CLKLANE_CTRL BIT(1)
167#define PHY_TXREQUESTCLKHS BIT(0)
168
169#define DSI_PHY_TMR_LPCLK_CFG 0x98
170#define PHY_CLKHS2LP_TIME(lbcc) (((lbcc) & 0x3ff) << 16)
171#define PHY_CLKLP2HS_TIME(lbcc) ((lbcc) & 0x3ff)
172
173#define DSI_PHY_TMR_CFG 0x9c
174#define PHY_HS2LP_TIME(lbcc) (((lbcc) & 0xff) << 24)
175#define PHY_LP2HS_TIME(lbcc) (((lbcc) & 0xff) << 16)
176#define MAX_RD_TIME(lbcc) ((lbcc) & 0x7fff)
177#define PHY_HS2LP_TIME_V131(lbcc) (((lbcc) & 0x3ff) << 16)
178#define PHY_LP2HS_TIME_V131(lbcc) ((lbcc) & 0x3ff)
179
180#define DSI_PHY_RSTZ 0xa0
181#define PHY_DISFORCEPLL 0
182#define PHY_ENFORCEPLL BIT(3)
183#define PHY_DISABLECLK 0
184#define PHY_ENABLECLK BIT(2)
185#define PHY_RSTZ 0
186#define PHY_UNRSTZ BIT(1)
187#define PHY_SHUTDOWNZ 0
188#define PHY_UNSHUTDOWNZ BIT(0)
189
190#define DSI_PHY_IF_CFG 0xa4
191#define PHY_STOP_WAIT_TIME(cycle) (((cycle) & 0xff) << 8)
192#define N_LANES(n) (((n) - 1) & 0x3)
193
194#define DSI_PHY_ULPS_CTRL 0xa8
195#define DSI_PHY_TX_TRIGGERS 0xac
196
197#define DSI_PHY_STATUS 0xb0
198#define PHY_STOP_STATE_CLK_LANE BIT(2)
199#define PHY_LOCK BIT(0)
200
201#define DSI_PHY_TST_CTRL0 0xb4
202#define PHY_TESTCLK BIT(1)
203#define PHY_UNTESTCLK 0
204#define PHY_TESTCLR BIT(0)
205#define PHY_UNTESTCLR 0
206
207#define DSI_PHY_TST_CTRL1 0xb8
208#define PHY_TESTEN BIT(16)
209#define PHY_UNTESTEN 0
210#define PHY_TESTDOUT(n) (((n) & 0xff) << 8)
211#define PHY_TESTDIN(n) ((n) & 0xff)
212
213#define DSI_INT_ST0 0xbc
214#define DSI_INT_ST1 0xc0
215#define DSI_INT_MSK0 0xc4
216#define DSI_INT_MSK1 0xc8
217
218#define DSI_PHY_TMR_RD_CFG 0xf4
219#define MAX_RD_TIME_V131(lbcc) ((lbcc) & 0x7fff)
220
221#define PHY_STATUS_TIMEOUT_US 10000
222#define CMD_PKT_STATUS_TIMEOUT_US 20000
223
224struct dw_mipi_dsi {
225 struct drm_bridge bridge;
226 struct mipi_dsi_host dsi_host;
227 struct drm_bridge *panel_bridge;
228 struct device *dev;
229 void __iomem *base;
230
231 struct clk *pclk;
232
233 unsigned int lane_mbps; /* per lane */
234 u32 channel;
235 u32 lanes;
236 u32 format;
237 unsigned long mode_flags;
238
239#ifdef CONFIG_DEBUG_FS
240 struct dentry *debugfs;
241
242 bool vpg;
243 bool vpg_horizontal;
244#endif /* CONFIG_DEBUG_FS */
245
246 struct dw_mipi_dsi *master; /* dual-dsi master ptr */
247 struct dw_mipi_dsi *slave; /* dual-dsi slave ptr */
248
249 const struct dw_mipi_dsi_plat_data *plat_data;
250};
251
252/*
253 * Check if either a link to a master or slave is present
254 */
255static inline bool dw_mipi_is_dual_mode(struct dw_mipi_dsi *dsi)
256{
257 return dsi->slave || dsi->master;
258}
259
260/*
261 * The controller should generate 2 frames before
262 * preparing the peripheral.
263 */
264static void dw_mipi_dsi_wait_for_two_frames(const struct drm_display_mode *mode)
265{
266 int refresh, two_frames;
267
268 refresh = drm_mode_vrefresh(mode);
269 two_frames = DIV_ROUND_UP(MSEC_PER_SEC, refresh) * 2;
270 msleep(two_frames);
271}
272
273static inline struct dw_mipi_dsi *host_to_dsi(struct mipi_dsi_host *host)
274{
275 return container_of(host, struct dw_mipi_dsi, dsi_host);
276}
277
278static inline struct dw_mipi_dsi *bridge_to_dsi(struct drm_bridge *bridge)
279{
280 return container_of(bridge, struct dw_mipi_dsi, bridge);
281}
282
283static inline void dsi_write(struct dw_mipi_dsi *dsi, u32 reg, u32 val)
284{
285 writel(val, dsi->base + reg);
286}
287
288static inline u32 dsi_read(struct dw_mipi_dsi *dsi, u32 reg)
289{
290 return readl(dsi->base + reg);
291}
292
293static int dw_mipi_dsi_host_attach(struct mipi_dsi_host *host,
294 struct mipi_dsi_device *device)
295{
296 struct dw_mipi_dsi *dsi = host_to_dsi(host);
297 const struct dw_mipi_dsi_plat_data *pdata = dsi->plat_data;
298 struct drm_bridge *bridge;
299 struct drm_panel *panel;
300 int ret;
301
302 if (device->lanes > dsi->plat_data->max_data_lanes) {
303 dev_err(dsi->dev, "the number of data lanes(%u) is too many\n",
304 device->lanes);
305 return -EINVAL;
306 }
307
308 dsi->lanes = device->lanes;
309 dsi->channel = device->channel;
310 dsi->format = device->format;
311 dsi->mode_flags = device->mode_flags;
312
313 ret = drm_of_find_panel_or_bridge(host->dev->of_node, 1, 0,
314 &panel, &bridge);
315 if (ret)
316 return ret;
317
318 if (panel) {
319 bridge = drm_panel_bridge_add(panel, DRM_MODE_CONNECTOR_DSI);
320 if (IS_ERR(bridge))
321 return PTR_ERR(bridge);
322 }
323
324 dsi->panel_bridge = bridge;
325
326 drm_bridge_add(&dsi->bridge);
327
328 if (pdata->host_ops && pdata->host_ops->attach) {
329 ret = pdata->host_ops->attach(pdata->priv_data, device);
330 if (ret < 0)
331 return ret;
332 }
333
334 return 0;
335}
336
337static int dw_mipi_dsi_host_detach(struct mipi_dsi_host *host,
338 struct mipi_dsi_device *device)
339{
340 struct dw_mipi_dsi *dsi = host_to_dsi(host);
341 const struct dw_mipi_dsi_plat_data *pdata = dsi->plat_data;
342 int ret;
343
344 if (pdata->host_ops && pdata->host_ops->detach) {
345 ret = pdata->host_ops->detach(pdata->priv_data, device);
346 if (ret < 0)
347 return ret;
348 }
349
350 drm_of_panel_bridge_remove(host->dev->of_node, 1, 0);
351
352 drm_bridge_remove(&dsi->bridge);
353
354 return 0;
355}
356
357static void dw_mipi_message_config(struct dw_mipi_dsi *dsi,
358 const struct mipi_dsi_msg *msg)
359{
360 bool lpm = msg->flags & MIPI_DSI_MSG_USE_LPM;
361 u32 val = 0;
362
363 if (msg->flags & MIPI_DSI_MSG_REQ_ACK)
364 val |= ACK_RQST_EN;
365 if (lpm)
366 val |= CMD_MODE_ALL_LP;
367
368 dsi_write(dsi, DSI_LPCLK_CTRL, lpm ? 0 : PHY_TXREQUESTCLKHS);
369 dsi_write(dsi, DSI_CMD_MODE_CFG, val);
370}
371
372static int dw_mipi_dsi_gen_pkt_hdr_write(struct dw_mipi_dsi *dsi, u32 hdr_val)
373{
374 int ret;
375 u32 val, mask;
376
377 ret = readl_poll_timeout(dsi->base + DSI_CMD_PKT_STATUS,
378 val, !(val & GEN_CMD_FULL), 1000,
379 CMD_PKT_STATUS_TIMEOUT_US);
380 if (ret) {
381 dev_err(dsi->dev, "failed to get available command FIFO\n");
382 return ret;
383 }
384
385 dsi_write(dsi, DSI_GEN_HDR, hdr_val);
386
387 mask = GEN_CMD_EMPTY | GEN_PLD_W_EMPTY;
388 ret = readl_poll_timeout(dsi->base + DSI_CMD_PKT_STATUS,
389 val, (val & mask) == mask,
390 1000, CMD_PKT_STATUS_TIMEOUT_US);
391 if (ret) {
392 dev_err(dsi->dev, "failed to write command FIFO\n");
393 return ret;
394 }
395
396 return 0;
397}
398
399static int dw_mipi_dsi_write(struct dw_mipi_dsi *dsi,
400 const struct mipi_dsi_packet *packet)
401{
402 const u8 *tx_buf = packet->payload;
403 int len = packet->payload_length, pld_data_bytes = sizeof(u32), ret;
404 __le32 word;
405 u32 val;
406
407 while (len) {
408 if (len < pld_data_bytes) {
409 word = 0;
410 memcpy(&word, tx_buf, len);
411 dsi_write(dsi, DSI_GEN_PLD_DATA, le32_to_cpu(word));
412 len = 0;
413 } else {
414 memcpy(&word, tx_buf, pld_data_bytes);
415 dsi_write(dsi, DSI_GEN_PLD_DATA, le32_to_cpu(word));
416 tx_buf += pld_data_bytes;
417 len -= pld_data_bytes;
418 }
419
420 ret = readl_poll_timeout(dsi->base + DSI_CMD_PKT_STATUS,
421 val, !(val & GEN_PLD_W_FULL), 1000,
422 CMD_PKT_STATUS_TIMEOUT_US);
423 if (ret) {
424 dev_err(dsi->dev,
425 "failed to get available write payload FIFO\n");
426 return ret;
427 }
428 }
429
430 word = 0;
431 memcpy(&word, packet->header, sizeof(packet->header));
432 return dw_mipi_dsi_gen_pkt_hdr_write(dsi, le32_to_cpu(word));
433}
434
435static int dw_mipi_dsi_read(struct dw_mipi_dsi *dsi,
436 const struct mipi_dsi_msg *msg)
437{
438 int i, j, ret, len = msg->rx_len;
439 u8 *buf = msg->rx_buf;
440 u32 val;
441
442 /* Wait end of the read operation */
443 ret = readl_poll_timeout(dsi->base + DSI_CMD_PKT_STATUS,
444 val, !(val & GEN_RD_CMD_BUSY),
445 1000, CMD_PKT_STATUS_TIMEOUT_US);
446 if (ret) {
447 dev_err(dsi->dev, "Timeout during read operation\n");
448 return ret;
449 }
450
451 for (i = 0; i < len; i += 4) {
452 /* Read fifo must not be empty before all bytes are read */
453 ret = readl_poll_timeout(dsi->base + DSI_CMD_PKT_STATUS,
454 val, !(val & GEN_PLD_R_EMPTY),
455 1000, CMD_PKT_STATUS_TIMEOUT_US);
456 if (ret) {
457 dev_err(dsi->dev, "Read payload FIFO is empty\n");
458 return ret;
459 }
460
461 val = dsi_read(dsi, DSI_GEN_PLD_DATA);
462 for (j = 0; j < 4 && j + i < len; j++)
463 buf[i + j] = val >> (8 * j);
464 }
465
466 return ret;
467}
468
469static ssize_t dw_mipi_dsi_host_transfer(struct mipi_dsi_host *host,
470 const struct mipi_dsi_msg *msg)
471{
472 struct dw_mipi_dsi *dsi = host_to_dsi(host);
473 struct mipi_dsi_packet packet;
474 int ret, nb_bytes;
475
476 ret = mipi_dsi_create_packet(&packet, msg);
477 if (ret) {
478 dev_err(dsi->dev, "failed to create packet: %d\n", ret);
479 return ret;
480 }
481
482 dw_mipi_message_config(dsi, msg);
483 if (dsi->slave)
484 dw_mipi_message_config(dsi->slave, msg);
485
486 ret = dw_mipi_dsi_write(dsi, &packet);
487 if (ret)
488 return ret;
489 if (dsi->slave) {
490 ret = dw_mipi_dsi_write(dsi->slave, &packet);
491 if (ret)
492 return ret;
493 }
494
495 if (msg->rx_buf && msg->rx_len) {
496 ret = dw_mipi_dsi_read(dsi, msg);
497 if (ret)
498 return ret;
499 nb_bytes = msg->rx_len;
500 } else {
501 nb_bytes = packet.size;
502 }
503
504 return nb_bytes;
505}
506
507static const struct mipi_dsi_host_ops dw_mipi_dsi_host_ops = {
508 .attach = dw_mipi_dsi_host_attach,
509 .detach = dw_mipi_dsi_host_detach,
510 .transfer = dw_mipi_dsi_host_transfer,
511};
512
513static void dw_mipi_dsi_video_mode_config(struct dw_mipi_dsi *dsi)
514{
515 u32 val;
516
517 /*
518 * TODO dw drv improvements
519 * enabling low power is panel-dependent, we should use the
520 * panel configuration here...
521 */
522 val = ENABLE_LOW_POWER;
523
524 if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_BURST)
525 val |= VID_MODE_TYPE_BURST;
526 else if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE)
527 val |= VID_MODE_TYPE_NON_BURST_SYNC_PULSES;
528 else
529 val |= VID_MODE_TYPE_NON_BURST_SYNC_EVENTS;
530
531#ifdef CONFIG_DEBUG_FS
532 if (dsi->vpg) {
533 val |= VID_MODE_VPG_ENABLE;
534 val |= dsi->vpg_horizontal ? VID_MODE_VPG_HORIZONTAL : 0;
535 }
536#endif /* CONFIG_DEBUG_FS */
537
538 dsi_write(dsi, DSI_VID_MODE_CFG, val);
539}
540
541static void dw_mipi_dsi_set_mode(struct dw_mipi_dsi *dsi,
542 unsigned long mode_flags)
543{
544 dsi_write(dsi, DSI_PWR_UP, RESET);
545
546 if (mode_flags & MIPI_DSI_MODE_VIDEO) {
547 dsi_write(dsi, DSI_MODE_CFG, ENABLE_VIDEO_MODE);
548 dw_mipi_dsi_video_mode_config(dsi);
549 dsi_write(dsi, DSI_LPCLK_CTRL, PHY_TXREQUESTCLKHS);
550 } else {
551 dsi_write(dsi, DSI_MODE_CFG, ENABLE_CMD_MODE);
552 }
553
554 dsi_write(dsi, DSI_PWR_UP, POWERUP);
555}
556
557static void dw_mipi_dsi_disable(struct dw_mipi_dsi *dsi)
558{
559 dsi_write(dsi, DSI_PWR_UP, RESET);
560 dsi_write(dsi, DSI_PHY_RSTZ, PHY_RSTZ);
561}
562
563static void dw_mipi_dsi_init(struct dw_mipi_dsi *dsi)
564{
565 /*
566 * The maximum permitted escape clock is 20MHz and it is derived from
567 * lanebyteclk, which is running at "lane_mbps / 8". Thus we want:
568 *
569 * (lane_mbps >> 3) / esc_clk_division < 20
570 * which is:
571 * (lane_mbps >> 3) / 20 > esc_clk_division
572 */
573 u32 esc_clk_division = (dsi->lane_mbps >> 3) / 20 + 1;
574
575 dsi_write(dsi, DSI_PWR_UP, RESET);
576
577 /*
578 * TODO dw drv improvements
579 * timeout clock division should be computed with the
580 * high speed transmission counter timeout and byte lane...
581 */
582 dsi_write(dsi, DSI_CLKMGR_CFG, TO_CLK_DIVISION(10) |
583 TX_ESC_CLK_DIVISION(esc_clk_division));
584}
585
586static void dw_mipi_dsi_dpi_config(struct dw_mipi_dsi *dsi,
587 const struct drm_display_mode *mode)
588{
589 u32 val = 0, color = 0;
590
591 switch (dsi->format) {
592 case MIPI_DSI_FMT_RGB888:
593 color = DPI_COLOR_CODING_24BIT;
594 break;
595 case MIPI_DSI_FMT_RGB666:
596 color = DPI_COLOR_CODING_18BIT_2 | LOOSELY18_EN;
597 break;
598 case MIPI_DSI_FMT_RGB666_PACKED:
599 color = DPI_COLOR_CODING_18BIT_1;
600 break;
601 case MIPI_DSI_FMT_RGB565:
602 color = DPI_COLOR_CODING_16BIT_1;
603 break;
604 }
605
606 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
607 val |= VSYNC_ACTIVE_LOW;
608 if (mode->flags & DRM_MODE_FLAG_NHSYNC)
609 val |= HSYNC_ACTIVE_LOW;
610
611 dsi_write(dsi, DSI_DPI_VCID, DPI_VCID(dsi->channel));
612 dsi_write(dsi, DSI_DPI_COLOR_CODING, color);
613 dsi_write(dsi, DSI_DPI_CFG_POL, val);
614 /*
615 * TODO dw drv improvements
616 * largest packet sizes during hfp or during vsa/vpb/vfp
617 * should be computed according to byte lane, lane number and only
618 * if sending lp cmds in high speed is enable (PHY_TXREQUESTCLKHS)
619 */
620 dsi_write(dsi, DSI_DPI_LP_CMD_TIM, OUTVACT_LPCMD_TIME(4)
621 | INVACT_LPCMD_TIME(4));
622}
623
624static void dw_mipi_dsi_packet_handler_config(struct dw_mipi_dsi *dsi)
625{
626 dsi_write(dsi, DSI_PCKHDL_CFG, CRC_RX_EN | ECC_RX_EN | BTA_EN);
627}
628
629static void dw_mipi_dsi_video_packet_config(struct dw_mipi_dsi *dsi,
630 const struct drm_display_mode *mode)
631{
632 /*
633 * TODO dw drv improvements
634 * only burst mode is supported here. For non-burst video modes,
635 * we should compute DSI_VID_PKT_SIZE, DSI_VCCR.NUMC &
636 * DSI_VNPCR.NPSIZE... especially because this driver supports
637 * non-burst video modes, see dw_mipi_dsi_video_mode_config()...
638 */
639
640 dsi_write(dsi, DSI_VID_PKT_SIZE,
641 dw_mipi_is_dual_mode(dsi) ?
642 VID_PKT_SIZE(mode->hdisplay / 2) :
643 VID_PKT_SIZE(mode->hdisplay));
644}
645
646static void dw_mipi_dsi_command_mode_config(struct dw_mipi_dsi *dsi)
647{
648 /*
649 * TODO dw drv improvements
650 * compute high speed transmission counter timeout according
651 * to the timeout clock division (TO_CLK_DIVISION) and byte lane...
652 */
653 dsi_write(dsi, DSI_TO_CNT_CFG, HSTX_TO_CNT(1000) | LPRX_TO_CNT(1000));
654 /*
655 * TODO dw drv improvements
656 * the Bus-Turn-Around Timeout Counter should be computed
657 * according to byte lane...
658 */
659 dsi_write(dsi, DSI_BTA_TO_CNT, 0xd00);
660 dsi_write(dsi, DSI_MODE_CFG, ENABLE_CMD_MODE);
661}
662
663/* Get lane byte clock cycles. */
664static u32 dw_mipi_dsi_get_hcomponent_lbcc(struct dw_mipi_dsi *dsi,
665 const struct drm_display_mode *mode,
666 u32 hcomponent)
667{
668 u32 frac, lbcc;
669
670 lbcc = hcomponent * dsi->lane_mbps * MSEC_PER_SEC / 8;
671
672 frac = lbcc % mode->clock;
673 lbcc = lbcc / mode->clock;
674 if (frac)
675 lbcc++;
676
677 return lbcc;
678}
679
680static void dw_mipi_dsi_line_timer_config(struct dw_mipi_dsi *dsi,
681 const struct drm_display_mode *mode)
682{
683 u32 htotal, hsa, hbp, lbcc;
684
685 htotal = mode->htotal;
686 hsa = mode->hsync_end - mode->hsync_start;
687 hbp = mode->htotal - mode->hsync_end;
688
689 /*
690 * TODO dw drv improvements
691 * computations below may be improved...
692 */
693 lbcc = dw_mipi_dsi_get_hcomponent_lbcc(dsi, mode, htotal);
694 dsi_write(dsi, DSI_VID_HLINE_TIME, lbcc);
695
696 lbcc = dw_mipi_dsi_get_hcomponent_lbcc(dsi, mode, hsa);
697 dsi_write(dsi, DSI_VID_HSA_TIME, lbcc);
698
699 lbcc = dw_mipi_dsi_get_hcomponent_lbcc(dsi, mode, hbp);
700 dsi_write(dsi, DSI_VID_HBP_TIME, lbcc);
701}
702
703static void dw_mipi_dsi_vertical_timing_config(struct dw_mipi_dsi *dsi,
704 const struct drm_display_mode *mode)
705{
706 u32 vactive, vsa, vfp, vbp;
707
708 vactive = mode->vdisplay;
709 vsa = mode->vsync_end - mode->vsync_start;
710 vfp = mode->vsync_start - mode->vdisplay;
711 vbp = mode->vtotal - mode->vsync_end;
712
713 dsi_write(dsi, DSI_VID_VACTIVE_LINES, vactive);
714 dsi_write(dsi, DSI_VID_VSA_LINES, vsa);
715 dsi_write(dsi, DSI_VID_VFP_LINES, vfp);
716 dsi_write(dsi, DSI_VID_VBP_LINES, vbp);
717}
718
719static void dw_mipi_dsi_dphy_timing_config(struct dw_mipi_dsi *dsi)
720{
721 u32 hw_version;
722
723 /*
724 * TODO dw drv improvements
725 * data & clock lane timers should be computed according to panel
726 * blankings and to the automatic clock lane control mode...
727 * note: DSI_PHY_TMR_CFG.MAX_RD_TIME should be in line with
728 * DSI_CMD_MODE_CFG.MAX_RD_PKT_SIZE_LP (see CMD_MODE_ALL_LP)
729 */
730
731 hw_version = dsi_read(dsi, DSI_VERSION) & VERSION;
732
733 if (hw_version >= HWVER_131) {
734 dsi_write(dsi, DSI_PHY_TMR_CFG, PHY_HS2LP_TIME_V131(0x40) |
735 PHY_LP2HS_TIME_V131(0x40));
736 dsi_write(dsi, DSI_PHY_TMR_RD_CFG, MAX_RD_TIME_V131(10000));
737 } else {
738 dsi_write(dsi, DSI_PHY_TMR_CFG, PHY_HS2LP_TIME(0x40) |
739 PHY_LP2HS_TIME(0x40) | MAX_RD_TIME(10000));
740 }
741
742 dsi_write(dsi, DSI_PHY_TMR_LPCLK_CFG, PHY_CLKHS2LP_TIME(0x40)
743 | PHY_CLKLP2HS_TIME(0x40));
744}
745
746static void dw_mipi_dsi_dphy_interface_config(struct dw_mipi_dsi *dsi)
747{
748 /*
749 * TODO dw drv improvements
750 * stop wait time should be the maximum between host dsi
751 * and panel stop wait times
752 */
753 dsi_write(dsi, DSI_PHY_IF_CFG, PHY_STOP_WAIT_TIME(0x20) |
754 N_LANES(dsi->lanes));
755}
756
757static void dw_mipi_dsi_dphy_init(struct dw_mipi_dsi *dsi)
758{
759 /* Clear PHY state */
760 dsi_write(dsi, DSI_PHY_RSTZ, PHY_DISFORCEPLL | PHY_DISABLECLK
761 | PHY_RSTZ | PHY_SHUTDOWNZ);
762 dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_UNTESTCLR);
763 dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_TESTCLR);
764 dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_UNTESTCLR);
765}
766
767static void dw_mipi_dsi_dphy_enable(struct dw_mipi_dsi *dsi)
768{
769 u32 val;
770 int ret;
771
772 dsi_write(dsi, DSI_PHY_RSTZ, PHY_ENFORCEPLL | PHY_ENABLECLK |
773 PHY_UNRSTZ | PHY_UNSHUTDOWNZ);
774
775 ret = readl_poll_timeout(dsi->base + DSI_PHY_STATUS, val,
776 val & PHY_LOCK, 1000, PHY_STATUS_TIMEOUT_US);
777 if (ret)
778 DRM_DEBUG_DRIVER("failed to wait phy lock state\n");
779
780 ret = readl_poll_timeout(dsi->base + DSI_PHY_STATUS,
781 val, val & PHY_STOP_STATE_CLK_LANE, 1000,
782 PHY_STATUS_TIMEOUT_US);
783 if (ret)
784 DRM_DEBUG_DRIVER("failed to wait phy clk lane stop state\n");
785}
786
787static void dw_mipi_dsi_clear_err(struct dw_mipi_dsi *dsi)
788{
789 dsi_read(dsi, DSI_INT_ST0);
790 dsi_read(dsi, DSI_INT_ST1);
791 dsi_write(dsi, DSI_INT_MSK0, 0);
792 dsi_write(dsi, DSI_INT_MSK1, 0);
793}
794
795static void dw_mipi_dsi_bridge_post_disable(struct drm_bridge *bridge)
796{
797 struct dw_mipi_dsi *dsi = bridge_to_dsi(bridge);
798 const struct dw_mipi_dsi_phy_ops *phy_ops = dsi->plat_data->phy_ops;
799
800 if (phy_ops->power_off)
801 phy_ops->power_off(dsi->plat_data->priv_data);
802
803 /*
804 * Switch to command mode before panel-bridge post_disable &
805 * panel unprepare.
806 * Note: panel-bridge disable & panel disable has been called
807 * before by the drm framework.
808 */
809 dw_mipi_dsi_set_mode(dsi, 0);
810
811 /*
812 * TODO Only way found to call panel-bridge post_disable &
813 * panel unprepare before the dsi "final" disable...
814 * This needs to be fixed in the drm_bridge framework and the API
815 * needs to be updated to manage our own call chains...
816 */
817 dsi->panel_bridge->funcs->post_disable(dsi->panel_bridge);
818
819 if (dsi->slave) {
820 dw_mipi_dsi_disable(dsi->slave);
821 clk_disable_unprepare(dsi->slave->pclk);
822 pm_runtime_put(dsi->slave->dev);
823 }
824 dw_mipi_dsi_disable(dsi);
825
826 clk_disable_unprepare(dsi->pclk);
827 pm_runtime_put(dsi->dev);
828}
829
830static unsigned int dw_mipi_dsi_get_lanes(struct dw_mipi_dsi *dsi)
831{
832 /* this instance is the slave, so add the master's lanes */
833 if (dsi->master)
834 return dsi->master->lanes + dsi->lanes;
835
836 /* this instance is the master, so add the slave's lanes */
837 if (dsi->slave)
838 return dsi->lanes + dsi->slave->lanes;
839
840 /* single-dsi, so no other instance to consider */
841 return dsi->lanes;
842}
843
844static void dw_mipi_dsi_mode_set(struct dw_mipi_dsi *dsi,
845 const struct drm_display_mode *adjusted_mode)
846{
847 const struct dw_mipi_dsi_phy_ops *phy_ops = dsi->plat_data->phy_ops;
848 void *priv_data = dsi->plat_data->priv_data;
849 int ret;
850 u32 lanes = dw_mipi_dsi_get_lanes(dsi);
851
852 clk_prepare_enable(dsi->pclk);
853
854 ret = phy_ops->get_lane_mbps(priv_data, adjusted_mode, dsi->mode_flags,
855 lanes, dsi->format, &dsi->lane_mbps);
856 if (ret)
857 DRM_DEBUG_DRIVER("Phy get_lane_mbps() failed\n");
858
859 pm_runtime_get_sync(dsi->dev);
860 dw_mipi_dsi_init(dsi);
861 dw_mipi_dsi_dpi_config(dsi, adjusted_mode);
862 dw_mipi_dsi_packet_handler_config(dsi);
863 dw_mipi_dsi_video_mode_config(dsi);
864 dw_mipi_dsi_video_packet_config(dsi, adjusted_mode);
865 dw_mipi_dsi_command_mode_config(dsi);
866 dw_mipi_dsi_line_timer_config(dsi, adjusted_mode);
867 dw_mipi_dsi_vertical_timing_config(dsi, adjusted_mode);
868
869 dw_mipi_dsi_dphy_init(dsi);
870 dw_mipi_dsi_dphy_timing_config(dsi);
871 dw_mipi_dsi_dphy_interface_config(dsi);
872
873 dw_mipi_dsi_clear_err(dsi);
874
875 ret = phy_ops->init(priv_data);
876 if (ret)
877 DRM_DEBUG_DRIVER("Phy init() failed\n");
878
879 dw_mipi_dsi_dphy_enable(dsi);
880
881 dw_mipi_dsi_wait_for_two_frames(adjusted_mode);
882
883 /* Switch to cmd mode for panel-bridge pre_enable & panel prepare */
884 dw_mipi_dsi_set_mode(dsi, 0);
885}
886
887static void dw_mipi_dsi_bridge_mode_set(struct drm_bridge *bridge,
888 const struct drm_display_mode *mode,
889 const struct drm_display_mode *adjusted_mode)
890{
891 struct dw_mipi_dsi *dsi = bridge_to_dsi(bridge);
892
893 dw_mipi_dsi_mode_set(dsi, adjusted_mode);
894 if (dsi->slave)
895 dw_mipi_dsi_mode_set(dsi->slave, adjusted_mode);
896}
897
898static void dw_mipi_dsi_bridge_enable(struct drm_bridge *bridge)
899{
900 struct dw_mipi_dsi *dsi = bridge_to_dsi(bridge);
901 const struct dw_mipi_dsi_phy_ops *phy_ops = dsi->plat_data->phy_ops;
902
903 /* Switch to video mode for panel-bridge enable & panel enable */
904 dw_mipi_dsi_set_mode(dsi, MIPI_DSI_MODE_VIDEO);
905 if (dsi->slave)
906 dw_mipi_dsi_set_mode(dsi->slave, MIPI_DSI_MODE_VIDEO);
907
908 if (phy_ops->power_on)
909 phy_ops->power_on(dsi->plat_data->priv_data);
910}
911
912static enum drm_mode_status
913dw_mipi_dsi_bridge_mode_valid(struct drm_bridge *bridge,
914 const struct drm_display_mode *mode)
915{
916 struct dw_mipi_dsi *dsi = bridge_to_dsi(bridge);
917 const struct dw_mipi_dsi_plat_data *pdata = dsi->plat_data;
918 enum drm_mode_status mode_status = MODE_OK;
919
920 if (pdata->mode_valid)
921 mode_status = pdata->mode_valid(pdata->priv_data, mode);
922
923 return mode_status;
924}
925
926static int dw_mipi_dsi_bridge_attach(struct drm_bridge *bridge)
927{
928 struct dw_mipi_dsi *dsi = bridge_to_dsi(bridge);
929
930 if (!bridge->encoder) {
931 DRM_ERROR("Parent encoder object not found\n");
932 return -ENODEV;
933 }
934
935 /* Set the encoder type as caller does not know it */
936 bridge->encoder->encoder_type = DRM_MODE_ENCODER_DSI;
937
938 /* Attach the panel-bridge to the dsi bridge */
939 return drm_bridge_attach(bridge->encoder, dsi->panel_bridge, bridge);
940}
941
942static const struct drm_bridge_funcs dw_mipi_dsi_bridge_funcs = {
943 .mode_set = dw_mipi_dsi_bridge_mode_set,
944 .enable = dw_mipi_dsi_bridge_enable,
945 .post_disable = dw_mipi_dsi_bridge_post_disable,
946 .mode_valid = dw_mipi_dsi_bridge_mode_valid,
947 .attach = dw_mipi_dsi_bridge_attach,
948};
949
950#ifdef CONFIG_DEBUG_FS
951
952static void dw_mipi_dsi_debugfs_init(struct dw_mipi_dsi *dsi)
953{
954 dsi->debugfs = debugfs_create_dir(dev_name(dsi->dev), NULL);
955 if (IS_ERR(dsi->debugfs)) {
956 dev_err(dsi->dev, "failed to create debugfs root\n");
957 return;
958 }
959
960 debugfs_create_bool("vpg", 0660, dsi->debugfs, &dsi->vpg);
961 debugfs_create_bool("vpg_horizontal", 0660, dsi->debugfs,
962 &dsi->vpg_horizontal);
963}
964
965static void dw_mipi_dsi_debugfs_remove(struct dw_mipi_dsi *dsi)
966{
967 debugfs_remove_recursive(dsi->debugfs);
968}
969
970#else
971
972static void dw_mipi_dsi_debugfs_init(struct dw_mipi_dsi *dsi) { }
973static void dw_mipi_dsi_debugfs_remove(struct dw_mipi_dsi *dsi) { }
974
975#endif /* CONFIG_DEBUG_FS */
976
977static struct dw_mipi_dsi *
978__dw_mipi_dsi_probe(struct platform_device *pdev,
979 const struct dw_mipi_dsi_plat_data *plat_data)
980{
981 struct device *dev = &pdev->dev;
982 struct reset_control *apb_rst;
983 struct dw_mipi_dsi *dsi;
984 struct resource *res;
985 int ret;
986
987 dsi = devm_kzalloc(dev, sizeof(*dsi), GFP_KERNEL);
988 if (!dsi)
989 return ERR_PTR(-ENOMEM);
990
991 dsi->dev = dev;
992 dsi->plat_data = plat_data;
993
994 if (!plat_data->phy_ops->init || !plat_data->phy_ops->get_lane_mbps) {
995 DRM_ERROR("Phy not properly configured\n");
996 return ERR_PTR(-ENODEV);
997 }
998
999 if (!plat_data->base) {
1000 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1001 if (!res)
1002 return ERR_PTR(-ENODEV);
1003
1004 dsi->base = devm_ioremap_resource(dev, res);
1005 if (IS_ERR(dsi->base))
1006 return ERR_PTR(-ENODEV);
1007
1008 } else {
1009 dsi->base = plat_data->base;
1010 }
1011
1012 dsi->pclk = devm_clk_get(dev, "pclk");
1013 if (IS_ERR(dsi->pclk)) {
1014 ret = PTR_ERR(dsi->pclk);
1015 dev_err(dev, "Unable to get pclk: %d\n", ret);
1016 return ERR_PTR(ret);
1017 }
1018
1019 /*
1020 * Note that the reset was not defined in the initial device tree, so
1021 * we have to be prepared for it not being found.
1022 */
1023 apb_rst = devm_reset_control_get_optional_exclusive(dev, "apb");
1024 if (IS_ERR(apb_rst)) {
1025 ret = PTR_ERR(apb_rst);
1026
1027 if (ret != -EPROBE_DEFER)
1028 dev_err(dev, "Unable to get reset control: %d\n", ret);
1029
1030 return ERR_PTR(ret);
1031 }
1032
1033 if (apb_rst) {
1034 ret = clk_prepare_enable(dsi->pclk);
1035 if (ret) {
1036 dev_err(dev, "%s: Failed to enable pclk\n", __func__);
1037 return ERR_PTR(ret);
1038 }
1039
1040 reset_control_assert(apb_rst);
1041 usleep_range(10, 20);
1042 reset_control_deassert(apb_rst);
1043
1044 clk_disable_unprepare(dsi->pclk);
1045 }
1046
1047 dw_mipi_dsi_debugfs_init(dsi);
1048 pm_runtime_enable(dev);
1049
1050 dsi->dsi_host.ops = &dw_mipi_dsi_host_ops;
1051 dsi->dsi_host.dev = dev;
1052 ret = mipi_dsi_host_register(&dsi->dsi_host);
1053 if (ret) {
1054 dev_err(dev, "Failed to register MIPI host: %d\n", ret);
1055 dw_mipi_dsi_debugfs_remove(dsi);
1056 return ERR_PTR(ret);
1057 }
1058
1059 dsi->bridge.driver_private = dsi;
1060 dsi->bridge.funcs = &dw_mipi_dsi_bridge_funcs;
1061#ifdef CONFIG_OF
1062 dsi->bridge.of_node = pdev->dev.of_node;
1063#endif
1064
1065 return dsi;
1066}
1067
1068static void __dw_mipi_dsi_remove(struct dw_mipi_dsi *dsi)
1069{
1070 mipi_dsi_host_unregister(&dsi->dsi_host);
1071
1072 pm_runtime_disable(dsi->dev);
1073 dw_mipi_dsi_debugfs_remove(dsi);
1074}
1075
1076void dw_mipi_dsi_set_slave(struct dw_mipi_dsi *dsi, struct dw_mipi_dsi *slave)
1077{
1078 /* introduce controllers to each other */
1079 dsi->slave = slave;
1080 dsi->slave->master = dsi;
1081
1082 /* migrate settings for already attached displays */
1083 dsi->slave->lanes = dsi->lanes;
1084 dsi->slave->channel = dsi->channel;
1085 dsi->slave->format = dsi->format;
1086 dsi->slave->mode_flags = dsi->mode_flags;
1087}
1088EXPORT_SYMBOL_GPL(dw_mipi_dsi_set_slave);
1089
1090/*
1091 * Probe/remove API, used from platforms based on the DRM bridge API.
1092 */
1093struct dw_mipi_dsi *
1094dw_mipi_dsi_probe(struct platform_device *pdev,
1095 const struct dw_mipi_dsi_plat_data *plat_data)
1096{
1097 return __dw_mipi_dsi_probe(pdev, plat_data);
1098}
1099EXPORT_SYMBOL_GPL(dw_mipi_dsi_probe);
1100
1101void dw_mipi_dsi_remove(struct dw_mipi_dsi *dsi)
1102{
1103 __dw_mipi_dsi_remove(dsi);
1104}
1105EXPORT_SYMBOL_GPL(dw_mipi_dsi_remove);
1106
1107/*
1108 * Bind/unbind API, used from platforms based on the component framework.
1109 */
1110int dw_mipi_dsi_bind(struct dw_mipi_dsi *dsi, struct drm_encoder *encoder)
1111{
1112 int ret;
1113
1114 ret = drm_bridge_attach(encoder, &dsi->bridge, NULL);
1115 if (ret) {
1116 DRM_ERROR("Failed to initialize bridge with drm\n");
1117 return ret;
1118 }
1119
1120 return ret;
1121}
1122EXPORT_SYMBOL_GPL(dw_mipi_dsi_bind);
1123
1124void dw_mipi_dsi_unbind(struct dw_mipi_dsi *dsi)
1125{
1126}
1127EXPORT_SYMBOL_GPL(dw_mipi_dsi_unbind);
1128
1129MODULE_AUTHOR("Chris Zhong <zyw@rock-chips.com>");
1130MODULE_AUTHOR("Philippe Cornu <philippe.cornu@st.com>");
1131MODULE_DESCRIPTION("DW MIPI DSI host controller driver");
1132MODULE_LICENSE("GPL");
1133MODULE_ALIAS("platform:dw-mipi-dsi");