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1/*
2 * Copyright 2014 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 */
25
26#include "amdgpu.h"
27#include "amdgpu_gfx.h"
28#include "amdgpu_rlc.h"
29
30/* delay 0.1 second to enable gfx off feature */
31#define GFX_OFF_DELAY_ENABLE msecs_to_jiffies(100)
32
33/*
34 * GPU GFX IP block helpers function.
35 */
36
37int amdgpu_gfx_mec_queue_to_bit(struct amdgpu_device *adev, int mec,
38 int pipe, int queue)
39{
40 int bit = 0;
41
42 bit += mec * adev->gfx.mec.num_pipe_per_mec
43 * adev->gfx.mec.num_queue_per_pipe;
44 bit += pipe * adev->gfx.mec.num_queue_per_pipe;
45 bit += queue;
46
47 return bit;
48}
49
50void amdgpu_gfx_bit_to_mec_queue(struct amdgpu_device *adev, int bit,
51 int *mec, int *pipe, int *queue)
52{
53 *queue = bit % adev->gfx.mec.num_queue_per_pipe;
54 *pipe = (bit / adev->gfx.mec.num_queue_per_pipe)
55 % adev->gfx.mec.num_pipe_per_mec;
56 *mec = (bit / adev->gfx.mec.num_queue_per_pipe)
57 / adev->gfx.mec.num_pipe_per_mec;
58
59}
60
61bool amdgpu_gfx_is_mec_queue_enabled(struct amdgpu_device *adev,
62 int mec, int pipe, int queue)
63{
64 return test_bit(amdgpu_gfx_mec_queue_to_bit(adev, mec, pipe, queue),
65 adev->gfx.mec.queue_bitmap);
66}
67
68int amdgpu_gfx_me_queue_to_bit(struct amdgpu_device *adev,
69 int me, int pipe, int queue)
70{
71 int bit = 0;
72
73 bit += me * adev->gfx.me.num_pipe_per_me
74 * adev->gfx.me.num_queue_per_pipe;
75 bit += pipe * adev->gfx.me.num_queue_per_pipe;
76 bit += queue;
77
78 return bit;
79}
80
81void amdgpu_gfx_bit_to_me_queue(struct amdgpu_device *adev, int bit,
82 int *me, int *pipe, int *queue)
83{
84 *queue = bit % adev->gfx.me.num_queue_per_pipe;
85 *pipe = (bit / adev->gfx.me.num_queue_per_pipe)
86 % adev->gfx.me.num_pipe_per_me;
87 *me = (bit / adev->gfx.me.num_queue_per_pipe)
88 / adev->gfx.me.num_pipe_per_me;
89}
90
91bool amdgpu_gfx_is_me_queue_enabled(struct amdgpu_device *adev,
92 int me, int pipe, int queue)
93{
94 return test_bit(amdgpu_gfx_me_queue_to_bit(adev, me, pipe, queue),
95 adev->gfx.me.queue_bitmap);
96}
97
98/**
99 * amdgpu_gfx_scratch_get - Allocate a scratch register
100 *
101 * @adev: amdgpu_device pointer
102 * @reg: scratch register mmio offset
103 *
104 * Allocate a CP scratch register for use by the driver (all asics).
105 * Returns 0 on success or -EINVAL on failure.
106 */
107int amdgpu_gfx_scratch_get(struct amdgpu_device *adev, uint32_t *reg)
108{
109 int i;
110
111 i = ffs(adev->gfx.scratch.free_mask);
112 if (i != 0 && i <= adev->gfx.scratch.num_reg) {
113 i--;
114 adev->gfx.scratch.free_mask &= ~(1u << i);
115 *reg = adev->gfx.scratch.reg_base + i;
116 return 0;
117 }
118 return -EINVAL;
119}
120
121/**
122 * amdgpu_gfx_scratch_free - Free a scratch register
123 *
124 * @adev: amdgpu_device pointer
125 * @reg: scratch register mmio offset
126 *
127 * Free a CP scratch register allocated for use by the driver (all asics)
128 */
129void amdgpu_gfx_scratch_free(struct amdgpu_device *adev, uint32_t reg)
130{
131 adev->gfx.scratch.free_mask |= 1u << (reg - adev->gfx.scratch.reg_base);
132}
133
134/**
135 * amdgpu_gfx_parse_disable_cu - Parse the disable_cu module parameter
136 *
137 * @mask: array in which the per-shader array disable masks will be stored
138 * @max_se: number of SEs
139 * @max_sh: number of SHs
140 *
141 * The bitmask of CUs to be disabled in the shader array determined by se and
142 * sh is stored in mask[se * max_sh + sh].
143 */
144void amdgpu_gfx_parse_disable_cu(unsigned *mask, unsigned max_se, unsigned max_sh)
145{
146 unsigned se, sh, cu;
147 const char *p;
148
149 memset(mask, 0, sizeof(*mask) * max_se * max_sh);
150
151 if (!amdgpu_disable_cu || !*amdgpu_disable_cu)
152 return;
153
154 p = amdgpu_disable_cu;
155 for (;;) {
156 char *next;
157 int ret = sscanf(p, "%u.%u.%u", &se, &sh, &cu);
158 if (ret < 3) {
159 DRM_ERROR("amdgpu: could not parse disable_cu\n");
160 return;
161 }
162
163 if (se < max_se && sh < max_sh && cu < 16) {
164 DRM_INFO("amdgpu: disabling CU %u.%u.%u\n", se, sh, cu);
165 mask[se * max_sh + sh] |= 1u << cu;
166 } else {
167 DRM_ERROR("amdgpu: disable_cu %u.%u.%u is out of range\n",
168 se, sh, cu);
169 }
170
171 next = strchr(p, ',');
172 if (!next)
173 break;
174 p = next + 1;
175 }
176}
177
178static bool amdgpu_gfx_is_multipipe_capable(struct amdgpu_device *adev)
179{
180 if (amdgpu_compute_multipipe != -1) {
181 DRM_INFO("amdgpu: forcing compute pipe policy %d\n",
182 amdgpu_compute_multipipe);
183 return amdgpu_compute_multipipe == 1;
184 }
185
186 /* FIXME: spreading the queues across pipes causes perf regressions
187 * on POLARIS11 compute workloads */
188 if (adev->asic_type == CHIP_POLARIS11)
189 return false;
190
191 return adev->gfx.mec.num_mec > 1;
192}
193
194void amdgpu_gfx_compute_queue_acquire(struct amdgpu_device *adev)
195{
196 int i, queue, pipe, mec;
197 bool multipipe_policy = amdgpu_gfx_is_multipipe_capable(adev);
198
199 /* policy for amdgpu compute queue ownership */
200 for (i = 0; i < AMDGPU_MAX_COMPUTE_QUEUES; ++i) {
201 queue = i % adev->gfx.mec.num_queue_per_pipe;
202 pipe = (i / adev->gfx.mec.num_queue_per_pipe)
203 % adev->gfx.mec.num_pipe_per_mec;
204 mec = (i / adev->gfx.mec.num_queue_per_pipe)
205 / adev->gfx.mec.num_pipe_per_mec;
206
207 /* we've run out of HW */
208 if (mec >= adev->gfx.mec.num_mec)
209 break;
210
211 if (multipipe_policy) {
212 /* policy: amdgpu owns the first two queues of the first MEC */
213 if (mec == 0 && queue < 2)
214 set_bit(i, adev->gfx.mec.queue_bitmap);
215 } else {
216 /* policy: amdgpu owns all queues in the first pipe */
217 if (mec == 0 && pipe == 0)
218 set_bit(i, adev->gfx.mec.queue_bitmap);
219 }
220 }
221
222 /* update the number of active compute rings */
223 adev->gfx.num_compute_rings =
224 bitmap_weight(adev->gfx.mec.queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES);
225
226 /* If you hit this case and edited the policy, you probably just
227 * need to increase AMDGPU_MAX_COMPUTE_RINGS */
228 if (WARN_ON(adev->gfx.num_compute_rings > AMDGPU_MAX_COMPUTE_RINGS))
229 adev->gfx.num_compute_rings = AMDGPU_MAX_COMPUTE_RINGS;
230}
231
232void amdgpu_gfx_graphics_queue_acquire(struct amdgpu_device *adev)
233{
234 int i, queue, pipe, me;
235
236 for (i = 0; i < AMDGPU_MAX_GFX_QUEUES; ++i) {
237 queue = i % adev->gfx.me.num_queue_per_pipe;
238 pipe = (i / adev->gfx.me.num_queue_per_pipe)
239 % adev->gfx.me.num_pipe_per_me;
240 me = (i / adev->gfx.me.num_queue_per_pipe)
241 / adev->gfx.me.num_pipe_per_me;
242
243 if (me >= adev->gfx.me.num_me)
244 break;
245 /* policy: amdgpu owns the first queue per pipe at this stage
246 * will extend to mulitple queues per pipe later */
247 if (me == 0 && queue < 1)
248 set_bit(i, adev->gfx.me.queue_bitmap);
249 }
250
251 /* update the number of active graphics rings */
252 adev->gfx.num_gfx_rings =
253 bitmap_weight(adev->gfx.me.queue_bitmap, AMDGPU_MAX_GFX_QUEUES);
254}
255
256static int amdgpu_gfx_kiq_acquire(struct amdgpu_device *adev,
257 struct amdgpu_ring *ring)
258{
259 int queue_bit;
260 int mec, pipe, queue;
261
262 queue_bit = adev->gfx.mec.num_mec
263 * adev->gfx.mec.num_pipe_per_mec
264 * adev->gfx.mec.num_queue_per_pipe;
265
266 while (queue_bit-- >= 0) {
267 if (test_bit(queue_bit, adev->gfx.mec.queue_bitmap))
268 continue;
269
270 amdgpu_gfx_bit_to_mec_queue(adev, queue_bit, &mec, &pipe, &queue);
271
272 /*
273 * 1. Using pipes 2/3 from MEC 2 seems cause problems.
274 * 2. It must use queue id 0, because CGPG_IDLE/SAVE/LOAD/RUN
275 * only can be issued on queue 0.
276 */
277 if ((mec == 1 && pipe > 1) || queue != 0)
278 continue;
279
280 ring->me = mec + 1;
281 ring->pipe = pipe;
282 ring->queue = queue;
283
284 return 0;
285 }
286
287 dev_err(adev->dev, "Failed to find a queue for KIQ\n");
288 return -EINVAL;
289}
290
291int amdgpu_gfx_kiq_init_ring(struct amdgpu_device *adev,
292 struct amdgpu_ring *ring,
293 struct amdgpu_irq_src *irq)
294{
295 struct amdgpu_kiq *kiq = &adev->gfx.kiq;
296 int r = 0;
297
298 spin_lock_init(&kiq->ring_lock);
299
300 r = amdgpu_device_wb_get(adev, &adev->virt.reg_val_offs);
301 if (r)
302 return r;
303
304 ring->adev = NULL;
305 ring->ring_obj = NULL;
306 ring->use_doorbell = true;
307 ring->doorbell_index = adev->doorbell_index.kiq;
308
309 r = amdgpu_gfx_kiq_acquire(adev, ring);
310 if (r)
311 return r;
312
313 ring->eop_gpu_addr = kiq->eop_gpu_addr;
314 sprintf(ring->name, "kiq_%d.%d.%d", ring->me, ring->pipe, ring->queue);
315 r = amdgpu_ring_init(adev, ring, 1024,
316 irq, AMDGPU_CP_KIQ_IRQ_DRIVER0);
317 if (r)
318 dev_warn(adev->dev, "(%d) failed to init kiq ring\n", r);
319
320 return r;
321}
322
323void amdgpu_gfx_kiq_free_ring(struct amdgpu_ring *ring,
324 struct amdgpu_irq_src *irq)
325{
326 amdgpu_device_wb_free(ring->adev, ring->adev->virt.reg_val_offs);
327 amdgpu_ring_fini(ring);
328}
329
330void amdgpu_gfx_kiq_fini(struct amdgpu_device *adev)
331{
332 struct amdgpu_kiq *kiq = &adev->gfx.kiq;
333
334 amdgpu_bo_free_kernel(&kiq->eop_obj, &kiq->eop_gpu_addr, NULL);
335}
336
337int amdgpu_gfx_kiq_init(struct amdgpu_device *adev,
338 unsigned hpd_size)
339{
340 int r;
341 u32 *hpd;
342 struct amdgpu_kiq *kiq = &adev->gfx.kiq;
343
344 r = amdgpu_bo_create_kernel(adev, hpd_size, PAGE_SIZE,
345 AMDGPU_GEM_DOMAIN_GTT, &kiq->eop_obj,
346 &kiq->eop_gpu_addr, (void **)&hpd);
347 if (r) {
348 dev_warn(adev->dev, "failed to create KIQ bo (%d).\n", r);
349 return r;
350 }
351
352 memset(hpd, 0, hpd_size);
353
354 r = amdgpu_bo_reserve(kiq->eop_obj, true);
355 if (unlikely(r != 0))
356 dev_warn(adev->dev, "(%d) reserve kiq eop bo failed\n", r);
357 amdgpu_bo_kunmap(kiq->eop_obj);
358 amdgpu_bo_unreserve(kiq->eop_obj);
359
360 return 0;
361}
362
363/* create MQD for each compute/gfx queue */
364int amdgpu_gfx_mqd_sw_init(struct amdgpu_device *adev,
365 unsigned mqd_size)
366{
367 struct amdgpu_ring *ring = NULL;
368 int r, i;
369
370 /* create MQD for KIQ */
371 ring = &adev->gfx.kiq.ring;
372 if (!ring->mqd_obj) {
373 /* originaly the KIQ MQD is put in GTT domain, but for SRIOV VRAM domain is a must
374 * otherwise hypervisor trigger SAVE_VF fail after driver unloaded which mean MQD
375 * deallocated and gart_unbind, to strict diverage we decide to use VRAM domain for
376 * KIQ MQD no matter SRIOV or Bare-metal
377 */
378 r = amdgpu_bo_create_kernel(adev, mqd_size, PAGE_SIZE,
379 AMDGPU_GEM_DOMAIN_VRAM, &ring->mqd_obj,
380 &ring->mqd_gpu_addr, &ring->mqd_ptr);
381 if (r) {
382 dev_warn(adev->dev, "failed to create ring mqd ob (%d)", r);
383 return r;
384 }
385
386 /* prepare MQD backup */
387 adev->gfx.mec.mqd_backup[AMDGPU_MAX_COMPUTE_RINGS] = kmalloc(mqd_size, GFP_KERNEL);
388 if (!adev->gfx.mec.mqd_backup[AMDGPU_MAX_COMPUTE_RINGS])
389 dev_warn(adev->dev, "no memory to create MQD backup for ring %s\n", ring->name);
390 }
391
392 if (adev->asic_type >= CHIP_NAVI10 && amdgpu_async_gfx_ring) {
393 /* create MQD for each KGQ */
394 for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
395 ring = &adev->gfx.gfx_ring[i];
396 if (!ring->mqd_obj) {
397 r = amdgpu_bo_create_kernel(adev, mqd_size, PAGE_SIZE,
398 AMDGPU_GEM_DOMAIN_GTT, &ring->mqd_obj,
399 &ring->mqd_gpu_addr, &ring->mqd_ptr);
400 if (r) {
401 dev_warn(adev->dev, "failed to create ring mqd bo (%d)", r);
402 return r;
403 }
404
405 /* prepare MQD backup */
406 adev->gfx.me.mqd_backup[i] = kmalloc(mqd_size, GFP_KERNEL);
407 if (!adev->gfx.me.mqd_backup[i])
408 dev_warn(adev->dev, "no memory to create MQD backup for ring %s\n", ring->name);
409 }
410 }
411 }
412
413 /* create MQD for each KCQ */
414 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
415 ring = &adev->gfx.compute_ring[i];
416 if (!ring->mqd_obj) {
417 r = amdgpu_bo_create_kernel(adev, mqd_size, PAGE_SIZE,
418 AMDGPU_GEM_DOMAIN_GTT, &ring->mqd_obj,
419 &ring->mqd_gpu_addr, &ring->mqd_ptr);
420 if (r) {
421 dev_warn(adev->dev, "failed to create ring mqd bo (%d)", r);
422 return r;
423 }
424
425 /* prepare MQD backup */
426 adev->gfx.mec.mqd_backup[i] = kmalloc(mqd_size, GFP_KERNEL);
427 if (!adev->gfx.mec.mqd_backup[i])
428 dev_warn(adev->dev, "no memory to create MQD backup for ring %s\n", ring->name);
429 }
430 }
431
432 return 0;
433}
434
435void amdgpu_gfx_mqd_sw_fini(struct amdgpu_device *adev)
436{
437 struct amdgpu_ring *ring = NULL;
438 int i;
439
440 if (adev->asic_type >= CHIP_NAVI10 && amdgpu_async_gfx_ring) {
441 for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
442 ring = &adev->gfx.gfx_ring[i];
443 kfree(adev->gfx.me.mqd_backup[i]);
444 amdgpu_bo_free_kernel(&ring->mqd_obj,
445 &ring->mqd_gpu_addr,
446 &ring->mqd_ptr);
447 }
448 }
449
450 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
451 ring = &adev->gfx.compute_ring[i];
452 kfree(adev->gfx.mec.mqd_backup[i]);
453 amdgpu_bo_free_kernel(&ring->mqd_obj,
454 &ring->mqd_gpu_addr,
455 &ring->mqd_ptr);
456 }
457
458 ring = &adev->gfx.kiq.ring;
459 if (adev->asic_type >= CHIP_NAVI10 && amdgpu_async_gfx_ring)
460 kfree(adev->gfx.me.mqd_backup[AMDGPU_MAX_GFX_RINGS]);
461 kfree(adev->gfx.mec.mqd_backup[AMDGPU_MAX_COMPUTE_RINGS]);
462 amdgpu_bo_free_kernel(&ring->mqd_obj,
463 &ring->mqd_gpu_addr,
464 &ring->mqd_ptr);
465}
466
467int amdgpu_gfx_disable_kcq(struct amdgpu_device *adev)
468{
469 struct amdgpu_kiq *kiq = &adev->gfx.kiq;
470 struct amdgpu_ring *kiq_ring = &kiq->ring;
471 int i;
472
473 if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues)
474 return -EINVAL;
475
476 if (amdgpu_ring_alloc(kiq_ring, kiq->pmf->unmap_queues_size *
477 adev->gfx.num_compute_rings))
478 return -ENOMEM;
479
480 for (i = 0; i < adev->gfx.num_compute_rings; i++)
481 kiq->pmf->kiq_unmap_queues(kiq_ring, &adev->gfx.compute_ring[i],
482 RESET_QUEUES, 0, 0);
483
484 return amdgpu_ring_test_ring(kiq_ring);
485}
486
487int amdgpu_gfx_enable_kcq(struct amdgpu_device *adev)
488{
489 struct amdgpu_kiq *kiq = &adev->gfx.kiq;
490 struct amdgpu_ring *kiq_ring = &adev->gfx.kiq.ring;
491 uint64_t queue_mask = 0;
492 int r, i;
493
494 if (!kiq->pmf || !kiq->pmf->kiq_map_queues || !kiq->pmf->kiq_set_resources)
495 return -EINVAL;
496
497 for (i = 0; i < AMDGPU_MAX_COMPUTE_QUEUES; ++i) {
498 if (!test_bit(i, adev->gfx.mec.queue_bitmap))
499 continue;
500
501 /* This situation may be hit in the future if a new HW
502 * generation exposes more than 64 queues. If so, the
503 * definition of queue_mask needs updating */
504 if (WARN_ON(i > (sizeof(queue_mask)*8))) {
505 DRM_ERROR("Invalid KCQ enabled: %d\n", i);
506 break;
507 }
508
509 queue_mask |= (1ull << i);
510 }
511
512 DRM_INFO("kiq ring mec %d pipe %d q %d\n", kiq_ring->me, kiq_ring->pipe,
513 kiq_ring->queue);
514
515 r = amdgpu_ring_alloc(kiq_ring, kiq->pmf->map_queues_size *
516 adev->gfx.num_compute_rings +
517 kiq->pmf->set_resources_size);
518 if (r) {
519 DRM_ERROR("Failed to lock KIQ (%d).\n", r);
520 return r;
521 }
522
523 kiq->pmf->kiq_set_resources(kiq_ring, queue_mask);
524 for (i = 0; i < adev->gfx.num_compute_rings; i++)
525 kiq->pmf->kiq_map_queues(kiq_ring, &adev->gfx.compute_ring[i]);
526
527 r = amdgpu_ring_test_helper(kiq_ring);
528 if (r)
529 DRM_ERROR("KCQ enable failed\n");
530
531 return r;
532}
533
534/* amdgpu_gfx_off_ctrl - Handle gfx off feature enable/disable
535 *
536 * @adev: amdgpu_device pointer
537 * @bool enable true: enable gfx off feature, false: disable gfx off feature
538 *
539 * 1. gfx off feature will be enabled by gfx ip after gfx cg gp enabled.
540 * 2. other client can send request to disable gfx off feature, the request should be honored.
541 * 3. other client can cancel their request of disable gfx off feature
542 * 4. other client should not send request to enable gfx off feature before disable gfx off feature.
543 */
544
545void amdgpu_gfx_off_ctrl(struct amdgpu_device *adev, bool enable)
546{
547 if (!(adev->pm.pp_feature & PP_GFXOFF_MASK))
548 return;
549
550 if (!is_support_sw_smu(adev) &&
551 (!adev->powerplay.pp_funcs ||
552 !adev->powerplay.pp_funcs->set_powergating_by_smu))
553 return;
554
555
556 mutex_lock(&adev->gfx.gfx_off_mutex);
557
558 if (!enable)
559 adev->gfx.gfx_off_req_count++;
560 else if (adev->gfx.gfx_off_req_count > 0)
561 adev->gfx.gfx_off_req_count--;
562
563 if (enable && !adev->gfx.gfx_off_state && !adev->gfx.gfx_off_req_count) {
564 schedule_delayed_work(&adev->gfx.gfx_off_delay_work, GFX_OFF_DELAY_ENABLE);
565 } else if (!enable && adev->gfx.gfx_off_state) {
566 if (!amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_GFX, false))
567 adev->gfx.gfx_off_state = false;
568 }
569
570 mutex_unlock(&adev->gfx.gfx_off_mutex);
571}