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1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Generic driver for memory-mapped GPIO controllers.
4 *
5 * Copyright 2008 MontaVista Software, Inc.
6 * Copyright 2008,2010 Anton Vorontsov <cbouatmailru@gmail.com>
7 *
8 * ....``.```~~~~````.`.`.`.`.```````'',,,.........`````......`.......
9 * ...`` ```````..
10 * ..The simplest form of a GPIO controller that the driver supports is``
11 * `.just a single "data" register, where GPIO state can be read and/or `
12 * `,..written. ,,..``~~~~ .....``.`.`.~~.```.`.........``````.```````
13 * `````````
14 ___
15_/~~|___/~| . ```~~~~~~ ___/___\___ ,~.`.`.`.`````.~~...,,,,...
16__________|~$@~~~ %~ /o*o*o*o*o*o\ .. Implementing such a GPIO .
17o ` ~~~~\___/~~~~ ` controller in FPGA is ,.`
18 `....trivial..'~`.```.```
19 * ```````
20 * .```````~~~~`..`.``.``.
21 * . The driver supports `... ,..```.`~~~```````````````....````.``,,
22 * . big-endian notation, just`. .. A bit more sophisticated controllers ,
23 * . register the device with -be`. .with a pair of set/clear-bit registers ,
24 * `.. suffix. ```~~`````....`.` . affecting the data register and the .`
25 * ``.`.``...``` ```.. output pins are also supported.`
26 * ^^ `````.`````````.,``~``~``~~``````
27 * . ^^
28 * ,..`.`.`...````````````......`.`.`.`.`.`..`.`.`..
29 * .. The expectation is that in at least some cases . ,-~~~-,
30 * .this will be used with roll-your-own ASIC/FPGA .` \ /
31 * .logic in Verilog or VHDL. ~~~`````````..`````~~` \ /
32 * ..````````......``````````` \o_
33 * |
34 * ^^ / \
35 *
36 * ...`````~~`.....``.`..........``````.`.``.```........``.
37 * ` 8, 16, 32 and 64 bits registers are supported, and``.
38 * . the number of GPIOs is determined by the width of ~
39 * .. the registers. ,............```.`.`..`.`.~~~.`.`.`~
40 * `.......````.```
41 */
42
43#include <linux/init.h>
44#include <linux/err.h>
45#include <linux/bug.h>
46#include <linux/kernel.h>
47#include <linux/module.h>
48#include <linux/spinlock.h>
49#include <linux/compiler.h>
50#include <linux/types.h>
51#include <linux/errno.h>
52#include <linux/log2.h>
53#include <linux/ioport.h>
54#include <linux/io.h>
55#include <linux/gpio/driver.h>
56#include <linux/slab.h>
57#include <linux/bitops.h>
58#include <linux/platform_device.h>
59#include <linux/mod_devicetable.h>
60#include <linux/of.h>
61#include <linux/of_device.h>
62
63static void bgpio_write8(void __iomem *reg, unsigned long data)
64{
65 writeb(data, reg);
66}
67
68static unsigned long bgpio_read8(void __iomem *reg)
69{
70 return readb(reg);
71}
72
73static void bgpio_write16(void __iomem *reg, unsigned long data)
74{
75 writew(data, reg);
76}
77
78static unsigned long bgpio_read16(void __iomem *reg)
79{
80 return readw(reg);
81}
82
83static void bgpio_write32(void __iomem *reg, unsigned long data)
84{
85 writel(data, reg);
86}
87
88static unsigned long bgpio_read32(void __iomem *reg)
89{
90 return readl(reg);
91}
92
93#if BITS_PER_LONG >= 64
94static void bgpio_write64(void __iomem *reg, unsigned long data)
95{
96 writeq(data, reg);
97}
98
99static unsigned long bgpio_read64(void __iomem *reg)
100{
101 return readq(reg);
102}
103#endif /* BITS_PER_LONG >= 64 */
104
105static void bgpio_write16be(void __iomem *reg, unsigned long data)
106{
107 iowrite16be(data, reg);
108}
109
110static unsigned long bgpio_read16be(void __iomem *reg)
111{
112 return ioread16be(reg);
113}
114
115static void bgpio_write32be(void __iomem *reg, unsigned long data)
116{
117 iowrite32be(data, reg);
118}
119
120static unsigned long bgpio_read32be(void __iomem *reg)
121{
122 return ioread32be(reg);
123}
124
125static unsigned long bgpio_line2mask(struct gpio_chip *gc, unsigned int line)
126{
127 if (gc->be_bits)
128 return BIT(gc->bgpio_bits - 1 - line);
129 return BIT(line);
130}
131
132static int bgpio_get_set(struct gpio_chip *gc, unsigned int gpio)
133{
134 unsigned long pinmask = bgpio_line2mask(gc, gpio);
135 bool dir = !!(gc->bgpio_dir & pinmask);
136
137 if (dir)
138 return !!(gc->read_reg(gc->reg_set) & pinmask);
139 else
140 return !!(gc->read_reg(gc->reg_dat) & pinmask);
141}
142
143/*
144 * This assumes that the bits in the GPIO register are in native endianness.
145 * We only assign the function pointer if we have that.
146 */
147static int bgpio_get_set_multiple(struct gpio_chip *gc, unsigned long *mask,
148 unsigned long *bits)
149{
150 unsigned long get_mask = 0;
151 unsigned long set_mask = 0;
152
153 /* Make sure we first clear any bits that are zero when we read the register */
154 *bits &= ~*mask;
155
156 set_mask = *mask & gc->bgpio_dir;
157 get_mask = *mask & ~gc->bgpio_dir;
158
159 if (set_mask)
160 *bits |= gc->read_reg(gc->reg_set) & set_mask;
161 if (get_mask)
162 *bits |= gc->read_reg(gc->reg_dat) & get_mask;
163
164 return 0;
165}
166
167static int bgpio_get(struct gpio_chip *gc, unsigned int gpio)
168{
169 return !!(gc->read_reg(gc->reg_dat) & bgpio_line2mask(gc, gpio));
170}
171
172/*
173 * This only works if the bits in the GPIO register are in native endianness.
174 */
175static int bgpio_get_multiple(struct gpio_chip *gc, unsigned long *mask,
176 unsigned long *bits)
177{
178 /* Make sure we first clear any bits that are zero when we read the register */
179 *bits &= ~*mask;
180 *bits |= gc->read_reg(gc->reg_dat) & *mask;
181 return 0;
182}
183
184/*
185 * With big endian mirrored bit order it becomes more tedious.
186 */
187static int bgpio_get_multiple_be(struct gpio_chip *gc, unsigned long *mask,
188 unsigned long *bits)
189{
190 unsigned long readmask = 0;
191 unsigned long val;
192 int bit;
193
194 /* Make sure we first clear any bits that are zero when we read the register */
195 *bits &= ~*mask;
196
197 /* Create a mirrored mask */
198 bit = -1;
199 while ((bit = find_next_bit(mask, gc->ngpio, bit + 1)) < gc->ngpio)
200 readmask |= bgpio_line2mask(gc, bit);
201
202 /* Read the register */
203 val = gc->read_reg(gc->reg_dat) & readmask;
204
205 /*
206 * Mirror the result into the "bits" result, this will give line 0
207 * in bit 0 ... line 31 in bit 31 for a 32bit register.
208 */
209 bit = -1;
210 while ((bit = find_next_bit(&val, gc->ngpio, bit + 1)) < gc->ngpio)
211 *bits |= bgpio_line2mask(gc, bit);
212
213 return 0;
214}
215
216static void bgpio_set_none(struct gpio_chip *gc, unsigned int gpio, int val)
217{
218}
219
220static void bgpio_set(struct gpio_chip *gc, unsigned int gpio, int val)
221{
222 unsigned long mask = bgpio_line2mask(gc, gpio);
223 unsigned long flags;
224
225 spin_lock_irqsave(&gc->bgpio_lock, flags);
226
227 if (val)
228 gc->bgpio_data |= mask;
229 else
230 gc->bgpio_data &= ~mask;
231
232 gc->write_reg(gc->reg_dat, gc->bgpio_data);
233
234 spin_unlock_irqrestore(&gc->bgpio_lock, flags);
235}
236
237static void bgpio_set_with_clear(struct gpio_chip *gc, unsigned int gpio,
238 int val)
239{
240 unsigned long mask = bgpio_line2mask(gc, gpio);
241
242 if (val)
243 gc->write_reg(gc->reg_set, mask);
244 else
245 gc->write_reg(gc->reg_clr, mask);
246}
247
248static void bgpio_set_set(struct gpio_chip *gc, unsigned int gpio, int val)
249{
250 unsigned long mask = bgpio_line2mask(gc, gpio);
251 unsigned long flags;
252
253 spin_lock_irqsave(&gc->bgpio_lock, flags);
254
255 if (val)
256 gc->bgpio_data |= mask;
257 else
258 gc->bgpio_data &= ~mask;
259
260 gc->write_reg(gc->reg_set, gc->bgpio_data);
261
262 spin_unlock_irqrestore(&gc->bgpio_lock, flags);
263}
264
265static void bgpio_multiple_get_masks(struct gpio_chip *gc,
266 unsigned long *mask, unsigned long *bits,
267 unsigned long *set_mask,
268 unsigned long *clear_mask)
269{
270 int i;
271
272 *set_mask = 0;
273 *clear_mask = 0;
274
275 for (i = 0; i < gc->bgpio_bits; i++) {
276 if (*mask == 0)
277 break;
278 if (__test_and_clear_bit(i, mask)) {
279 if (test_bit(i, bits))
280 *set_mask |= bgpio_line2mask(gc, i);
281 else
282 *clear_mask |= bgpio_line2mask(gc, i);
283 }
284 }
285}
286
287static void bgpio_set_multiple_single_reg(struct gpio_chip *gc,
288 unsigned long *mask,
289 unsigned long *bits,
290 void __iomem *reg)
291{
292 unsigned long flags;
293 unsigned long set_mask, clear_mask;
294
295 spin_lock_irqsave(&gc->bgpio_lock, flags);
296
297 bgpio_multiple_get_masks(gc, mask, bits, &set_mask, &clear_mask);
298
299 gc->bgpio_data |= set_mask;
300 gc->bgpio_data &= ~clear_mask;
301
302 gc->write_reg(reg, gc->bgpio_data);
303
304 spin_unlock_irqrestore(&gc->bgpio_lock, flags);
305}
306
307static void bgpio_set_multiple(struct gpio_chip *gc, unsigned long *mask,
308 unsigned long *bits)
309{
310 bgpio_set_multiple_single_reg(gc, mask, bits, gc->reg_dat);
311}
312
313static void bgpio_set_multiple_set(struct gpio_chip *gc, unsigned long *mask,
314 unsigned long *bits)
315{
316 bgpio_set_multiple_single_reg(gc, mask, bits, gc->reg_set);
317}
318
319static void bgpio_set_multiple_with_clear(struct gpio_chip *gc,
320 unsigned long *mask,
321 unsigned long *bits)
322{
323 unsigned long set_mask, clear_mask;
324
325 bgpio_multiple_get_masks(gc, mask, bits, &set_mask, &clear_mask);
326
327 if (set_mask)
328 gc->write_reg(gc->reg_set, set_mask);
329 if (clear_mask)
330 gc->write_reg(gc->reg_clr, clear_mask);
331}
332
333static int bgpio_simple_dir_in(struct gpio_chip *gc, unsigned int gpio)
334{
335 return 0;
336}
337
338static int bgpio_dir_out_err(struct gpio_chip *gc, unsigned int gpio,
339 int val)
340{
341 return -EINVAL;
342}
343
344static int bgpio_simple_dir_out(struct gpio_chip *gc, unsigned int gpio,
345 int val)
346{
347 gc->set(gc, gpio, val);
348
349 return 0;
350}
351
352static int bgpio_dir_in(struct gpio_chip *gc, unsigned int gpio)
353{
354 unsigned long flags;
355
356 spin_lock_irqsave(&gc->bgpio_lock, flags);
357
358 gc->bgpio_dir &= ~bgpio_line2mask(gc, gpio);
359
360 if (gc->reg_dir_in)
361 gc->write_reg(gc->reg_dir_in, ~gc->bgpio_dir);
362 if (gc->reg_dir_out)
363 gc->write_reg(gc->reg_dir_out, gc->bgpio_dir);
364
365 spin_unlock_irqrestore(&gc->bgpio_lock, flags);
366
367 return 0;
368}
369
370static int bgpio_get_dir(struct gpio_chip *gc, unsigned int gpio)
371{
372 /* Return 0 if output, 1 if input */
373 if (gc->bgpio_dir_unreadable)
374 return !(gc->bgpio_dir & bgpio_line2mask(gc, gpio));
375 if (gc->reg_dir_out)
376 return !(gc->read_reg(gc->reg_dir_out) & bgpio_line2mask(gc, gpio));
377 if (gc->reg_dir_in)
378 return !!(gc->read_reg(gc->reg_dir_in) & bgpio_line2mask(gc, gpio));
379
380 /* This should not happen */
381 return 1;
382}
383
384static int bgpio_dir_out(struct gpio_chip *gc, unsigned int gpio, int val)
385{
386 unsigned long flags;
387
388 gc->set(gc, gpio, val);
389
390 spin_lock_irqsave(&gc->bgpio_lock, flags);
391
392 gc->bgpio_dir |= bgpio_line2mask(gc, gpio);
393
394 if (gc->reg_dir_in)
395 gc->write_reg(gc->reg_dir_in, ~gc->bgpio_dir);
396 if (gc->reg_dir_out)
397 gc->write_reg(gc->reg_dir_out, gc->bgpio_dir);
398
399 spin_unlock_irqrestore(&gc->bgpio_lock, flags);
400
401 return 0;
402}
403
404static int bgpio_setup_accessors(struct device *dev,
405 struct gpio_chip *gc,
406 bool byte_be)
407{
408
409 switch (gc->bgpio_bits) {
410 case 8:
411 gc->read_reg = bgpio_read8;
412 gc->write_reg = bgpio_write8;
413 break;
414 case 16:
415 if (byte_be) {
416 gc->read_reg = bgpio_read16be;
417 gc->write_reg = bgpio_write16be;
418 } else {
419 gc->read_reg = bgpio_read16;
420 gc->write_reg = bgpio_write16;
421 }
422 break;
423 case 32:
424 if (byte_be) {
425 gc->read_reg = bgpio_read32be;
426 gc->write_reg = bgpio_write32be;
427 } else {
428 gc->read_reg = bgpio_read32;
429 gc->write_reg = bgpio_write32;
430 }
431 break;
432#if BITS_PER_LONG >= 64
433 case 64:
434 if (byte_be) {
435 dev_err(dev,
436 "64 bit big endian byte order unsupported\n");
437 return -EINVAL;
438 } else {
439 gc->read_reg = bgpio_read64;
440 gc->write_reg = bgpio_write64;
441 }
442 break;
443#endif /* BITS_PER_LONG >= 64 */
444 default:
445 dev_err(dev, "unsupported data width %u bits\n", gc->bgpio_bits);
446 return -EINVAL;
447 }
448
449 return 0;
450}
451
452/*
453 * Create the device and allocate the resources. For setting GPIO's there are
454 * three supported configurations:
455 *
456 * - single input/output register resource (named "dat").
457 * - set/clear pair (named "set" and "clr").
458 * - single output register resource and single input resource ("set" and
459 * dat").
460 *
461 * For the single output register, this drives a 1 by setting a bit and a zero
462 * by clearing a bit. For the set clr pair, this drives a 1 by setting a bit
463 * in the set register and clears it by setting a bit in the clear register.
464 * The configuration is detected by which resources are present.
465 *
466 * For setting the GPIO direction, there are three supported configurations:
467 *
468 * - simple bidirection GPIO that requires no configuration.
469 * - an output direction register (named "dirout") where a 1 bit
470 * indicates the GPIO is an output.
471 * - an input direction register (named "dirin") where a 1 bit indicates
472 * the GPIO is an input.
473 */
474static int bgpio_setup_io(struct gpio_chip *gc,
475 void __iomem *dat,
476 void __iomem *set,
477 void __iomem *clr,
478 unsigned long flags)
479{
480
481 gc->reg_dat = dat;
482 if (!gc->reg_dat)
483 return -EINVAL;
484
485 if (set && clr) {
486 gc->reg_set = set;
487 gc->reg_clr = clr;
488 gc->set = bgpio_set_with_clear;
489 gc->set_multiple = bgpio_set_multiple_with_clear;
490 } else if (set && !clr) {
491 gc->reg_set = set;
492 gc->set = bgpio_set_set;
493 gc->set_multiple = bgpio_set_multiple_set;
494 } else if (flags & BGPIOF_NO_OUTPUT) {
495 gc->set = bgpio_set_none;
496 gc->set_multiple = NULL;
497 } else {
498 gc->set = bgpio_set;
499 gc->set_multiple = bgpio_set_multiple;
500 }
501
502 if (!(flags & BGPIOF_UNREADABLE_REG_SET) &&
503 (flags & BGPIOF_READ_OUTPUT_REG_SET)) {
504 gc->get = bgpio_get_set;
505 if (!gc->be_bits)
506 gc->get_multiple = bgpio_get_set_multiple;
507 /*
508 * We deliberately avoid assigning the ->get_multiple() call
509 * for big endian mirrored registers which are ALSO reflecting
510 * their value in the set register when used as output. It is
511 * simply too much complexity, let the GPIO core fall back to
512 * reading each line individually in that fringe case.
513 */
514 } else {
515 gc->get = bgpio_get;
516 if (gc->be_bits)
517 gc->get_multiple = bgpio_get_multiple_be;
518 else
519 gc->get_multiple = bgpio_get_multiple;
520 }
521
522 return 0;
523}
524
525static int bgpio_setup_direction(struct gpio_chip *gc,
526 void __iomem *dirout,
527 void __iomem *dirin,
528 unsigned long flags)
529{
530 if (dirout || dirin) {
531 gc->reg_dir_out = dirout;
532 gc->reg_dir_in = dirin;
533 gc->direction_output = bgpio_dir_out;
534 gc->direction_input = bgpio_dir_in;
535 gc->get_direction = bgpio_get_dir;
536 } else {
537 if (flags & BGPIOF_NO_OUTPUT)
538 gc->direction_output = bgpio_dir_out_err;
539 else
540 gc->direction_output = bgpio_simple_dir_out;
541 gc->direction_input = bgpio_simple_dir_in;
542 }
543
544 return 0;
545}
546
547static int bgpio_request(struct gpio_chip *chip, unsigned gpio_pin)
548{
549 if (gpio_pin < chip->ngpio)
550 return 0;
551
552 return -EINVAL;
553}
554
555/**
556 * bgpio_init() - Initialize generic GPIO accessor functions
557 * @gc: the GPIO chip to set up
558 * @dev: the parent device of the new GPIO chip (compulsory)
559 * @sz: the size (width) of the MMIO registers in bytes, typically 1, 2 or 4
560 * @dat: MMIO address for the register to READ the value of the GPIO lines, it
561 * is expected that a 1 in the corresponding bit in this register means the
562 * line is asserted
563 * @set: MMIO address for the register to SET the value of the GPIO lines, it is
564 * expected that we write the line with 1 in this register to drive the GPIO line
565 * high.
566 * @clr: MMIO address for the register to CLEAR the value of the GPIO lines, it is
567 * expected that we write the line with 1 in this register to drive the GPIO line
568 * low. It is allowed to leave this address as NULL, in that case the SET register
569 * will be assumed to also clear the GPIO lines, by actively writing the line
570 * with 0.
571 * @dirout: MMIO address for the register to set the line as OUTPUT. It is assumed
572 * that setting a line to 1 in this register will turn that line into an
573 * output line. Conversely, setting the line to 0 will turn that line into
574 * an input.
575 * @dirin: MMIO address for the register to set this line as INPUT. It is assumed
576 * that setting a line to 1 in this register will turn that line into an
577 * input line. Conversely, setting the line to 0 will turn that line into
578 * an output.
579 * @flags: Different flags that will affect the behaviour of the device, such as
580 * endianness etc.
581 */
582int bgpio_init(struct gpio_chip *gc, struct device *dev,
583 unsigned long sz, void __iomem *dat, void __iomem *set,
584 void __iomem *clr, void __iomem *dirout, void __iomem *dirin,
585 unsigned long flags)
586{
587 int ret;
588
589 if (!is_power_of_2(sz))
590 return -EINVAL;
591
592 gc->bgpio_bits = sz * 8;
593 if (gc->bgpio_bits > BITS_PER_LONG)
594 return -EINVAL;
595
596 spin_lock_init(&gc->bgpio_lock);
597 gc->parent = dev;
598 gc->label = dev_name(dev);
599 gc->base = -1;
600 gc->ngpio = gc->bgpio_bits;
601 gc->request = bgpio_request;
602 gc->be_bits = !!(flags & BGPIOF_BIG_ENDIAN);
603
604 ret = bgpio_setup_io(gc, dat, set, clr, flags);
605 if (ret)
606 return ret;
607
608 ret = bgpio_setup_accessors(dev, gc, flags & BGPIOF_BIG_ENDIAN_BYTE_ORDER);
609 if (ret)
610 return ret;
611
612 ret = bgpio_setup_direction(gc, dirout, dirin, flags);
613 if (ret)
614 return ret;
615
616 gc->bgpio_data = gc->read_reg(gc->reg_dat);
617 if (gc->set == bgpio_set_set &&
618 !(flags & BGPIOF_UNREADABLE_REG_SET))
619 gc->bgpio_data = gc->read_reg(gc->reg_set);
620
621 if (flags & BGPIOF_UNREADABLE_REG_DIR)
622 gc->bgpio_dir_unreadable = true;
623
624 /*
625 * Inspect hardware to find initial direction setting.
626 */
627 if ((gc->reg_dir_out || gc->reg_dir_in) &&
628 !(flags & BGPIOF_UNREADABLE_REG_DIR)) {
629 if (gc->reg_dir_out)
630 gc->bgpio_dir = gc->read_reg(gc->reg_dir_out);
631 else if (gc->reg_dir_in)
632 gc->bgpio_dir = ~gc->read_reg(gc->reg_dir_in);
633 /*
634 * If we have two direction registers, synchronise
635 * input setting to output setting, the library
636 * can not handle a line being input and output at
637 * the same time.
638 */
639 if (gc->reg_dir_out && gc->reg_dir_in)
640 gc->write_reg(gc->reg_dir_in, ~gc->bgpio_dir);
641 }
642
643 return ret;
644}
645EXPORT_SYMBOL_GPL(bgpio_init);
646
647#if IS_ENABLED(CONFIG_GPIO_GENERIC_PLATFORM)
648
649static void __iomem *bgpio_map(struct platform_device *pdev,
650 const char *name,
651 resource_size_t sane_sz)
652{
653 struct resource *r;
654 resource_size_t sz;
655
656 r = platform_get_resource_byname(pdev, IORESOURCE_MEM, name);
657 if (!r)
658 return NULL;
659
660 sz = resource_size(r);
661 if (sz != sane_sz)
662 return IOMEM_ERR_PTR(-EINVAL);
663
664 return devm_ioremap_resource(&pdev->dev, r);
665}
666
667#ifdef CONFIG_OF
668static const struct of_device_id bgpio_of_match[] = {
669 { .compatible = "brcm,bcm6345-gpio" },
670 { .compatible = "wd,mbl-gpio" },
671 { .compatible = "ni,169445-nand-gpio" },
672 { }
673};
674MODULE_DEVICE_TABLE(of, bgpio_of_match);
675
676static struct bgpio_pdata *bgpio_parse_dt(struct platform_device *pdev,
677 unsigned long *flags)
678{
679 struct bgpio_pdata *pdata;
680
681 if (!of_match_device(bgpio_of_match, &pdev->dev))
682 return NULL;
683
684 pdata = devm_kzalloc(&pdev->dev, sizeof(struct bgpio_pdata),
685 GFP_KERNEL);
686 if (!pdata)
687 return ERR_PTR(-ENOMEM);
688
689 pdata->base = -1;
690
691 if (of_device_is_big_endian(pdev->dev.of_node))
692 *flags |= BGPIOF_BIG_ENDIAN_BYTE_ORDER;
693
694 if (of_property_read_bool(pdev->dev.of_node, "no-output"))
695 *flags |= BGPIOF_NO_OUTPUT;
696
697 return pdata;
698}
699#else
700static struct bgpio_pdata *bgpio_parse_dt(struct platform_device *pdev,
701 unsigned long *flags)
702{
703 return NULL;
704}
705#endif /* CONFIG_OF */
706
707static int bgpio_pdev_probe(struct platform_device *pdev)
708{
709 struct device *dev = &pdev->dev;
710 struct resource *r;
711 void __iomem *dat;
712 void __iomem *set;
713 void __iomem *clr;
714 void __iomem *dirout;
715 void __iomem *dirin;
716 unsigned long sz;
717 unsigned long flags = 0;
718 int err;
719 struct gpio_chip *gc;
720 struct bgpio_pdata *pdata;
721
722 pdata = bgpio_parse_dt(pdev, &flags);
723 if (IS_ERR(pdata))
724 return PTR_ERR(pdata);
725
726 if (!pdata) {
727 pdata = dev_get_platdata(dev);
728 flags = pdev->id_entry->driver_data;
729 }
730
731 r = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dat");
732 if (!r)
733 return -EINVAL;
734
735 sz = resource_size(r);
736
737 dat = bgpio_map(pdev, "dat", sz);
738 if (IS_ERR(dat))
739 return PTR_ERR(dat);
740
741 set = bgpio_map(pdev, "set", sz);
742 if (IS_ERR(set))
743 return PTR_ERR(set);
744
745 clr = bgpio_map(pdev, "clr", sz);
746 if (IS_ERR(clr))
747 return PTR_ERR(clr);
748
749 dirout = bgpio_map(pdev, "dirout", sz);
750 if (IS_ERR(dirout))
751 return PTR_ERR(dirout);
752
753 dirin = bgpio_map(pdev, "dirin", sz);
754 if (IS_ERR(dirin))
755 return PTR_ERR(dirin);
756
757 gc = devm_kzalloc(&pdev->dev, sizeof(*gc), GFP_KERNEL);
758 if (!gc)
759 return -ENOMEM;
760
761 err = bgpio_init(gc, dev, sz, dat, set, clr, dirout, dirin, flags);
762 if (err)
763 return err;
764
765 if (pdata) {
766 if (pdata->label)
767 gc->label = pdata->label;
768 gc->base = pdata->base;
769 if (pdata->ngpio > 0)
770 gc->ngpio = pdata->ngpio;
771 }
772
773 platform_set_drvdata(pdev, gc);
774
775 return devm_gpiochip_add_data(&pdev->dev, gc, NULL);
776}
777
778static const struct platform_device_id bgpio_id_table[] = {
779 {
780 .name = "basic-mmio-gpio",
781 .driver_data = 0,
782 }, {
783 .name = "basic-mmio-gpio-be",
784 .driver_data = BGPIOF_BIG_ENDIAN,
785 },
786 { }
787};
788MODULE_DEVICE_TABLE(platform, bgpio_id_table);
789
790static struct platform_driver bgpio_driver = {
791 .driver = {
792 .name = "basic-mmio-gpio",
793 .of_match_table = of_match_ptr(bgpio_of_match),
794 },
795 .id_table = bgpio_id_table,
796 .probe = bgpio_pdev_probe,
797};
798
799module_platform_driver(bgpio_driver);
800
801#endif /* CONFIG_GPIO_GENERIC_PLATFORM */
802
803MODULE_DESCRIPTION("Driver for basic memory-mapped GPIO controllers");
804MODULE_AUTHOR("Anton Vorontsov <cbouatmailru@gmail.com>");
805MODULE_LICENSE("GPL");