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1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * drivers/ata/ahci_tegra.c
4 *
5 * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved.
6 *
7 * Author:
8 * Mikko Perttunen <mperttunen@nvidia.com>
9 */
10
11#include <linux/ahci_platform.h>
12#include <linux/errno.h>
13#include <linux/kernel.h>
14#include <linux/module.h>
15#include <linux/of_device.h>
16#include <linux/platform_device.h>
17#include <linux/regulator/consumer.h>
18#include <linux/reset.h>
19
20#include <soc/tegra/fuse.h>
21#include <soc/tegra/pmc.h>
22
23#include "ahci.h"
24
25#define DRV_NAME "tegra-ahci"
26
27#define SATA_CONFIGURATION_0 0x180
28#define SATA_CONFIGURATION_0_EN_FPCI BIT(0)
29#define SATA_CONFIGURATION_0_CLK_OVERRIDE BIT(31)
30
31#define SCFG_OFFSET 0x1000
32
33#define T_SATA0_CFG_1 0x04
34#define T_SATA0_CFG_1_IO_SPACE BIT(0)
35#define T_SATA0_CFG_1_MEMORY_SPACE BIT(1)
36#define T_SATA0_CFG_1_BUS_MASTER BIT(2)
37#define T_SATA0_CFG_1_SERR BIT(8)
38
39#define T_SATA0_CFG_9 0x24
40#define T_SATA0_CFG_9_BASE_ADDRESS 0x40020000
41
42#define SATA_FPCI_BAR5 0x94
43#define SATA_FPCI_BAR5_START_MASK (0xfffffff << 4)
44#define SATA_FPCI_BAR5_START (0x0040020 << 4)
45#define SATA_FPCI_BAR5_ACCESS_TYPE (0x1)
46
47#define SATA_INTR_MASK 0x188
48#define SATA_INTR_MASK_IP_INT_MASK BIT(16)
49
50#define T_SATA0_CFG_35 0x94
51#define T_SATA0_CFG_35_IDP_INDEX_MASK (0x7ff << 2)
52#define T_SATA0_CFG_35_IDP_INDEX (0x2a << 2)
53
54#define T_SATA0_AHCI_IDP1 0x98
55#define T_SATA0_AHCI_IDP1_DATA (0x400040)
56
57#define T_SATA0_CFG_PHY_1 0x12c
58#define T_SATA0_CFG_PHY_1_PADS_IDDQ_EN BIT(23)
59#define T_SATA0_CFG_PHY_1_PAD_PLL_IDDQ_EN BIT(22)
60
61#define T_SATA0_NVOOB 0x114
62#define T_SATA0_NVOOB_COMMA_CNT_MASK (0xff << 16)
63#define T_SATA0_NVOOB_COMMA_CNT (0x07 << 16)
64#define T_SATA0_NVOOB_SQUELCH_FILTER_MODE_MASK (0x3 << 24)
65#define T_SATA0_NVOOB_SQUELCH_FILTER_MODE (0x1 << 24)
66#define T_SATA0_NVOOB_SQUELCH_FILTER_LENGTH_MASK (0x3 << 26)
67#define T_SATA0_NVOOB_SQUELCH_FILTER_LENGTH (0x3 << 26)
68
69#define T_SATA_CFG_PHY_0 0x120
70#define T_SATA_CFG_PHY_0_USE_7BIT_ALIGN_DET_FOR_SPD BIT(11)
71#define T_SATA_CFG_PHY_0_MASK_SQUELCH BIT(24)
72
73#define T_SATA0_CFG2NVOOB_2 0x134
74#define T_SATA0_CFG2NVOOB_2_COMWAKE_IDLE_CNT_LOW_MASK (0x1ff << 18)
75#define T_SATA0_CFG2NVOOB_2_COMWAKE_IDLE_CNT_LOW (0xc << 18)
76
77#define T_SATA0_AHCI_HBA_CAP_BKDR 0x300
78#define T_SATA0_AHCI_HBA_CAP_BKDR_PARTIAL_ST_CAP BIT(13)
79#define T_SATA0_AHCI_HBA_CAP_BKDR_SLUMBER_ST_CAP BIT(14)
80#define T_SATA0_AHCI_HBA_CAP_BKDR_SALP BIT(26)
81#define T_SATA0_AHCI_HBA_CAP_BKDR_SUPP_PM BIT(17)
82#define T_SATA0_AHCI_HBA_CAP_BKDR_SNCQ BIT(30)
83
84#define T_SATA0_BKDOOR_CC 0x4a4
85#define T_SATA0_BKDOOR_CC_CLASS_CODE_MASK (0xffff << 16)
86#define T_SATA0_BKDOOR_CC_CLASS_CODE (0x0106 << 16)
87#define T_SATA0_BKDOOR_CC_PROG_IF_MASK (0xff << 8)
88#define T_SATA0_BKDOOR_CC_PROG_IF (0x01 << 8)
89
90#define T_SATA0_CFG_SATA 0x54c
91#define T_SATA0_CFG_SATA_BACKDOOR_PROG_IF_EN BIT(12)
92
93#define T_SATA0_CFG_MISC 0x550
94
95#define T_SATA0_INDEX 0x680
96
97#define T_SATA0_CHX_PHY_CTRL1_GEN1 0x690
98#define T_SATA0_CHX_PHY_CTRL1_GEN1_TX_AMP_MASK 0xff
99#define T_SATA0_CHX_PHY_CTRL1_GEN1_TX_AMP_SHIFT 0
100#define T_SATA0_CHX_PHY_CTRL1_GEN1_TX_PEAK_MASK (0xff << 8)
101#define T_SATA0_CHX_PHY_CTRL1_GEN1_TX_PEAK_SHIFT 8
102
103#define T_SATA0_CHX_PHY_CTRL1_GEN2 0x694
104#define T_SATA0_CHX_PHY_CTRL1_GEN2_TX_AMP_MASK 0xff
105#define T_SATA0_CHX_PHY_CTRL1_GEN2_TX_AMP_SHIFT 0
106#define T_SATA0_CHX_PHY_CTRL1_GEN2_TX_PEAK_MASK (0xff << 12)
107#define T_SATA0_CHX_PHY_CTRL1_GEN2_TX_PEAK_SHIFT 12
108
109#define T_SATA0_CHX_PHY_CTRL2 0x69c
110#define T_SATA0_CHX_PHY_CTRL2_CDR_CNTL_GEN1 0x23
111
112#define T_SATA0_CHX_PHY_CTRL11 0x6d0
113#define T_SATA0_CHX_PHY_CTRL11_GEN2_RX_EQ (0x2800 << 16)
114
115#define T_SATA0_CHX_PHY_CTRL17_0 0x6e8
116#define T_SATA0_CHX_PHY_CTRL17_0_RX_EQ_CTRL_L_GEN1 0x55010000
117#define T_SATA0_CHX_PHY_CTRL18_0 0x6ec
118#define T_SATA0_CHX_PHY_CTRL18_0_RX_EQ_CTRL_L_GEN2 0x55010000
119#define T_SATA0_CHX_PHY_CTRL20_0 0x6f4
120#define T_SATA0_CHX_PHY_CTRL20_0_RX_EQ_CTRL_H_GEN1 0x1
121#define T_SATA0_CHX_PHY_CTRL21_0 0x6f8
122#define T_SATA0_CHX_PHY_CTRL21_0_RX_EQ_CTRL_H_GEN2 0x1
123
124/* AUX Registers */
125#define SATA_AUX_MISC_CNTL_1_0 0x8
126#define SATA_AUX_MISC_CNTL_1_0_DEVSLP_OVERRIDE BIT(17)
127#define SATA_AUX_MISC_CNTL_1_0_SDS_SUPPORT BIT(13)
128#define SATA_AUX_MISC_CNTL_1_0_DESO_SUPPORT BIT(15)
129
130#define SATA_AUX_RX_STAT_INT_0 0xc
131#define SATA_AUX_RX_STAT_INT_0_SATA_DEVSLP BIT(7)
132
133#define SATA_AUX_SPARE_CFG0_0 0x18
134#define SATA_AUX_SPARE_CFG0_0_MDAT_TIMER_AFTER_PG_VALID BIT(14)
135
136#define FUSE_SATA_CALIB 0x124
137#define FUSE_SATA_CALIB_MASK 0x3
138
139struct sata_pad_calibration {
140 u8 gen1_tx_amp;
141 u8 gen1_tx_peak;
142 u8 gen2_tx_amp;
143 u8 gen2_tx_peak;
144};
145
146static const struct sata_pad_calibration tegra124_pad_calibration[] = {
147 {0x18, 0x04, 0x18, 0x0a},
148 {0x0e, 0x04, 0x14, 0x0a},
149 {0x0e, 0x07, 0x1a, 0x0e},
150 {0x14, 0x0e, 0x1a, 0x0e},
151};
152
153struct tegra_ahci_ops {
154 int (*init)(struct ahci_host_priv *hpriv);
155};
156
157struct tegra_ahci_soc {
158 const char *const *supply_names;
159 u32 num_supplies;
160 bool supports_devslp;
161 const struct tegra_ahci_ops *ops;
162};
163
164struct tegra_ahci_priv {
165 struct platform_device *pdev;
166 void __iomem *sata_regs;
167 void __iomem *sata_aux_regs;
168 struct reset_control *sata_rst;
169 struct reset_control *sata_oob_rst;
170 struct reset_control *sata_cold_rst;
171 /* Needs special handling, cannot use ahci_platform */
172 struct clk *sata_clk;
173 struct regulator_bulk_data *supplies;
174 const struct tegra_ahci_soc *soc;
175};
176
177static void tegra_ahci_handle_quirks(struct ahci_host_priv *hpriv)
178{
179 struct tegra_ahci_priv *tegra = hpriv->plat_data;
180 u32 val;
181
182 if (tegra->sata_aux_regs && !tegra->soc->supports_devslp) {
183 val = readl(tegra->sata_aux_regs + SATA_AUX_MISC_CNTL_1_0);
184 val &= ~SATA_AUX_MISC_CNTL_1_0_SDS_SUPPORT;
185 writel(val, tegra->sata_aux_regs + SATA_AUX_MISC_CNTL_1_0);
186 }
187}
188
189static int tegra124_ahci_init(struct ahci_host_priv *hpriv)
190{
191 struct tegra_ahci_priv *tegra = hpriv->plat_data;
192 struct sata_pad_calibration calib;
193 int ret;
194 u32 val;
195
196 /* Pad calibration */
197 ret = tegra_fuse_readl(FUSE_SATA_CALIB, &val);
198 if (ret)
199 return ret;
200
201 calib = tegra124_pad_calibration[val & FUSE_SATA_CALIB_MASK];
202
203 writel(BIT(0), tegra->sata_regs + SCFG_OFFSET + T_SATA0_INDEX);
204
205 val = readl(tegra->sata_regs +
206 SCFG_OFFSET + T_SATA0_CHX_PHY_CTRL1_GEN1);
207 val &= ~T_SATA0_CHX_PHY_CTRL1_GEN1_TX_AMP_MASK;
208 val &= ~T_SATA0_CHX_PHY_CTRL1_GEN1_TX_PEAK_MASK;
209 val |= calib.gen1_tx_amp << T_SATA0_CHX_PHY_CTRL1_GEN1_TX_AMP_SHIFT;
210 val |= calib.gen1_tx_peak << T_SATA0_CHX_PHY_CTRL1_GEN1_TX_PEAK_SHIFT;
211 writel(val, tegra->sata_regs + SCFG_OFFSET +
212 T_SATA0_CHX_PHY_CTRL1_GEN1);
213
214 val = readl(tegra->sata_regs +
215 SCFG_OFFSET + T_SATA0_CHX_PHY_CTRL1_GEN2);
216 val &= ~T_SATA0_CHX_PHY_CTRL1_GEN2_TX_AMP_MASK;
217 val &= ~T_SATA0_CHX_PHY_CTRL1_GEN2_TX_PEAK_MASK;
218 val |= calib.gen2_tx_amp << T_SATA0_CHX_PHY_CTRL1_GEN1_TX_AMP_SHIFT;
219 val |= calib.gen2_tx_peak << T_SATA0_CHX_PHY_CTRL1_GEN1_TX_PEAK_SHIFT;
220 writel(val, tegra->sata_regs + SCFG_OFFSET +
221 T_SATA0_CHX_PHY_CTRL1_GEN2);
222
223 writel(T_SATA0_CHX_PHY_CTRL11_GEN2_RX_EQ,
224 tegra->sata_regs + SCFG_OFFSET + T_SATA0_CHX_PHY_CTRL11);
225 writel(T_SATA0_CHX_PHY_CTRL2_CDR_CNTL_GEN1,
226 tegra->sata_regs + SCFG_OFFSET + T_SATA0_CHX_PHY_CTRL2);
227
228 writel(0, tegra->sata_regs + SCFG_OFFSET + T_SATA0_INDEX);
229
230 return 0;
231}
232
233static int tegra_ahci_power_on(struct ahci_host_priv *hpriv)
234{
235 struct tegra_ahci_priv *tegra = hpriv->plat_data;
236 int ret;
237
238 ret = regulator_bulk_enable(tegra->soc->num_supplies,
239 tegra->supplies);
240 if (ret)
241 return ret;
242
243 ret = tegra_powergate_sequence_power_up(TEGRA_POWERGATE_SATA,
244 tegra->sata_clk,
245 tegra->sata_rst);
246 if (ret)
247 goto disable_regulators;
248
249 reset_control_assert(tegra->sata_oob_rst);
250 reset_control_assert(tegra->sata_cold_rst);
251
252 ret = ahci_platform_enable_resources(hpriv);
253 if (ret)
254 goto disable_power;
255
256 reset_control_deassert(tegra->sata_cold_rst);
257 reset_control_deassert(tegra->sata_oob_rst);
258
259 return 0;
260
261disable_power:
262 clk_disable_unprepare(tegra->sata_clk);
263
264 tegra_powergate_power_off(TEGRA_POWERGATE_SATA);
265
266disable_regulators:
267 regulator_bulk_disable(tegra->soc->num_supplies, tegra->supplies);
268
269 return ret;
270}
271
272static void tegra_ahci_power_off(struct ahci_host_priv *hpriv)
273{
274 struct tegra_ahci_priv *tegra = hpriv->plat_data;
275
276 ahci_platform_disable_resources(hpriv);
277
278 reset_control_assert(tegra->sata_rst);
279 reset_control_assert(tegra->sata_oob_rst);
280 reset_control_assert(tegra->sata_cold_rst);
281
282 clk_disable_unprepare(tegra->sata_clk);
283 tegra_powergate_power_off(TEGRA_POWERGATE_SATA);
284
285 regulator_bulk_disable(tegra->soc->num_supplies, tegra->supplies);
286}
287
288static int tegra_ahci_controller_init(struct ahci_host_priv *hpriv)
289{
290 struct tegra_ahci_priv *tegra = hpriv->plat_data;
291 int ret;
292 u32 val;
293
294 ret = tegra_ahci_power_on(hpriv);
295 if (ret) {
296 dev_err(&tegra->pdev->dev,
297 "failed to power on AHCI controller: %d\n", ret);
298 return ret;
299 }
300
301 /*
302 * Program the following SATA IPFS registers to allow SW accesses to
303 * SATA's MMIO register range.
304 */
305 val = readl(tegra->sata_regs + SATA_FPCI_BAR5);
306 val &= ~(SATA_FPCI_BAR5_START_MASK | SATA_FPCI_BAR5_ACCESS_TYPE);
307 val |= SATA_FPCI_BAR5_START | SATA_FPCI_BAR5_ACCESS_TYPE;
308 writel(val, tegra->sata_regs + SATA_FPCI_BAR5);
309
310 /* Program the following SATA IPFS register to enable the SATA */
311 val = readl(tegra->sata_regs + SATA_CONFIGURATION_0);
312 val |= SATA_CONFIGURATION_0_EN_FPCI;
313 writel(val, tegra->sata_regs + SATA_CONFIGURATION_0);
314
315 /* Electrical settings for better link stability */
316 val = T_SATA0_CHX_PHY_CTRL17_0_RX_EQ_CTRL_L_GEN1;
317 writel(val, tegra->sata_regs + SCFG_OFFSET + T_SATA0_CHX_PHY_CTRL17_0);
318 val = T_SATA0_CHX_PHY_CTRL18_0_RX_EQ_CTRL_L_GEN2;
319 writel(val, tegra->sata_regs + SCFG_OFFSET + T_SATA0_CHX_PHY_CTRL18_0);
320 val = T_SATA0_CHX_PHY_CTRL20_0_RX_EQ_CTRL_H_GEN1;
321 writel(val, tegra->sata_regs + SCFG_OFFSET + T_SATA0_CHX_PHY_CTRL20_0);
322 val = T_SATA0_CHX_PHY_CTRL21_0_RX_EQ_CTRL_H_GEN2;
323 writel(val, tegra->sata_regs + SCFG_OFFSET + T_SATA0_CHX_PHY_CTRL21_0);
324
325 /* For SQUELCH Filter & Gen3 drive getting detected as Gen1 drive */
326
327 val = readl(tegra->sata_regs + SCFG_OFFSET + T_SATA_CFG_PHY_0);
328 val |= T_SATA_CFG_PHY_0_MASK_SQUELCH;
329 val &= ~T_SATA_CFG_PHY_0_USE_7BIT_ALIGN_DET_FOR_SPD;
330 writel(val, tegra->sata_regs + SCFG_OFFSET + T_SATA_CFG_PHY_0);
331
332 val = readl(tegra->sata_regs + SCFG_OFFSET + T_SATA0_NVOOB);
333 val &= ~(T_SATA0_NVOOB_COMMA_CNT_MASK |
334 T_SATA0_NVOOB_SQUELCH_FILTER_LENGTH_MASK |
335 T_SATA0_NVOOB_SQUELCH_FILTER_MODE_MASK);
336 val |= (T_SATA0_NVOOB_COMMA_CNT |
337 T_SATA0_NVOOB_SQUELCH_FILTER_LENGTH |
338 T_SATA0_NVOOB_SQUELCH_FILTER_MODE);
339 writel(val, tegra->sata_regs + SCFG_OFFSET + T_SATA0_NVOOB);
340
341 /*
342 * Change CFG2NVOOB_2_COMWAKE_IDLE_CNT_LOW from 83.3 ns to 58.8ns
343 */
344 val = readl(tegra->sata_regs + SCFG_OFFSET + T_SATA0_CFG2NVOOB_2);
345 val &= ~T_SATA0_CFG2NVOOB_2_COMWAKE_IDLE_CNT_LOW_MASK;
346 val |= T_SATA0_CFG2NVOOB_2_COMWAKE_IDLE_CNT_LOW;
347 writel(val, tegra->sata_regs + SCFG_OFFSET + T_SATA0_CFG2NVOOB_2);
348
349 if (tegra->soc->ops && tegra->soc->ops->init)
350 tegra->soc->ops->init(hpriv);
351
352 /*
353 * Program the following SATA configuration registers to
354 * initialize SATA
355 */
356 val = readl(tegra->sata_regs + SCFG_OFFSET + T_SATA0_CFG_1);
357 val |= (T_SATA0_CFG_1_IO_SPACE | T_SATA0_CFG_1_MEMORY_SPACE |
358 T_SATA0_CFG_1_BUS_MASTER | T_SATA0_CFG_1_SERR);
359 writel(val, tegra->sata_regs + SCFG_OFFSET + T_SATA0_CFG_1);
360 val = T_SATA0_CFG_9_BASE_ADDRESS;
361 writel(val, tegra->sata_regs + SCFG_OFFSET + T_SATA0_CFG_9);
362
363 /* Program Class Code and Programming interface for SATA */
364 val = readl(tegra->sata_regs + SCFG_OFFSET + T_SATA0_CFG_SATA);
365 val |= T_SATA0_CFG_SATA_BACKDOOR_PROG_IF_EN;
366 writel(val, tegra->sata_regs + SCFG_OFFSET + T_SATA0_CFG_SATA);
367
368 val = readl(tegra->sata_regs + SCFG_OFFSET + T_SATA0_BKDOOR_CC);
369 val &=
370 ~(T_SATA0_BKDOOR_CC_CLASS_CODE_MASK |
371 T_SATA0_BKDOOR_CC_PROG_IF_MASK);
372 val |= T_SATA0_BKDOOR_CC_CLASS_CODE | T_SATA0_BKDOOR_CC_PROG_IF;
373 writel(val, tegra->sata_regs + SCFG_OFFSET + T_SATA0_BKDOOR_CC);
374
375 val = readl(tegra->sata_regs + SCFG_OFFSET + T_SATA0_CFG_SATA);
376 val &= ~T_SATA0_CFG_SATA_BACKDOOR_PROG_IF_EN;
377 writel(val, tegra->sata_regs + SCFG_OFFSET + T_SATA0_CFG_SATA);
378
379 /* Enabling LPM capabilities through Backdoor Programming */
380 val = readl(tegra->sata_regs + SCFG_OFFSET + T_SATA0_AHCI_HBA_CAP_BKDR);
381 val |= (T_SATA0_AHCI_HBA_CAP_BKDR_PARTIAL_ST_CAP |
382 T_SATA0_AHCI_HBA_CAP_BKDR_SLUMBER_ST_CAP |
383 T_SATA0_AHCI_HBA_CAP_BKDR_SALP |
384 T_SATA0_AHCI_HBA_CAP_BKDR_SUPP_PM);
385 writel(val, tegra->sata_regs + SCFG_OFFSET + T_SATA0_AHCI_HBA_CAP_BKDR);
386
387 /* SATA Second Level Clock Gating configuration
388 * Enabling Gating of Tx/Rx clocks and driving Pad IDDQ and Lane
389 * IDDQ Signals
390 */
391 val = readl(tegra->sata_regs + SCFG_OFFSET + T_SATA0_CFG_35);
392 val &= ~T_SATA0_CFG_35_IDP_INDEX_MASK;
393 val |= T_SATA0_CFG_35_IDP_INDEX;
394 writel(val, tegra->sata_regs + SCFG_OFFSET + T_SATA0_CFG_35);
395
396 val = T_SATA0_AHCI_IDP1_DATA;
397 writel(val, tegra->sata_regs + SCFG_OFFSET + T_SATA0_AHCI_IDP1);
398
399 val = readl(tegra->sata_regs + SCFG_OFFSET + T_SATA0_CFG_PHY_1);
400 val |= (T_SATA0_CFG_PHY_1_PADS_IDDQ_EN |
401 T_SATA0_CFG_PHY_1_PAD_PLL_IDDQ_EN);
402 writel(val, tegra->sata_regs + SCFG_OFFSET + T_SATA0_CFG_PHY_1);
403
404 /* Enabling IPFS Clock Gating */
405 val = readl(tegra->sata_regs + SATA_CONFIGURATION_0);
406 val &= ~SATA_CONFIGURATION_0_CLK_OVERRIDE;
407 writel(val, tegra->sata_regs + SATA_CONFIGURATION_0);
408
409 tegra_ahci_handle_quirks(hpriv);
410
411 /* Unmask SATA interrupts */
412
413 val = readl(tegra->sata_regs + SATA_INTR_MASK);
414 val |= SATA_INTR_MASK_IP_INT_MASK;
415 writel(val, tegra->sata_regs + SATA_INTR_MASK);
416
417 return 0;
418}
419
420static void tegra_ahci_controller_deinit(struct ahci_host_priv *hpriv)
421{
422 tegra_ahci_power_off(hpriv);
423}
424
425static void tegra_ahci_host_stop(struct ata_host *host)
426{
427 struct ahci_host_priv *hpriv = host->private_data;
428
429 tegra_ahci_controller_deinit(hpriv);
430}
431
432static struct ata_port_operations ahci_tegra_port_ops = {
433 .inherits = &ahci_ops,
434 .host_stop = tegra_ahci_host_stop,
435};
436
437static const struct ata_port_info ahci_tegra_port_info = {
438 .flags = AHCI_FLAG_COMMON | ATA_FLAG_NO_DIPM,
439 .pio_mask = ATA_PIO4,
440 .udma_mask = ATA_UDMA6,
441 .port_ops = &ahci_tegra_port_ops,
442};
443
444static const char *const tegra124_supply_names[] = {
445 "avdd", "hvdd", "vddio", "target-5v", "target-12v"
446};
447
448static const struct tegra_ahci_ops tegra124_ahci_ops = {
449 .init = tegra124_ahci_init,
450};
451
452static const struct tegra_ahci_soc tegra124_ahci_soc = {
453 .supply_names = tegra124_supply_names,
454 .num_supplies = ARRAY_SIZE(tegra124_supply_names),
455 .supports_devslp = false,
456 .ops = &tegra124_ahci_ops,
457};
458
459static const struct tegra_ahci_soc tegra210_ahci_soc = {
460 .supports_devslp = false,
461};
462
463static const struct of_device_id tegra_ahci_of_match[] = {
464 {
465 .compatible = "nvidia,tegra124-ahci",
466 .data = &tegra124_ahci_soc
467 },
468 {
469 .compatible = "nvidia,tegra210-ahci",
470 .data = &tegra210_ahci_soc
471 },
472 {}
473};
474MODULE_DEVICE_TABLE(of, tegra_ahci_of_match);
475
476static struct scsi_host_template ahci_platform_sht = {
477 AHCI_SHT(DRV_NAME),
478};
479
480static int tegra_ahci_probe(struct platform_device *pdev)
481{
482 struct ahci_host_priv *hpriv;
483 struct tegra_ahci_priv *tegra;
484 struct resource *res;
485 int ret;
486 unsigned int i;
487
488 hpriv = ahci_platform_get_resources(pdev, 0);
489 if (IS_ERR(hpriv))
490 return PTR_ERR(hpriv);
491
492 tegra = devm_kzalloc(&pdev->dev, sizeof(*tegra), GFP_KERNEL);
493 if (!tegra)
494 return -ENOMEM;
495
496 hpriv->plat_data = tegra;
497
498 tegra->pdev = pdev;
499 tegra->soc = of_device_get_match_data(&pdev->dev);
500
501 res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
502 tegra->sata_regs = devm_ioremap_resource(&pdev->dev, res);
503 if (IS_ERR(tegra->sata_regs))
504 return PTR_ERR(tegra->sata_regs);
505
506 /*
507 * AUX registers is optional.
508 */
509 res = platform_get_resource(pdev, IORESOURCE_MEM, 2);
510 if (res) {
511 tegra->sata_aux_regs = devm_ioremap_resource(&pdev->dev, res);
512 if (IS_ERR(tegra->sata_aux_regs))
513 return PTR_ERR(tegra->sata_aux_regs);
514 }
515
516 tegra->sata_rst = devm_reset_control_get(&pdev->dev, "sata");
517 if (IS_ERR(tegra->sata_rst)) {
518 dev_err(&pdev->dev, "Failed to get sata reset\n");
519 return PTR_ERR(tegra->sata_rst);
520 }
521
522 tegra->sata_oob_rst = devm_reset_control_get(&pdev->dev, "sata-oob");
523 if (IS_ERR(tegra->sata_oob_rst)) {
524 dev_err(&pdev->dev, "Failed to get sata-oob reset\n");
525 return PTR_ERR(tegra->sata_oob_rst);
526 }
527
528 tegra->sata_cold_rst = devm_reset_control_get(&pdev->dev, "sata-cold");
529 if (IS_ERR(tegra->sata_cold_rst)) {
530 dev_err(&pdev->dev, "Failed to get sata-cold reset\n");
531 return PTR_ERR(tegra->sata_cold_rst);
532 }
533
534 tegra->sata_clk = devm_clk_get(&pdev->dev, "sata");
535 if (IS_ERR(tegra->sata_clk)) {
536 dev_err(&pdev->dev, "Failed to get sata clock\n");
537 return PTR_ERR(tegra->sata_clk);
538 }
539
540 tegra->supplies = devm_kcalloc(&pdev->dev,
541 tegra->soc->num_supplies,
542 sizeof(*tegra->supplies), GFP_KERNEL);
543 if (!tegra->supplies)
544 return -ENOMEM;
545
546 for (i = 0; i < tegra->soc->num_supplies; i++)
547 tegra->supplies[i].supply = tegra->soc->supply_names[i];
548
549 ret = devm_regulator_bulk_get(&pdev->dev,
550 tegra->soc->num_supplies,
551 tegra->supplies);
552 if (ret) {
553 dev_err(&pdev->dev, "Failed to get regulators\n");
554 return ret;
555 }
556
557 ret = tegra_ahci_controller_init(hpriv);
558 if (ret)
559 return ret;
560
561 ret = ahci_platform_init_host(pdev, hpriv, &ahci_tegra_port_info,
562 &ahci_platform_sht);
563 if (ret)
564 goto deinit_controller;
565
566 return 0;
567
568deinit_controller:
569 tegra_ahci_controller_deinit(hpriv);
570
571 return ret;
572};
573
574static struct platform_driver tegra_ahci_driver = {
575 .probe = tegra_ahci_probe,
576 .remove = ata_platform_remove_one,
577 .driver = {
578 .name = DRV_NAME,
579 .of_match_table = tegra_ahci_of_match,
580 },
581 /* LP0 suspend support not implemented */
582};
583module_platform_driver(tegra_ahci_driver);
584
585MODULE_AUTHOR("Mikko Perttunen <mperttunen@nvidia.com>");
586MODULE_DESCRIPTION("Tegra AHCI SATA driver");
587MODULE_LICENSE("GPL v2");