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1/*
2 * swift.S: MicroSparc-II mmu/cache operations.
3 *
4 * Copyright (C) 1999 David S. Miller (davem@redhat.com)
5 */
6
7#include <asm/psr.h>
8#include <asm/asi.h>
9#include <asm/page.h>
10#include <asm/pgtsrmmu.h>
11#include <asm/asm-offsets.h>
12
13 .text
14 .align 4
15
16#if 1 /* XXX screw this, I can't get the VAC flushes working
17 * XXX reliably... -DaveM
18 */
19 .globl swift_flush_cache_all, swift_flush_cache_mm
20 .globl swift_flush_cache_range, swift_flush_cache_page
21 .globl swift_flush_page_for_dma
22 .globl swift_flush_page_to_ram
23
24swift_flush_cache_all:
25swift_flush_cache_mm:
26swift_flush_cache_range:
27swift_flush_cache_page:
28swift_flush_page_for_dma:
29swift_flush_page_to_ram:
30 sethi %hi(0x2000), %o0
311: subcc %o0, 0x10, %o0
32 add %o0, %o0, %o1
33 sta %g0, [%o0] ASI_M_DATAC_TAG
34 bne 1b
35 sta %g0, [%o1] ASI_M_TXTC_TAG
36 retl
37 nop
38#else
39
40 .globl swift_flush_cache_all
41swift_flush_cache_all:
42 WINDOW_FLUSH(%g4, %g5)
43
44 /* Just clear out all the tags. */
45 sethi %hi(16 * 1024), %o0
461: subcc %o0, 16, %o0
47 sta %g0, [%o0] ASI_M_TXTC_TAG
48 bne 1b
49 sta %g0, [%o0] ASI_M_DATAC_TAG
50 retl
51 nop
52
53 .globl swift_flush_cache_mm
54swift_flush_cache_mm:
55 ld [%o0 + AOFF_mm_context], %g2
56 cmp %g2, -1
57 be swift_flush_cache_mm_out
58 WINDOW_FLUSH(%g4, %g5)
59 rd %psr, %g1
60 andn %g1, PSR_ET, %g3
61 wr %g3, 0x0, %psr
62 nop
63 nop
64 mov SRMMU_CTX_REG, %g7
65 lda [%g7] ASI_M_MMUREGS, %g5
66 sta %g2, [%g7] ASI_M_MMUREGS
67
68#if 1
69 sethi %hi(0x2000), %o0
701: subcc %o0, 0x10, %o0
71 sta %g0, [%o0] ASI_M_FLUSH_CTX
72 bne 1b
73 nop
74#else
75 clr %o0
76 or %g0, 2048, %g7
77 or %g0, 2048, %o1
78 add %o1, 2048, %o2
79 add %o2, 2048, %o3
80 mov 16, %o4
81 add %o4, 2048, %o5
82 add %o5, 2048, %g2
83 add %g2, 2048, %g3
841: sta %g0, [%o0 ] ASI_M_FLUSH_CTX
85 sta %g0, [%o0 + %o1] ASI_M_FLUSH_CTX
86 sta %g0, [%o0 + %o2] ASI_M_FLUSH_CTX
87 sta %g0, [%o0 + %o3] ASI_M_FLUSH_CTX
88 sta %g0, [%o0 + %o4] ASI_M_FLUSH_CTX
89 sta %g0, [%o0 + %o5] ASI_M_FLUSH_CTX
90 sta %g0, [%o0 + %g2] ASI_M_FLUSH_CTX
91 sta %g0, [%o0 + %g3] ASI_M_FLUSH_CTX
92 subcc %g7, 32, %g7
93 bne 1b
94 add %o0, 32, %o0
95#endif
96
97 mov SRMMU_CTX_REG, %g7
98 sta %g5, [%g7] ASI_M_MMUREGS
99 wr %g1, 0x0, %psr
100 nop
101 nop
102swift_flush_cache_mm_out:
103 retl
104 nop
105
106 .globl swift_flush_cache_range
107swift_flush_cache_range:
108 ld [%o0 + 0x0], %o0 /* XXX vma->vm_mm, GROSS XXX */
109 sub %o2, %o1, %o2
110 sethi %hi(4096), %o3
111 cmp %o2, %o3
112 bgu swift_flush_cache_mm
113 nop
114 b 70f
115 nop
116
117 .globl swift_flush_cache_page
118swift_flush_cache_page:
119 ld [%o0 + 0x0], %o0 /* XXX vma->vm_mm, GROSS XXX */
12070:
121 ld [%o0 + AOFF_mm_context], %g2
122 cmp %g2, -1
123 be swift_flush_cache_page_out
124 WINDOW_FLUSH(%g4, %g5)
125 rd %psr, %g1
126 andn %g1, PSR_ET, %g3
127 wr %g3, 0x0, %psr
128 nop
129 nop
130 mov SRMMU_CTX_REG, %g7
131 lda [%g7] ASI_M_MMUREGS, %g5
132 sta %g2, [%g7] ASI_M_MMUREGS
133
134 andn %o1, (PAGE_SIZE - 1), %o1
135#if 1
136 sethi %hi(0x1000), %o0
1371: subcc %o0, 0x10, %o0
138 sta %g0, [%o1 + %o0] ASI_M_FLUSH_PAGE
139 bne 1b
140 nop
141#else
142 or %g0, 512, %g7
143 or %g0, 512, %o0
144 add %o0, 512, %o2
145 add %o2, 512, %o3
146 add %o3, 512, %o4
147 add %o4, 512, %o5
148 add %o5, 512, %g3
149 add %g3, 512, %g4
1501: sta %g0, [%o1 ] ASI_M_FLUSH_PAGE
151 sta %g0, [%o1 + %o0] ASI_M_FLUSH_PAGE
152 sta %g0, [%o1 + %o2] ASI_M_FLUSH_PAGE
153 sta %g0, [%o1 + %o3] ASI_M_FLUSH_PAGE
154 sta %g0, [%o1 + %o4] ASI_M_FLUSH_PAGE
155 sta %g0, [%o1 + %o5] ASI_M_FLUSH_PAGE
156 sta %g0, [%o1 + %g3] ASI_M_FLUSH_PAGE
157 sta %g0, [%o1 + %g4] ASI_M_FLUSH_PAGE
158 subcc %g7, 16, %g7
159 bne 1b
160 add %o1, 16, %o1
161#endif
162
163 mov SRMMU_CTX_REG, %g7
164 sta %g5, [%g7] ASI_M_MMUREGS
165 wr %g1, 0x0, %psr
166 nop
167 nop
168swift_flush_cache_page_out:
169 retl
170 nop
171
172 /* Swift is write-thru, however it is not
173 * I/O nor TLB-walk coherent. Also it has
174 * caches which are virtually indexed and tagged.
175 */
176 .globl swift_flush_page_for_dma
177 .globl swift_flush_page_to_ram
178swift_flush_page_for_dma:
179swift_flush_page_to_ram:
180 andn %o0, (PAGE_SIZE - 1), %o1
181#if 1
182 sethi %hi(0x1000), %o0
1831: subcc %o0, 0x10, %o0
184 sta %g0, [%o1 + %o0] ASI_M_FLUSH_PAGE
185 bne 1b
186 nop
187#else
188 or %g0, 512, %g7
189 or %g0, 512, %o0
190 add %o0, 512, %o2
191 add %o2, 512, %o3
192 add %o3, 512, %o4
193 add %o4, 512, %o5
194 add %o5, 512, %g3
195 add %g3, 512, %g4
1961: sta %g0, [%o1 ] ASI_M_FLUSH_PAGE
197 sta %g0, [%o1 + %o0] ASI_M_FLUSH_PAGE
198 sta %g0, [%o1 + %o2] ASI_M_FLUSH_PAGE
199 sta %g0, [%o1 + %o3] ASI_M_FLUSH_PAGE
200 sta %g0, [%o1 + %o4] ASI_M_FLUSH_PAGE
201 sta %g0, [%o1 + %o5] ASI_M_FLUSH_PAGE
202 sta %g0, [%o1 + %g3] ASI_M_FLUSH_PAGE
203 sta %g0, [%o1 + %g4] ASI_M_FLUSH_PAGE
204 subcc %g7, 16, %g7
205 bne 1b
206 add %o1, 16, %o1
207#endif
208 retl
209 nop
210#endif
211
212 .globl swift_flush_sig_insns
213swift_flush_sig_insns:
214 flush %o1
215 retl
216 flush %o1 + 4
217
218 .globl swift_flush_tlb_mm
219 .globl swift_flush_tlb_range
220 .globl swift_flush_tlb_all
221swift_flush_tlb_range:
222 ld [%o0 + 0x00], %o0 /* XXX vma->vm_mm GROSS XXX */
223swift_flush_tlb_mm:
224 ld [%o0 + AOFF_mm_context], %g2
225 cmp %g2, -1
226 be swift_flush_tlb_all_out
227swift_flush_tlb_all:
228 mov 0x400, %o1
229 sta %g0, [%o1] ASI_M_FLUSH_PROBE
230swift_flush_tlb_all_out:
231 retl
232 nop
233
234 .globl swift_flush_tlb_page
235swift_flush_tlb_page:
236 ld [%o0 + 0x00], %o0 /* XXX vma->vm_mm GROSS XXX */
237 mov SRMMU_CTX_REG, %g1
238 ld [%o0 + AOFF_mm_context], %o3
239 andn %o1, (PAGE_SIZE - 1), %o1
240 cmp %o3, -1
241 be swift_flush_tlb_page_out
242 nop
243#if 1
244 mov 0x400, %o1
245 sta %g0, [%o1] ASI_M_FLUSH_PROBE
246#else
247 lda [%g1] ASI_M_MMUREGS, %g5
248 sta %o3, [%g1] ASI_M_MMUREGS
249 sta %g0, [%o1] ASI_M_FLUSH_PAGE /* rem. virt. cache. prot. */
250 sta %g0, [%o1] ASI_M_FLUSH_PROBE
251 sta %g5, [%g1] ASI_M_MMUREGS
252#endif
253swift_flush_tlb_page_out:
254 retl
255 nop
1/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 * swift.S: MicroSparc-II mmu/cache operations.
4 *
5 * Copyright (C) 1999 David S. Miller (davem@redhat.com)
6 */
7
8#include <asm/psr.h>
9#include <asm/asi.h>
10#include <asm/page.h>
11#include <asm/pgtsrmmu.h>
12#include <asm/asm-offsets.h>
13
14 .text
15 .align 4
16
17#if 1 /* XXX screw this, I can't get the VAC flushes working
18 * XXX reliably... -DaveM
19 */
20 .globl swift_flush_cache_all, swift_flush_cache_mm
21 .globl swift_flush_cache_range, swift_flush_cache_page
22 .globl swift_flush_page_for_dma
23 .globl swift_flush_page_to_ram
24
25swift_flush_cache_all:
26swift_flush_cache_mm:
27swift_flush_cache_range:
28swift_flush_cache_page:
29swift_flush_page_for_dma:
30swift_flush_page_to_ram:
31 sethi %hi(0x2000), %o0
321: subcc %o0, 0x10, %o0
33 add %o0, %o0, %o1
34 sta %g0, [%o0] ASI_M_DATAC_TAG
35 bne 1b
36 sta %g0, [%o1] ASI_M_TXTC_TAG
37 retl
38 nop
39#else
40
41 .globl swift_flush_cache_all
42swift_flush_cache_all:
43 WINDOW_FLUSH(%g4, %g5)
44
45 /* Just clear out all the tags. */
46 sethi %hi(16 * 1024), %o0
471: subcc %o0, 16, %o0
48 sta %g0, [%o0] ASI_M_TXTC_TAG
49 bne 1b
50 sta %g0, [%o0] ASI_M_DATAC_TAG
51 retl
52 nop
53
54 .globl swift_flush_cache_mm
55swift_flush_cache_mm:
56 ld [%o0 + AOFF_mm_context], %g2
57 cmp %g2, -1
58 be swift_flush_cache_mm_out
59 WINDOW_FLUSH(%g4, %g5)
60 rd %psr, %g1
61 andn %g1, PSR_ET, %g3
62 wr %g3, 0x0, %psr
63 nop
64 nop
65 mov SRMMU_CTX_REG, %g7
66 lda [%g7] ASI_M_MMUREGS, %g5
67 sta %g2, [%g7] ASI_M_MMUREGS
68
69#if 1
70 sethi %hi(0x2000), %o0
711: subcc %o0, 0x10, %o0
72 sta %g0, [%o0] ASI_M_FLUSH_CTX
73 bne 1b
74 nop
75#else
76 clr %o0
77 or %g0, 2048, %g7
78 or %g0, 2048, %o1
79 add %o1, 2048, %o2
80 add %o2, 2048, %o3
81 mov 16, %o4
82 add %o4, 2048, %o5
83 add %o5, 2048, %g2
84 add %g2, 2048, %g3
851: sta %g0, [%o0 ] ASI_M_FLUSH_CTX
86 sta %g0, [%o0 + %o1] ASI_M_FLUSH_CTX
87 sta %g0, [%o0 + %o2] ASI_M_FLUSH_CTX
88 sta %g0, [%o0 + %o3] ASI_M_FLUSH_CTX
89 sta %g0, [%o0 + %o4] ASI_M_FLUSH_CTX
90 sta %g0, [%o0 + %o5] ASI_M_FLUSH_CTX
91 sta %g0, [%o0 + %g2] ASI_M_FLUSH_CTX
92 sta %g0, [%o0 + %g3] ASI_M_FLUSH_CTX
93 subcc %g7, 32, %g7
94 bne 1b
95 add %o0, 32, %o0
96#endif
97
98 mov SRMMU_CTX_REG, %g7
99 sta %g5, [%g7] ASI_M_MMUREGS
100 wr %g1, 0x0, %psr
101 nop
102 nop
103swift_flush_cache_mm_out:
104 retl
105 nop
106
107 .globl swift_flush_cache_range
108swift_flush_cache_range:
109 ld [%o0 + VMA_VM_MM], %o0
110 sub %o2, %o1, %o2
111 sethi %hi(4096), %o3
112 cmp %o2, %o3
113 bgu swift_flush_cache_mm
114 nop
115 b 70f
116 nop
117
118 .globl swift_flush_cache_page
119swift_flush_cache_page:
120 ld [%o0 + VMA_VM_MM], %o0
12170:
122 ld [%o0 + AOFF_mm_context], %g2
123 cmp %g2, -1
124 be swift_flush_cache_page_out
125 WINDOW_FLUSH(%g4, %g5)
126 rd %psr, %g1
127 andn %g1, PSR_ET, %g3
128 wr %g3, 0x0, %psr
129 nop
130 nop
131 mov SRMMU_CTX_REG, %g7
132 lda [%g7] ASI_M_MMUREGS, %g5
133 sta %g2, [%g7] ASI_M_MMUREGS
134
135 andn %o1, (PAGE_SIZE - 1), %o1
136#if 1
137 sethi %hi(0x1000), %o0
1381: subcc %o0, 0x10, %o0
139 sta %g0, [%o1 + %o0] ASI_M_FLUSH_PAGE
140 bne 1b
141 nop
142#else
143 or %g0, 512, %g7
144 or %g0, 512, %o0
145 add %o0, 512, %o2
146 add %o2, 512, %o3
147 add %o3, 512, %o4
148 add %o4, 512, %o5
149 add %o5, 512, %g3
150 add %g3, 512, %g4
1511: sta %g0, [%o1 ] ASI_M_FLUSH_PAGE
152 sta %g0, [%o1 + %o0] ASI_M_FLUSH_PAGE
153 sta %g0, [%o1 + %o2] ASI_M_FLUSH_PAGE
154 sta %g0, [%o1 + %o3] ASI_M_FLUSH_PAGE
155 sta %g0, [%o1 + %o4] ASI_M_FLUSH_PAGE
156 sta %g0, [%o1 + %o5] ASI_M_FLUSH_PAGE
157 sta %g0, [%o1 + %g3] ASI_M_FLUSH_PAGE
158 sta %g0, [%o1 + %g4] ASI_M_FLUSH_PAGE
159 subcc %g7, 16, %g7
160 bne 1b
161 add %o1, 16, %o1
162#endif
163
164 mov SRMMU_CTX_REG, %g7
165 sta %g5, [%g7] ASI_M_MMUREGS
166 wr %g1, 0x0, %psr
167 nop
168 nop
169swift_flush_cache_page_out:
170 retl
171 nop
172
173 /* Swift is write-thru, however it is not
174 * I/O nor TLB-walk coherent. Also it has
175 * caches which are virtually indexed and tagged.
176 */
177 .globl swift_flush_page_for_dma
178 .globl swift_flush_page_to_ram
179swift_flush_page_for_dma:
180swift_flush_page_to_ram:
181 andn %o0, (PAGE_SIZE - 1), %o1
182#if 1
183 sethi %hi(0x1000), %o0
1841: subcc %o0, 0x10, %o0
185 sta %g0, [%o1 + %o0] ASI_M_FLUSH_PAGE
186 bne 1b
187 nop
188#else
189 or %g0, 512, %g7
190 or %g0, 512, %o0
191 add %o0, 512, %o2
192 add %o2, 512, %o3
193 add %o3, 512, %o4
194 add %o4, 512, %o5
195 add %o5, 512, %g3
196 add %g3, 512, %g4
1971: sta %g0, [%o1 ] ASI_M_FLUSH_PAGE
198 sta %g0, [%o1 + %o0] ASI_M_FLUSH_PAGE
199 sta %g0, [%o1 + %o2] ASI_M_FLUSH_PAGE
200 sta %g0, [%o1 + %o3] ASI_M_FLUSH_PAGE
201 sta %g0, [%o1 + %o4] ASI_M_FLUSH_PAGE
202 sta %g0, [%o1 + %o5] ASI_M_FLUSH_PAGE
203 sta %g0, [%o1 + %g3] ASI_M_FLUSH_PAGE
204 sta %g0, [%o1 + %g4] ASI_M_FLUSH_PAGE
205 subcc %g7, 16, %g7
206 bne 1b
207 add %o1, 16, %o1
208#endif
209 retl
210 nop
211#endif
212
213 .globl swift_flush_sig_insns
214swift_flush_sig_insns:
215 flush %o1
216 retl
217 flush %o1 + 4
218
219 .globl swift_flush_tlb_mm
220 .globl swift_flush_tlb_range
221 .globl swift_flush_tlb_all
222swift_flush_tlb_range:
223 ld [%o0 + VMA_VM_MM], %o0
224swift_flush_tlb_mm:
225 ld [%o0 + AOFF_mm_context], %g2
226 cmp %g2, -1
227 be swift_flush_tlb_all_out
228swift_flush_tlb_all:
229 mov 0x400, %o1
230 sta %g0, [%o1] ASI_M_FLUSH_PROBE
231swift_flush_tlb_all_out:
232 retl
233 nop
234
235 .globl swift_flush_tlb_page
236swift_flush_tlb_page:
237 ld [%o0 + VMA_VM_MM], %o0
238 mov SRMMU_CTX_REG, %g1
239 ld [%o0 + AOFF_mm_context], %o3
240 andn %o1, (PAGE_SIZE - 1), %o1
241 cmp %o3, -1
242 be swift_flush_tlb_page_out
243 nop
244#if 1
245 mov 0x400, %o1
246 sta %g0, [%o1] ASI_M_FLUSH_PROBE
247#else
248 lda [%g1] ASI_M_MMUREGS, %g5
249 sta %o3, [%g1] ASI_M_MMUREGS
250 sta %g0, [%o1] ASI_M_FLUSH_PAGE /* rem. virt. cache. prot. */
251 sta %g0, [%o1] ASI_M_FLUSH_PROBE
252 sta %g5, [%g1] ASI_M_MMUREGS
253#endif
254swift_flush_tlb_page_out:
255 retl
256 nop