1/*
 2 * arch/sh/mm/tlb-sh3.c
 3 *
 4 * SH-3 specific TLB operations
 5 *
 6 * Copyright (C) 1999  Niibe Yutaka
 7 * Copyright (C) 2002  Paul Mundt
 8 *
 9 * Released under the terms of the GNU GPL v2.0.
10 */
11#include <linux/signal.h>
12#include <linux/sched.h>
13#include <linux/kernel.h>
14#include <linux/errno.h>
15#include <linux/string.h>
16#include <linux/types.h>
17#include <linux/ptrace.h>
18#include <linux/mman.h>
19#include <linux/mm.h>
20#include <linux/smp.h>
21#include <linux/interrupt.h>
22
23#include <asm/system.h>
24#include <asm/io.h>
25#include <asm/uaccess.h>
26#include <asm/pgalloc.h>
27#include <asm/mmu_context.h>
28#include <asm/cacheflush.h>
29
30void __update_tlb(struct vm_area_struct *vma, unsigned long address, pte_t pte)
31{
32	unsigned long flags, pteval, vpn;
33
34	/*
35	 * Handle debugger faulting in for debugee.
36	 */
37	if (vma && current->active_mm != vma->vm_mm)
38		return;
39
40	local_irq_save(flags);
41
42	/* Set PTEH register */
43	vpn = (address & MMU_VPN_MASK) | get_asid();
44	__raw_writel(vpn, MMU_PTEH);
45
46	pteval = pte_val(pte);
47
48	/* Set PTEL register */
49	pteval &= _PAGE_FLAGS_HARDWARE_MASK; /* drop software flags */
50	/* conveniently, we want all the software flags to be 0 anyway */
51	__raw_writel(pteval, MMU_PTEL);
52
53	/* Load the TLB */
54	asm volatile("ldtlb": /* no output */ : /* no input */ : "memory");
55	local_irq_restore(flags);
56}
57
58void local_flush_tlb_one(unsigned long asid, unsigned long page)
59{
60	unsigned long addr, data;
61	int i, ways = MMU_NTLB_WAYS;
62
63	/*
64	 * NOTE: PTEH.ASID should be set to this MM
65	 *       _AND_ we need to write ASID to the array.
66	 *
67	 * It would be simple if we didn't need to set PTEH.ASID...
68	 */
69	addr = MMU_TLB_ADDRESS_ARRAY | (page & 0x1F000);
70	data = (page & 0xfffe0000) | asid; /* VALID bit is off */
71
72	if ((current_cpu_data.flags & CPU_HAS_MMU_PAGE_ASSOC)) {
73		addr |= MMU_PAGE_ASSOC_BIT;
74		ways = 1;	/* we already know the way .. */
75	}
76
77	for (i = 0; i < ways; i++)
78		__raw_writel(data, addr + (i << 8));
79}
80
81void local_flush_tlb_all(void)
82{
83	unsigned long flags, status;
84
85	/*
86	 * Flush all the TLB.
87	 *
88	 * Write to the MMU control register's bit:
89	 *	TF-bit for SH-3, TI-bit for SH-4.
90	 *      It's same position, bit #2.
91	 */
92	local_irq_save(flags);
93	status = __raw_readl(MMUCR);
94	status |= 0x04;
95	__raw_writel(status, MMUCR);
96	ctrl_barrier();
97	local_irq_restore(flags);
98}

 1// SPDX-License-Identifier: GPL-2.0-only
 2/*
 3 * arch/sh/mm/tlb-sh3.c
 4 *
 5 * SH-3 specific TLB operations
 6 *
 7 * Copyright (C) 1999  Niibe Yutaka
 8 * Copyright (C) 2002  Paul Mundt
 
 
 9 */
10#include <linux/signal.h>
11#include <linux/sched.h>
12#include <linux/kernel.h>
13#include <linux/errno.h>
14#include <linux/string.h>
15#include <linux/types.h>
16#include <linux/ptrace.h>
17#include <linux/mman.h>
18#include <linux/mm.h>
19#include <linux/smp.h>
20#include <linux/interrupt.h>
21
 
22#include <asm/io.h>
23#include <linux/uaccess.h>
24#include <asm/pgalloc.h>
25#include <asm/mmu_context.h>
26#include <asm/cacheflush.h>
27
28void __update_tlb(struct vm_area_struct *vma, unsigned long address, pte_t pte)
29{
30	unsigned long flags, pteval, vpn;
31
32	/*
33	 * Handle debugger faulting in for debugee.
34	 */
35	if (vma && current->active_mm != vma->vm_mm)
36		return;
37
38	local_irq_save(flags);
39
40	/* Set PTEH register */
41	vpn = (address & MMU_VPN_MASK) | get_asid();
42	__raw_writel(vpn, MMU_PTEH);
43
44	pteval = pte_val(pte);
45
46	/* Set PTEL register */
47	pteval &= _PAGE_FLAGS_HARDWARE_MASK; /* drop software flags */
48	/* conveniently, we want all the software flags to be 0 anyway */
49	__raw_writel(pteval, MMU_PTEL);
50
51	/* Load the TLB */
52	asm volatile("ldtlb": /* no output */ : /* no input */ : "memory");
53	local_irq_restore(flags);
54}
55
56void local_flush_tlb_one(unsigned long asid, unsigned long page)
57{
58	unsigned long addr, data;
59	int i, ways = MMU_NTLB_WAYS;
60
61	/*
62	 * NOTE: PTEH.ASID should be set to this MM
63	 *       _AND_ we need to write ASID to the array.
64	 *
65	 * It would be simple if we didn't need to set PTEH.ASID...
66	 */
67	addr = MMU_TLB_ADDRESS_ARRAY | (page & 0x1F000);
68	data = (page & 0xfffe0000) | asid; /* VALID bit is off */
69
70	if ((current_cpu_data.flags & CPU_HAS_MMU_PAGE_ASSOC)) {
71		addr |= MMU_PAGE_ASSOC_BIT;
72		ways = 1;	/* we already know the way .. */
73	}
74
75	for (i = 0; i < ways; i++)
76		__raw_writel(data, addr + (i << 8));
77}
78
79void local_flush_tlb_all(void)
80{
81	unsigned long flags, status;
82
83	/*
84	 * Flush all the TLB.
85	 *
86	 * Write to the MMU control register's bit:
87	 *	TF-bit for SH-3, TI-bit for SH-4.
88	 *      It's same position, bit #2.
89	 */
90	local_irq_save(flags);
91	status = __raw_readl(MMUCR);
92	status |= 0x04;
93	__raw_writel(status, MMUCR);
94	ctrl_barrier();
95	local_irq_restore(flags);
96}