Loading...
1/*
2 * This file contains the functions and defines necessary to modify and
3 * use the SuperH page table tree.
4 *
5 * Copyright (C) 1999 Niibe Yutaka
6 * Copyright (C) 2002 - 2007 Paul Mundt
7 *
8 * This file is subject to the terms and conditions of the GNU General
9 * Public License. See the file "COPYING" in the main directory of this
10 * archive for more details.
11 */
12#ifndef __ASM_SH_PGTABLE_H
13#define __ASM_SH_PGTABLE_H
14
15#ifdef CONFIG_X2TLB
16#include <asm/pgtable-3level.h>
17#else
18#include <asm/pgtable-2level.h>
19#endif
20#include <asm/page.h>
21#include <asm/mmu.h>
22
23#ifndef __ASSEMBLY__
24#include <asm/addrspace.h>
25#include <asm/fixmap.h>
26
27/*
28 * ZERO_PAGE is a global shared page that is always zero: used
29 * for zero-mapped memory areas etc..
30 */
31extern unsigned long empty_zero_page[PAGE_SIZE / sizeof(unsigned long)];
32#define ZERO_PAGE(vaddr) (virt_to_page(empty_zero_page))
33
34#endif /* !__ASSEMBLY__ */
35
36/*
37 * Effective and physical address definitions, to aid with sign
38 * extension.
39 */
40#define NEFF 32
41#define NEFF_SIGN (1LL << (NEFF - 1))
42#define NEFF_MASK (-1LL << NEFF)
43
44static inline unsigned long long neff_sign_extend(unsigned long val)
45{
46 unsigned long long extended = val;
47 return (extended & NEFF_SIGN) ? (extended | NEFF_MASK) : extended;
48}
49
50#ifdef CONFIG_29BIT
51#define NPHYS 29
52#else
53#define NPHYS 32
54#endif
55
56#define NPHYS_SIGN (1LL << (NPHYS - 1))
57#define NPHYS_MASK (-1LL << NPHYS)
58
59#define PGDIR_SIZE (1UL << PGDIR_SHIFT)
60#define PGDIR_MASK (~(PGDIR_SIZE-1))
61
62/* Entries per level */
63#define PTRS_PER_PTE (PAGE_SIZE / (1 << PTE_MAGNITUDE))
64
65#define FIRST_USER_ADDRESS 0
66
67#define PHYS_ADDR_MASK29 0x1fffffff
68#define PHYS_ADDR_MASK32 0xffffffff
69
70static inline unsigned long phys_addr_mask(void)
71{
72 /* Is the MMU in 29bit mode? */
73 if (__in_29bit_mode())
74 return PHYS_ADDR_MASK29;
75
76 return PHYS_ADDR_MASK32;
77}
78
79#define PTE_PHYS_MASK (phys_addr_mask() & PAGE_MASK)
80#define PTE_FLAGS_MASK (~(PTE_PHYS_MASK) << PAGE_SHIFT)
81
82#ifdef CONFIG_SUPERH32
83#define VMALLOC_START (P3SEG)
84#else
85#define VMALLOC_START (0xf0000000)
86#endif
87#define VMALLOC_END (FIXADDR_START-2*PAGE_SIZE)
88
89#if defined(CONFIG_SUPERH32)
90#include <asm/pgtable_32.h>
91#else
92#include <asm/pgtable_64.h>
93#endif
94
95/*
96 * SH-X and lower (legacy) SuperH parts (SH-3, SH-4, some SH-4A) can't do page
97 * protection for execute, and considers it the same as a read. Also, write
98 * permission implies read permission. This is the closest we can get..
99 *
100 * SH-X2 (SH7785) and later parts take this to the opposite end of the extreme,
101 * not only supporting separate execute, read, and write bits, but having
102 * completely separate permission bits for user and kernel space.
103 */
104 /*xwr*/
105#define __P000 PAGE_NONE
106#define __P001 PAGE_READONLY
107#define __P010 PAGE_COPY
108#define __P011 PAGE_COPY
109#define __P100 PAGE_EXECREAD
110#define __P101 PAGE_EXECREAD
111#define __P110 PAGE_COPY
112#define __P111 PAGE_COPY
113
114#define __S000 PAGE_NONE
115#define __S001 PAGE_READONLY
116#define __S010 PAGE_WRITEONLY
117#define __S011 PAGE_SHARED
118#define __S100 PAGE_EXECREAD
119#define __S101 PAGE_EXECREAD
120#define __S110 PAGE_RWX
121#define __S111 PAGE_RWX
122
123typedef pte_t *pte_addr_t;
124
125#define kern_addr_valid(addr) (1)
126
127#define io_remap_pfn_range(vma, vaddr, pfn, size, prot) \
128 remap_pfn_range(vma, vaddr, pfn, size, prot)
129
130#define pte_pfn(x) ((unsigned long)(((x).pte_low >> PAGE_SHIFT)))
131
132/*
133 * Initialise the page table caches
134 */
135extern void pgtable_cache_init(void);
136
137struct vm_area_struct;
138struct mm_struct;
139
140extern void __update_cache(struct vm_area_struct *vma,
141 unsigned long address, pte_t pte);
142extern void __update_tlb(struct vm_area_struct *vma,
143 unsigned long address, pte_t pte);
144
145static inline void
146update_mmu_cache(struct vm_area_struct *vma, unsigned long address, pte_t *ptep)
147{
148 pte_t pte = *ptep;
149 __update_cache(vma, address, pte);
150 __update_tlb(vma, address, pte);
151}
152
153extern pgd_t swapper_pg_dir[PTRS_PER_PGD];
154extern void paging_init(void);
155extern void page_table_range_init(unsigned long start, unsigned long end,
156 pgd_t *pgd);
157
158/* arch/sh/mm/mmap.c */
159#define HAVE_ARCH_UNMAPPED_AREA
160#define HAVE_ARCH_UNMAPPED_AREA_TOPDOWN
161
162#define __HAVE_ARCH_PTE_SPECIAL
163
164#include <asm-generic/pgtable.h>
165
166#endif /* __ASM_SH_PGTABLE_H */
1/* SPDX-License-Identifier: GPL-2.0
2 *
3 * This file contains the functions and defines necessary to modify and
4 * use the SuperH page table tree.
5 *
6 * Copyright (C) 1999 Niibe Yutaka
7 * Copyright (C) 2002 - 2007 Paul Mundt
8 */
9#ifndef __ASM_SH_PGTABLE_H
10#define __ASM_SH_PGTABLE_H
11
12#ifdef CONFIG_X2TLB
13#include <asm/pgtable-3level.h>
14#else
15#include <asm/pgtable-2level.h>
16#endif
17#include <asm/page.h>
18#include <asm/mmu.h>
19
20#ifndef __ASSEMBLY__
21#include <asm/addrspace.h>
22#include <asm/fixmap.h>
23
24/*
25 * ZERO_PAGE is a global shared page that is always zero: used
26 * for zero-mapped memory areas etc..
27 */
28extern unsigned long empty_zero_page[PAGE_SIZE / sizeof(unsigned long)];
29#define ZERO_PAGE(vaddr) (virt_to_page(empty_zero_page))
30
31#endif /* !__ASSEMBLY__ */
32
33/*
34 * Effective and physical address definitions, to aid with sign
35 * extension.
36 */
37#define NEFF 32
38#define NEFF_SIGN (1LL << (NEFF - 1))
39#define NEFF_MASK (-1LL << NEFF)
40
41static inline unsigned long long neff_sign_extend(unsigned long val)
42{
43 unsigned long long extended = val;
44 return (extended & NEFF_SIGN) ? (extended | NEFF_MASK) : extended;
45}
46
47#ifdef CONFIG_29BIT
48#define NPHYS 29
49#else
50#define NPHYS 32
51#endif
52
53#define NPHYS_SIGN (1LL << (NPHYS - 1))
54#define NPHYS_MASK (-1LL << NPHYS)
55
56#define PGDIR_SIZE (1UL << PGDIR_SHIFT)
57#define PGDIR_MASK (~(PGDIR_SIZE-1))
58
59/* Entries per level */
60#define PTRS_PER_PTE (PAGE_SIZE / (1 << PTE_MAGNITUDE))
61
62#define FIRST_USER_ADDRESS 0UL
63
64#define PHYS_ADDR_MASK29 0x1fffffff
65#define PHYS_ADDR_MASK32 0xffffffff
66
67static inline unsigned long phys_addr_mask(void)
68{
69 /* Is the MMU in 29bit mode? */
70 if (__in_29bit_mode())
71 return PHYS_ADDR_MASK29;
72
73 return PHYS_ADDR_MASK32;
74}
75
76#define PTE_PHYS_MASK (phys_addr_mask() & PAGE_MASK)
77#define PTE_FLAGS_MASK (~(PTE_PHYS_MASK) << PAGE_SHIFT)
78
79#ifdef CONFIG_SUPERH32
80#define VMALLOC_START (P3SEG)
81#else
82#define VMALLOC_START (0xf0000000)
83#endif
84#define VMALLOC_END (FIXADDR_START-2*PAGE_SIZE)
85
86#if defined(CONFIG_SUPERH32)
87#include <asm/pgtable_32.h>
88#else
89#include <asm/pgtable_64.h>
90#endif
91
92/*
93 * SH-X and lower (legacy) SuperH parts (SH-3, SH-4, some SH-4A) can't do page
94 * protection for execute, and considers it the same as a read. Also, write
95 * permission implies read permission. This is the closest we can get..
96 *
97 * SH-X2 (SH7785) and later parts take this to the opposite end of the extreme,
98 * not only supporting separate execute, read, and write bits, but having
99 * completely separate permission bits for user and kernel space.
100 */
101 /*xwr*/
102#define __P000 PAGE_NONE
103#define __P001 PAGE_READONLY
104#define __P010 PAGE_COPY
105#define __P011 PAGE_COPY
106#define __P100 PAGE_EXECREAD
107#define __P101 PAGE_EXECREAD
108#define __P110 PAGE_COPY
109#define __P111 PAGE_COPY
110
111#define __S000 PAGE_NONE
112#define __S001 PAGE_READONLY
113#define __S010 PAGE_WRITEONLY
114#define __S011 PAGE_SHARED
115#define __S100 PAGE_EXECREAD
116#define __S101 PAGE_EXECREAD
117#define __S110 PAGE_RWX
118#define __S111 PAGE_RWX
119
120typedef pte_t *pte_addr_t;
121
122#define kern_addr_valid(addr) (1)
123
124#define pte_pfn(x) ((unsigned long)(((x).pte_low >> PAGE_SHIFT)))
125
126struct vm_area_struct;
127struct mm_struct;
128
129extern void __update_cache(struct vm_area_struct *vma,
130 unsigned long address, pte_t pte);
131extern void __update_tlb(struct vm_area_struct *vma,
132 unsigned long address, pte_t pte);
133
134static inline void
135update_mmu_cache(struct vm_area_struct *vma, unsigned long address, pte_t *ptep)
136{
137 pte_t pte = *ptep;
138 __update_cache(vma, address, pte);
139 __update_tlb(vma, address, pte);
140}
141
142extern pgd_t swapper_pg_dir[PTRS_PER_PGD];
143extern void paging_init(void);
144extern void page_table_range_init(unsigned long start, unsigned long end,
145 pgd_t *pgd);
146
147static inline bool __pte_access_permitted(pte_t pte, u64 prot)
148{
149 return (pte_val(pte) & (prot | _PAGE_SPECIAL)) == prot;
150}
151
152#ifdef CONFIG_X2TLB
153static inline bool pte_access_permitted(pte_t pte, bool write)
154{
155 u64 prot = _PAGE_PRESENT;
156
157 prot |= _PAGE_EXT(_PAGE_EXT_KERN_READ | _PAGE_EXT_USER_READ);
158 if (write)
159 prot |= _PAGE_EXT(_PAGE_EXT_KERN_WRITE | _PAGE_EXT_USER_WRITE);
160 return __pte_access_permitted(pte, prot);
161}
162#elif defined(CONFIG_SUPERH64)
163static inline bool pte_access_permitted(pte_t pte, bool write)
164{
165 u64 prot = _PAGE_PRESENT | _PAGE_USER | _PAGE_READ;
166
167 if (write)
168 prot |= _PAGE_WRITE;
169 return __pte_access_permitted(pte, prot);
170}
171#else
172static inline bool pte_access_permitted(pte_t pte, bool write)
173{
174 u64 prot = _PAGE_PRESENT | _PAGE_USER;
175
176 if (write)
177 prot |= _PAGE_RW;
178 return __pte_access_permitted(pte, prot);
179}
180#endif
181
182#define pte_access_permitted pte_access_permitted
183
184/* arch/sh/mm/mmap.c */
185#define HAVE_ARCH_UNMAPPED_AREA
186#define HAVE_ARCH_UNMAPPED_AREA_TOPDOWN
187
188#include <asm-generic/pgtable.h>
189
190#endif /* __ASM_SH_PGTABLE_H */