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1/*
2 * Carsten Langgaard, carstenl@mips.com
3 * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved.
4 *
5 * This program is free software; you can distribute it and/or modify it
6 * under the terms of the GNU General Public License (Version 2) as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * for more details.
13 *
14 * You should have received a copy of the GNU General Public License along
15 * with this program; if not, write to the Free Software Foundation, Inc.,
16 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
17 *
18 * Register definitions for Intel PIIX4 South Bridge Device.
19 */
20#ifndef __ASM_MIPS_BOARDS_PIIX4_H
21#define __ASM_MIPS_BOARDS_PIIX4_H
22
23/************************************************************************
24 * IO register offsets
25 ************************************************************************/
26#define PIIX4_ICTLR1_ICW1 0x20
27#define PIIX4_ICTLR1_ICW2 0x21
28#define PIIX4_ICTLR1_ICW3 0x21
29#define PIIX4_ICTLR1_ICW4 0x21
30#define PIIX4_ICTLR2_ICW1 0xa0
31#define PIIX4_ICTLR2_ICW2 0xa1
32#define PIIX4_ICTLR2_ICW3 0xa1
33#define PIIX4_ICTLR2_ICW4 0xa1
34#define PIIX4_ICTLR1_OCW1 0x21
35#define PIIX4_ICTLR1_OCW2 0x20
36#define PIIX4_ICTLR1_OCW3 0x20
37#define PIIX4_ICTLR1_OCW4 0x20
38#define PIIX4_ICTLR2_OCW1 0xa1
39#define PIIX4_ICTLR2_OCW2 0xa0
40#define PIIX4_ICTLR2_OCW3 0xa0
41#define PIIX4_ICTLR2_OCW4 0xa0
42
43
44/************************************************************************
45 * Register encodings.
46 ************************************************************************/
47#define PIIX4_OCW2_NSEOI (0x1 << 5)
48#define PIIX4_OCW2_SEOI (0x3 << 5)
49#define PIIX4_OCW2_RNSEOI (0x5 << 5)
50#define PIIX4_OCW2_RAEOIS (0x4 << 5)
51#define PIIX4_OCW2_RAEOIC (0x0 << 5)
52#define PIIX4_OCW2_RSEOI (0x7 << 5)
53#define PIIX4_OCW2_SP (0x6 << 5)
54#define PIIX4_OCW2_NOP (0x2 << 5)
55
56#define PIIX4_OCW2_SEL (0x0 << 3)
57
58#define PIIX4_OCW2_ILS_0 0
59#define PIIX4_OCW2_ILS_1 1
60#define PIIX4_OCW2_ILS_2 2
61#define PIIX4_OCW2_ILS_3 3
62#define PIIX4_OCW2_ILS_4 4
63#define PIIX4_OCW2_ILS_5 5
64#define PIIX4_OCW2_ILS_6 6
65#define PIIX4_OCW2_ILS_7 7
66#define PIIX4_OCW2_ILS_8 0
67#define PIIX4_OCW2_ILS_9 1
68#define PIIX4_OCW2_ILS_10 2
69#define PIIX4_OCW2_ILS_11 3
70#define PIIX4_OCW2_ILS_12 4
71#define PIIX4_OCW2_ILS_13 5
72#define PIIX4_OCW2_ILS_14 6
73#define PIIX4_OCW2_ILS_15 7
74
75#define PIIX4_OCW3_SEL (0x1 << 3)
76
77#define PIIX4_OCW3_IRR 0x2
78#define PIIX4_OCW3_ISR 0x3
79
80#endif /* __ASM_MIPS_BOARDS_PIIX4_H */
1/* SPDX-License-Identifier: GPL-2.0-only */
2/*
3 * Carsten Langgaard, carstenl@mips.com
4 * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved.
5 * Copyright (C) 2013 Imagination Technologies Ltd.
6 *
7 * Register definitions for Intel PIIX4 South Bridge Device.
8 */
9#ifndef __ASM_MIPS_BOARDS_PIIX4_H
10#define __ASM_MIPS_BOARDS_PIIX4_H
11
12/* PIRQX Route Control */
13#define PIIX4_FUNC0_PIRQRC 0x60
14#define PIIX4_FUNC0_PIRQRC_IRQ_ROUTING_DISABLE (1 << 7)
15#define PIIX4_FUNC0_PIRQRC_IRQ_ROUTING_MASK 0xf
16#define PIIX4_FUNC0_PIRQRC_IRQ_ROUTING_MAX 16
17/* SERIRQ Control */
18#define PIIX4_FUNC0_SERIRQC 0x64
19#define PIIX4_FUNC0_SERIRQC_EN (1 << 7)
20#define PIIX4_FUNC0_SERIRQC_CONT (1 << 6)
21/* Top Of Memory */
22#define PIIX4_FUNC0_TOM 0x69
23#define PIIX4_FUNC0_TOM_TOP_OF_MEMORY_MASK 0xf0
24/* Deterministic Latency Control */
25#define PIIX4_FUNC0_DLC 0x82
26#define PIIX4_FUNC0_DLC_USBPR_EN (1 << 2)
27#define PIIX4_FUNC0_DLC_PASSIVE_RELEASE_EN (1 << 1)
28#define PIIX4_FUNC0_DLC_DELAYED_TRANSACTION_EN (1 << 0)
29/* General Configuration */
30#define PIIX4_FUNC0_GENCFG 0xb0
31#define PIIX4_FUNC0_GENCFG_SERIRQ (1 << 16)
32
33/* IDE Timing */
34#define PIIX4_FUNC1_IDETIM_PRIMARY_LO 0x40
35#define PIIX4_FUNC1_IDETIM_PRIMARY_HI 0x41
36#define PIIX4_FUNC1_IDETIM_PRIMARY_HI_IDE_DECODE_EN (1 << 7)
37#define PIIX4_FUNC1_IDETIM_SECONDARY_LO 0x42
38#define PIIX4_FUNC1_IDETIM_SECONDARY_HI 0x43
39#define PIIX4_FUNC1_IDETIM_SECONDARY_HI_IDE_DECODE_EN (1 << 7)
40
41/* Power Management Configuration Space */
42#define PIIX4_FUNC3_PMBA 0x40
43#define PIIX4_FUNC3_PMREGMISC 0x80
44#define PIIX4_FUNC3_PMREGMISC_EN (1 << 0)
45
46/* Power Management IO Space */
47#define PIIX4_FUNC3IO_PMSTS 0x00
48#define PIIX4_FUNC3IO_PMSTS_PWRBTN_STS (1 << 8)
49#define PIIX4_FUNC3IO_PMCNTRL 0x04
50#define PIIX4_FUNC3IO_PMCNTRL_SUS_EN (1 << 13)
51#define PIIX4_FUNC3IO_PMCNTRL_SUS_TYP (0x7 << 10)
52#define PIIX4_FUNC3IO_PMCNTRL_SUS_TYP_SOFF (0x0 << 10)
53#define PIIX4_FUNC3IO_PMCNTRL_SUS_TYP_STR (0x1 << 10)
54
55/* Data for magic special PCI cycle */
56#define PIIX4_SUSPEND_MAGIC 0x00120002
57
58#endif /* __ASM_MIPS_BOARDS_PIIX4_H */