1/*
 2 *  linux/arch/arm/mm/tlb-v7.S
 3 *
 4 *  Copyright (C) 1997-2002 Russell King
 5 *  Modified for ARMv7 by Catalin Marinas
 6 *
 7 * This program is free software; you can redistribute it and/or modify
 8 * it under the terms of the GNU General Public License version 2 as
 9 * published by the Free Software Foundation.
10 *
11 *  ARM architecture version 6 TLB handling functions.
12 *  These assume a split I/D TLB.
13 */
14#include <linux/init.h>
15#include <linux/linkage.h>
16#include <asm/assembler.h>
17#include <asm/asm-offsets.h>
18#include <asm/page.h>
19#include <asm/tlbflush.h>
20#include "proc-macros.S"
21
22/*
23 *	v7wbi_flush_user_tlb_range(start, end, vma)
24 *
25 *	Invalidate a range of TLB entries in the specified address space.
26 *
27 *	- start - start address (may not be aligned)
28 *	- end   - end address (exclusive, may not be aligned)
29 *	- vma   - vma_struct describing address range
30 *
31 *	It is assumed that:
32 *	- the "Invalidate single entry" instruction will invalidate
33 *	  both the I and the D TLBs on Harvard-style TLBs
34 */
35ENTRY(v7wbi_flush_user_tlb_range)
36	vma_vm_mm r3, r2			@ get vma->vm_mm
37	mmid	r3, r3				@ get vm_mm->context.id
38	dsb
39	mov	r0, r0, lsr #PAGE_SHIFT		@ align address
40	mov	r1, r1, lsr #PAGE_SHIFT
41	asid	r3, r3				@ mask ASID
 
 
 
 
42	orr	r0, r3, r0, lsl #PAGE_SHIFT	@ Create initial MVA
43	mov	r1, r1, lsl #PAGE_SHIFT
441:
 
 
 
45	ALT_SMP(mcr	p15, 0, r0, c8, c3, 1)	@ TLB invalidate U MVA (shareable)
 
46	ALT_UP(mcr	p15, 0, r0, c8, c7, 1)	@ TLB invalidate U MVA
47
48	add	r0, r0, #PAGE_SZ
49	cmp	r0, r1
50	blo	1b
51	dsb
52	mov	pc, lr
53ENDPROC(v7wbi_flush_user_tlb_range)
54
55/*
56 *	v7wbi_flush_kern_tlb_range(start,end)
57 *
58 *	Invalidate a range of kernel TLB entries
59 *
60 *	- start - start address (may not be aligned)
61 *	- end   - end address (exclusive, may not be aligned)
62 */
63ENTRY(v7wbi_flush_kern_tlb_range)
64	dsb
65	mov	r0, r0, lsr #PAGE_SHIFT		@ align address
66	mov	r1, r1, lsr #PAGE_SHIFT
67	mov	r0, r0, lsl #PAGE_SHIFT
68	mov	r1, r1, lsl #PAGE_SHIFT
691:
 
 
 
70	ALT_SMP(mcr	p15, 0, r0, c8, c3, 1)	@ TLB invalidate U MVA (shareable)
 
71	ALT_UP(mcr	p15, 0, r0, c8, c7, 1)	@ TLB invalidate U MVA
72	add	r0, r0, #PAGE_SZ
73	cmp	r0, r1
74	blo	1b
75	dsb
76	isb
77	mov	pc, lr
78ENDPROC(v7wbi_flush_kern_tlb_range)
79
80	__INIT
81
82	/* define struct cpu_tlb_fns (see <asm/tlbflush.h> and proc-macros.S) */
83	define_tlb_functions v7wbi, v7wbi_tlb_flags_up, flags_smp=v7wbi_tlb_flags_smp

 1/* SPDX-License-Identifier: GPL-2.0-only */
 2/*
 3 *  linux/arch/arm/mm/tlb-v7.S
 4 *
 5 *  Copyright (C) 1997-2002 Russell King
 6 *  Modified for ARMv7 by Catalin Marinas
 7 *
 
 
 
 
 8 *  ARM architecture version 6 TLB handling functions.
 9 *  These assume a split I/D TLB.
10 */
11#include <linux/init.h>
12#include <linux/linkage.h>
13#include <asm/assembler.h>
14#include <asm/asm-offsets.h>
15#include <asm/page.h>
16#include <asm/tlbflush.h>
17#include "proc-macros.S"
18
19/*
20 *	v7wbi_flush_user_tlb_range(start, end, vma)
21 *
22 *	Invalidate a range of TLB entries in the specified address space.
23 *
24 *	- start - start address (may not be aligned)
25 *	- end   - end address (exclusive, may not be aligned)
26 *	- vma   - vma_struct describing address range
27 *
28 *	It is assumed that:
29 *	- the "Invalidate single entry" instruction will invalidate
30 *	  both the I and the D TLBs on Harvard-style TLBs
31 */
32ENTRY(v7wbi_flush_user_tlb_range)
33	vma_vm_mm r3, r2			@ get vma->vm_mm
34	mmid	r3, r3				@ get vm_mm->context.id
35	dsb	ish
36	mov	r0, r0, lsr #PAGE_SHIFT		@ align address
37	mov	r1, r1, lsr #PAGE_SHIFT
38	asid	r3, r3				@ mask ASID
39#ifdef CONFIG_ARM_ERRATA_720789
40	ALT_SMP(W(mov)	r3, #0	)
41	ALT_UP(W(nop)		)
42#endif
43	orr	r0, r3, r0, lsl #PAGE_SHIFT	@ Create initial MVA
44	mov	r1, r1, lsl #PAGE_SHIFT
451:
46#ifdef CONFIG_ARM_ERRATA_720789
47	ALT_SMP(mcr	p15, 0, r0, c8, c3, 3)	@ TLB invalidate U MVA all ASID (shareable)
48#else
49	ALT_SMP(mcr	p15, 0, r0, c8, c3, 1)	@ TLB invalidate U MVA (shareable)
50#endif
51	ALT_UP(mcr	p15, 0, r0, c8, c7, 1)	@ TLB invalidate U MVA
52
53	add	r0, r0, #PAGE_SZ
54	cmp	r0, r1
55	blo	1b
56	dsb	ish
57	ret	lr
58ENDPROC(v7wbi_flush_user_tlb_range)
59
60/*
61 *	v7wbi_flush_kern_tlb_range(start,end)
62 *
63 *	Invalidate a range of kernel TLB entries
64 *
65 *	- start - start address (may not be aligned)
66 *	- end   - end address (exclusive, may not be aligned)
67 */
68ENTRY(v7wbi_flush_kern_tlb_range)
69	dsb	ish
70	mov	r0, r0, lsr #PAGE_SHIFT		@ align address
71	mov	r1, r1, lsr #PAGE_SHIFT
72	mov	r0, r0, lsl #PAGE_SHIFT
73	mov	r1, r1, lsl #PAGE_SHIFT
741:
75#ifdef CONFIG_ARM_ERRATA_720789
76	ALT_SMP(mcr	p15, 0, r0, c8, c3, 3)	@ TLB invalidate U MVA all ASID (shareable)
77#else
78	ALT_SMP(mcr	p15, 0, r0, c8, c3, 1)	@ TLB invalidate U MVA (shareable)
79#endif
80	ALT_UP(mcr	p15, 0, r0, c8, c7, 1)	@ TLB invalidate U MVA
81	add	r0, r0, #PAGE_SZ
82	cmp	r0, r1
83	blo	1b
84	dsb	ish
85	isb
86	ret	lr
87ENDPROC(v7wbi_flush_kern_tlb_range)
88
89	__INIT
90
91	/* define struct cpu_tlb_fns (see <asm/tlbflush.h> and proc-macros.S) */
92	define_tlb_functions v7wbi, v7wbi_tlb_flags_up, flags_smp=v7wbi_tlb_flags_smp