1/*
 2 * interrupt controller support for CSR SiRFprimaII
 3 *
 4 * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
 5 *
 6 * Licensed under GPLv2 or later.
 7 */
 8
 9#include <linux/init.h>
10#include <linux/io.h>
11#include <linux/irq.h>
12#include <mach/hardware.h>
13#include <asm/mach/irq.h>
14#include <linux/of.h>
15#include <linux/of_address.h>
16
17#define SIRFSOC_INT_RISC_MASK0          0x0018
18#define SIRFSOC_INT_RISC_MASK1          0x001C
19#define SIRFSOC_INT_RISC_LEVEL0         0x0020
20#define SIRFSOC_INT_RISC_LEVEL1         0x0024
21
22void __iomem *sirfsoc_intc_base;
23
24static __init void
25sirfsoc_alloc_gc(void __iomem *base, unsigned int irq_start, unsigned int num)
26{
27	struct irq_chip_generic *gc;
28	struct irq_chip_type *ct;
29
30	gc = irq_alloc_generic_chip("SIRFINTC", 1, irq_start, base, handle_level_irq);
31	ct = gc->chip_types;
32
33	ct->chip.irq_mask = irq_gc_mask_clr_bit;
34	ct->chip.irq_unmask = irq_gc_mask_set_bit;
35	ct->regs.mask = SIRFSOC_INT_RISC_MASK0;
36
37	irq_setup_generic_chip(gc, IRQ_MSK(num), IRQ_GC_INIT_MASK_CACHE, IRQ_NOREQUEST, 0);
38}
39
40static __init void sirfsoc_irq_init(void)
41{
42	sirfsoc_alloc_gc(sirfsoc_intc_base, 0, 32);
43	sirfsoc_alloc_gc(sirfsoc_intc_base + 4, 32, SIRFSOC_INTENAL_IRQ_END - 32);
44
45	writel_relaxed(0, sirfsoc_intc_base + SIRFSOC_INT_RISC_LEVEL0);
46	writel_relaxed(0, sirfsoc_intc_base + SIRFSOC_INT_RISC_LEVEL1);
47
48	writel_relaxed(0, sirfsoc_intc_base + SIRFSOC_INT_RISC_MASK0);
49	writel_relaxed(0, sirfsoc_intc_base + SIRFSOC_INT_RISC_MASK1);
50}
51
52static struct of_device_id intc_ids[]  = {
53	{ .compatible = "sirf,prima2-intc" },
54	{},
55};
56
57void __init sirfsoc_of_irq_init(void)
58{
59	struct device_node *np;
60
61	np = of_find_matching_node(NULL, intc_ids);
62	if (!np)
63		panic("unable to find compatible intc node in dtb\n");
64
65	sirfsoc_intc_base = of_iomap(np, 0);
66	if (!sirfsoc_intc_base)
67		panic("unable to map intc cpu registers\n");
68
69	of_node_put(np);
70
71	sirfsoc_irq_init();
72}