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1/*
2 * Driver for Digigram VX soundcards
3 *
4 * Hardware core part
5 *
6 * Copyright (c) 2002 by Takashi Iwai <tiwai@suse.de>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21 */
22
23#ifndef __SOUND_VX_COMMON_H
24#define __SOUND_VX_COMMON_H
25
26#include <sound/pcm.h>
27#include <sound/hwdep.h>
28#include <linux/interrupt.h>
29
30#if defined(CONFIG_FW_LOADER) || defined(CONFIG_FW_LOADER_MODULE)
31#if !defined(CONFIG_USE_VXLOADER) && !defined(CONFIG_SND_VX_LIB) /* built-in kernel */
32#define SND_VX_FW_LOADER /* use the standard firmware loader */
33#endif
34#endif
35
36struct firmware;
37struct device;
38
39#define VX_DRIVER_VERSION 0x010000 /* 1.0.0 */
40
41/*
42 */
43#define SIZE_MAX_CMD 0x10
44#define SIZE_MAX_STATUS 0x10
45
46struct vx_rmh {
47 u16 LgCmd; /* length of the command to send (WORDs) */
48 u16 LgStat; /* length of the status received (WORDs) */
49 u32 Cmd[SIZE_MAX_CMD];
50 u32 Stat[SIZE_MAX_STATUS];
51 u16 DspStat; /* status type, RMP_SSIZE_XXX */
52};
53
54typedef u64 pcx_time_t;
55
56#define VX_MAX_PIPES 16
57#define VX_MAX_PERIODS 32
58#define VX_MAX_CODECS 2
59
60struct vx_ibl_info {
61 int size; /* the current IBL size (0 = query) in bytes */
62 int max_size; /* max. IBL size in bytes */
63 int min_size; /* min. IBL size in bytes */
64 int granularity; /* granularity */
65};
66
67struct vx_pipe {
68 int number;
69 unsigned int is_capture: 1;
70 unsigned int data_mode: 1;
71 unsigned int running: 1;
72 unsigned int prepared: 1;
73 int channels;
74 unsigned int differed_type;
75 pcx_time_t pcx_time;
76 struct snd_pcm_substream *substream;
77
78 int hbuf_size; /* H-buffer size in bytes */
79 int buffer_bytes; /* the ALSA pcm buffer size in bytes */
80 int period_bytes; /* the ALSA pcm period size in bytes */
81 int hw_ptr; /* the current hardware pointer in bytes */
82 int position; /* the current position in frames (playback only) */
83 int transferred; /* the transferred size (per period) in frames */
84 int align; /* size of alignment */
85 u64 cur_count; /* current sample position (for playback) */
86
87 unsigned int references; /* an output pipe may be used for monitoring and/or playback */
88 struct vx_pipe *monitoring_pipe; /* pointer to the monitoring pipe (capture pipe only)*/
89
90 struct tasklet_struct start_tq;
91};
92
93struct vx_core;
94
95struct snd_vx_ops {
96 /* low-level i/o */
97 unsigned char (*in8)(struct vx_core *chip, int reg);
98 unsigned int (*in32)(struct vx_core *chip, int reg);
99 void (*out8)(struct vx_core *chip, int reg, unsigned char val);
100 void (*out32)(struct vx_core *chip, int reg, unsigned int val);
101 /* irq */
102 int (*test_and_ack)(struct vx_core *chip);
103 void (*validate_irq)(struct vx_core *chip, int enable);
104 /* codec */
105 void (*write_codec)(struct vx_core *chip, int codec, unsigned int data);
106 void (*akm_write)(struct vx_core *chip, int reg, unsigned int data);
107 void (*reset_codec)(struct vx_core *chip);
108 void (*change_audio_source)(struct vx_core *chip, int src);
109 void (*set_clock_source)(struct vx_core *chp, int src);
110 /* chip init */
111 int (*load_dsp)(struct vx_core *chip, int idx, const struct firmware *fw);
112 void (*reset_dsp)(struct vx_core *chip);
113 void (*reset_board)(struct vx_core *chip, int cold_reset);
114 int (*add_controls)(struct vx_core *chip);
115 /* pcm */
116 void (*dma_write)(struct vx_core *chip, struct snd_pcm_runtime *runtime,
117 struct vx_pipe *pipe, int count);
118 void (*dma_read)(struct vx_core *chip, struct snd_pcm_runtime *runtime,
119 struct vx_pipe *pipe, int count);
120};
121
122struct snd_vx_hardware {
123 const char *name;
124 int type; /* VX_TYPE_XXX */
125
126 /* hardware specs */
127 unsigned int num_codecs;
128 unsigned int num_ins;
129 unsigned int num_outs;
130 unsigned int output_level_max;
131 const unsigned int *output_level_db_scale;
132};
133
134/* hwdep id string */
135#define SND_VX_HWDEP_ID "VX Loader"
136
137/* hardware type */
138enum {
139 /* VX222 PCI */
140 VX_TYPE_BOARD, /* old VX222 PCI */
141 VX_TYPE_V2, /* VX222 V2 PCI */
142 VX_TYPE_MIC, /* VX222 Mic PCI */
143 /* VX-pocket */
144 VX_TYPE_VXPOCKET, /* VXpocket V2 */
145 VX_TYPE_VXP440, /* VXpocket 440 */
146 VX_TYPE_NUMS
147};
148
149/* chip status */
150enum {
151 VX_STAT_XILINX_LOADED = (1 << 0), /* devices are registered */
152 VX_STAT_DEVICE_INIT = (1 << 1), /* devices are registered */
153 VX_STAT_CHIP_INIT = (1 << 2), /* all operational */
154 VX_STAT_IN_SUSPEND = (1 << 10), /* in suspend phase */
155 VX_STAT_IS_STALE = (1 << 15) /* device is stale */
156};
157
158/* min/max values for analog output for old codecs */
159#define VX_ANALOG_OUT_LEVEL_MAX 0xe3
160
161struct vx_core {
162 /* ALSA stuff */
163 struct snd_card *card;
164 struct snd_pcm *pcm[VX_MAX_CODECS];
165 int type; /* VX_TYPE_XXX */
166
167 int irq;
168 /* ports are defined externally */
169
170 /* low-level functions */
171 struct snd_vx_hardware *hw;
172 struct snd_vx_ops *ops;
173
174 spinlock_t lock;
175 spinlock_t irq_lock;
176 struct tasklet_struct tq;
177
178 unsigned int chip_status;
179 unsigned int pcm_running;
180
181 struct device *dev;
182 struct snd_hwdep *hwdep;
183
184 struct vx_rmh irq_rmh; /* RMH used in interrupts */
185
186 unsigned int audio_info; /* see VX_AUDIO_INFO */
187 unsigned int audio_ins;
188 unsigned int audio_outs;
189 struct vx_pipe **playback_pipes;
190 struct vx_pipe **capture_pipes;
191
192 /* clock and audio sources */
193 unsigned int audio_source; /* current audio input source */
194 unsigned int audio_source_target;
195 unsigned int clock_mode; /* clock mode (VX_CLOCK_MODE_XXX) */
196 unsigned int clock_source; /* current clock source (INTERNAL_QUARTZ or UER_SYNC) */
197 unsigned int freq; /* current frequency */
198 unsigned int freq_detected; /* detected frequency from digital in */
199 unsigned int uer_detected; /* VX_UER_MODE_XXX */
200 unsigned int uer_bits; /* IEC958 status bits */
201 struct vx_ibl_info ibl; /* IBL information */
202
203 /* mixer setting */
204 int output_level[VX_MAX_CODECS][2]; /* analog output level */
205 int audio_gain[2][4]; /* digital audio level (playback/capture) */
206 unsigned char audio_active[4]; /* mute/unmute on digital playback */
207 int audio_monitor[4]; /* playback hw-monitor level */
208 unsigned char audio_monitor_active[4]; /* playback hw-monitor mute/unmute */
209
210 struct mutex mixer_mutex;
211
212 const struct firmware *firmware[4]; /* loaded firmware data */
213};
214
215
216/*
217 * constructor
218 */
219struct vx_core *snd_vx_create(struct snd_card *card, struct snd_vx_hardware *hw,
220 struct snd_vx_ops *ops, int extra_size);
221int snd_vx_setup_firmware(struct vx_core *chip);
222int snd_vx_load_boot_image(struct vx_core *chip, const struct firmware *dsp);
223int snd_vx_dsp_boot(struct vx_core *chip, const struct firmware *dsp);
224int snd_vx_dsp_load(struct vx_core *chip, const struct firmware *dsp);
225
226void snd_vx_free_firmware(struct vx_core *chip);
227
228/*
229 * interrupt handler; exported for pcmcia
230 */
231irqreturn_t snd_vx_irq_handler(int irq, void *dev);
232
233/*
234 * lowlevel functions
235 */
236static inline int vx_test_and_ack(struct vx_core *chip)
237{
238 return chip->ops->test_and_ack(chip);
239}
240
241static inline void vx_validate_irq(struct vx_core *chip, int enable)
242{
243 chip->ops->validate_irq(chip, enable);
244}
245
246static inline unsigned char snd_vx_inb(struct vx_core *chip, int reg)
247{
248 return chip->ops->in8(chip, reg);
249}
250
251static inline unsigned int snd_vx_inl(struct vx_core *chip, int reg)
252{
253 return chip->ops->in32(chip, reg);
254}
255
256static inline void snd_vx_outb(struct vx_core *chip, int reg, unsigned char val)
257{
258 chip->ops->out8(chip, reg, val);
259}
260
261static inline void snd_vx_outl(struct vx_core *chip, int reg, unsigned int val)
262{
263 chip->ops->out32(chip, reg, val);
264}
265
266#define vx_inb(chip,reg) snd_vx_inb(chip, VX_##reg)
267#define vx_outb(chip,reg,val) snd_vx_outb(chip, VX_##reg,val)
268#define vx_inl(chip,reg) snd_vx_inl(chip, VX_##reg)
269#define vx_outl(chip,reg,val) snd_vx_outl(chip, VX_##reg,val)
270
271static inline void vx_reset_dsp(struct vx_core *chip)
272{
273 chip->ops->reset_dsp(chip);
274}
275
276int vx_send_msg(struct vx_core *chip, struct vx_rmh *rmh);
277int vx_send_msg_nolock(struct vx_core *chip, struct vx_rmh *rmh);
278int vx_send_rih(struct vx_core *chip, int cmd);
279int vx_send_rih_nolock(struct vx_core *chip, int cmd);
280
281void vx_reset_codec(struct vx_core *chip, int cold_reset);
282
283/*
284 * check the bit on the specified register
285 * returns zero if a bit matches, or a negative error code.
286 * exported for vxpocket driver
287 */
288int snd_vx_check_reg_bit(struct vx_core *chip, int reg, int mask, int bit, int time);
289#define vx_check_isr(chip,mask,bit,time) snd_vx_check_reg_bit(chip, VX_ISR, mask, bit, time)
290#define vx_wait_isr_bit(chip,bit) vx_check_isr(chip, bit, bit, 200)
291#define vx_wait_for_rx_full(chip) vx_wait_isr_bit(chip, ISR_RX_FULL)
292
293
294/*
295 * pseudo-DMA transfer
296 */
297static inline void vx_pseudo_dma_write(struct vx_core *chip, struct snd_pcm_runtime *runtime,
298 struct vx_pipe *pipe, int count)
299{
300 chip->ops->dma_write(chip, runtime, pipe, count);
301}
302
303static inline void vx_pseudo_dma_read(struct vx_core *chip, struct snd_pcm_runtime *runtime,
304 struct vx_pipe *pipe, int count)
305{
306 chip->ops->dma_read(chip, runtime, pipe, count);
307}
308
309
310
311/* error with hardware code,
312 * the return value is -(VX_ERR_MASK | actual-hw-error-code)
313 */
314#define VX_ERR_MASK 0x1000000
315#define vx_get_error(err) (-(err) & ~VX_ERR_MASK)
316
317
318/*
319 * pcm stuff
320 */
321int snd_vx_pcm_new(struct vx_core *chip);
322void vx_pcm_update_intr(struct vx_core *chip, unsigned int events);
323
324/*
325 * mixer stuff
326 */
327int snd_vx_mixer_new(struct vx_core *chip);
328void vx_toggle_dac_mute(struct vx_core *chip, int mute);
329int vx_sync_audio_source(struct vx_core *chip);
330int vx_set_monitor_level(struct vx_core *chip, int audio, int level, int active);
331
332/*
333 * IEC958 & clock stuff
334 */
335void vx_set_iec958_status(struct vx_core *chip, unsigned int bits);
336int vx_set_clock(struct vx_core *chip, unsigned int freq);
337void vx_set_internal_clock(struct vx_core *chip, unsigned int freq);
338int vx_change_frequency(struct vx_core *chip);
339
340
341/*
342 * PM
343 */
344int snd_vx_suspend(struct vx_core *card, pm_message_t state);
345int snd_vx_resume(struct vx_core *card);
346
347/*
348 * hardware constants
349 */
350
351#define vx_has_new_dsp(chip) ((chip)->type != VX_TYPE_BOARD)
352#define vx_is_pcmcia(chip) ((chip)->type >= VX_TYPE_VXPOCKET)
353
354/* audio input source */
355enum {
356 VX_AUDIO_SRC_DIGITAL,
357 VX_AUDIO_SRC_LINE,
358 VX_AUDIO_SRC_MIC
359};
360
361/* clock source */
362enum {
363 INTERNAL_QUARTZ,
364 UER_SYNC
365};
366
367/* clock mode */
368enum {
369 VX_CLOCK_MODE_AUTO, /* depending on the current audio source */
370 VX_CLOCK_MODE_INTERNAL, /* fixed to internal quartz */
371 VX_CLOCK_MODE_EXTERNAL /* fixed to UER sync */
372};
373
374/* SPDIF/UER type */
375enum {
376 VX_UER_MODE_CONSUMER,
377 VX_UER_MODE_PROFESSIONAL,
378 VX_UER_MODE_NOT_PRESENT,
379};
380
381/* register indices */
382enum {
383 VX_ICR,
384 VX_CVR,
385 VX_ISR,
386 VX_IVR,
387 VX_RXH,
388 VX_TXH = VX_RXH,
389 VX_RXM,
390 VX_TXM = VX_RXM,
391 VX_RXL,
392 VX_TXL = VX_RXL,
393 VX_DMA,
394 VX_CDSP,
395 VX_RFREQ,
396 VX_RUER_V2,
397 VX_GAIN,
398 VX_DATA = VX_GAIN,
399 VX_MEMIRQ,
400 VX_ACQ,
401 VX_BIT0,
402 VX_BIT1,
403 VX_MIC0,
404 VX_MIC1,
405 VX_MIC2,
406 VX_MIC3,
407 VX_PLX0,
408 VX_PLX1,
409 VX_PLX2,
410
411 VX_LOFREQ, // V2: ACQ, VP: RFREQ
412 VX_HIFREQ, // V2: BIT0, VP: RUER_V2
413 VX_CSUER, // V2: BIT1, VP: BIT0
414 VX_RUER, // V2: RUER_V2, VP: BIT1
415
416 VX_REG_MAX,
417
418 /* aliases for VX board */
419 VX_RESET_DMA = VX_ISR,
420 VX_CFG = VX_RFREQ,
421 VX_STATUS = VX_MEMIRQ,
422 VX_SELMIC = VX_MIC0,
423 VX_COMPOT = VX_MIC1,
424 VX_SCOMPR = VX_MIC2,
425 VX_GLIMIT = VX_MIC3,
426 VX_INTCSR = VX_PLX0,
427 VX_CNTRL = VX_PLX1,
428 VX_GPIOC = VX_PLX2,
429
430 /* aliases for VXPOCKET board */
431 VX_MICRO = VX_MEMIRQ,
432 VX_CODEC2 = VX_MEMIRQ,
433 VX_DIALOG = VX_ACQ,
434
435};
436
437/* RMH status type */
438enum {
439 RMH_SSIZE_FIXED = 0, /* status size given by the driver (in LgStat) */
440 RMH_SSIZE_ARG = 1, /* status size given in the LSB byte */
441 RMH_SSIZE_MASK = 2, /* status size given in bitmask */
442};
443
444
445/* bits for ICR register */
446#define ICR_HF1 0x10
447#define ICR_HF0 0x08
448#define ICR_TREQ 0x02 /* Interrupt mode + HREQ set on for transfer (->DSP) request */
449#define ICR_RREQ 0x01 /* Interrupt mode + RREQ set on for transfer (->PC) request */
450
451/* bits for CVR register */
452#define CVR_HC 0x80
453
454/* bits for ISR register */
455#define ISR_HF3 0x10
456#define ISR_HF2 0x08
457#define ISR_CHK 0x10
458#define ISR_ERR 0x08
459#define ISR_TX_READY 0x04
460#define ISR_TX_EMPTY 0x02
461#define ISR_RX_FULL 0x01
462
463/* Constants used to access the DATA register */
464#define VX_DATA_CODEC_MASK 0x80
465#define VX_DATA_XICOR_MASK 0x80
466
467/* Constants used to access the CSUER register (both for VX2 and VXP) */
468#define VX_SUER_FREQ_MASK 0x0c
469#define VX_SUER_FREQ_32KHz_MASK 0x0c
470#define VX_SUER_FREQ_44KHz_MASK 0x00
471#define VX_SUER_FREQ_48KHz_MASK 0x04
472#define VX_SUER_DATA_PRESENT_MASK 0x02
473#define VX_SUER_CLOCK_PRESENT_MASK 0x01
474
475#define VX_CUER_HH_BITC_SEL_MASK 0x08
476#define VX_CUER_MH_BITC_SEL_MASK 0x04
477#define VX_CUER_ML_BITC_SEL_MASK 0x02
478#define VX_CUER_LL_BITC_SEL_MASK 0x01
479
480#define XX_UER_CBITS_OFFSET_MASK 0x1f
481
482
483/* bits for audio_info */
484#define VX_AUDIO_INFO_REAL_TIME (1<<0) /* real-time processing available */
485#define VX_AUDIO_INFO_OFFLINE (1<<1) /* offline processing available */
486#define VX_AUDIO_INFO_MPEG1 (1<<5)
487#define VX_AUDIO_INFO_MPEG2 (1<<6)
488#define VX_AUDIO_INFO_LINEAR_8 (1<<7)
489#define VX_AUDIO_INFO_LINEAR_16 (1<<8)
490#define VX_AUDIO_INFO_LINEAR_24 (1<<9)
491
492/* DSP Interrupt Request values */
493#define VXP_IRQ_OFFSET 0x40 /* add 0x40 offset for vxpocket and vx222/v2 */
494/* call with vx_send_irq_dsp() */
495#define IRQ_MESS_WRITE_END 0x30
496#define IRQ_MESS_WRITE_NEXT 0x32
497#define IRQ_MESS_READ_NEXT 0x34
498#define IRQ_MESS_READ_END 0x36
499#define IRQ_MESSAGE 0x38
500#define IRQ_RESET_CHK 0x3A
501#define IRQ_CONNECT_STREAM_NEXT 0x26
502#define IRQ_CONNECT_STREAM_END 0x28
503#define IRQ_PAUSE_START_CONNECT 0x2A
504#define IRQ_END_CONNECTION 0x2C
505
506/* Is there async. events pending ( IT Source Test ) */
507#define ASYNC_EVENTS_PENDING 0x008000
508#define HBUFFER_EVENTS_PENDING 0x004000 // Not always accurate
509#define NOTIF_EVENTS_PENDING 0x002000
510#define TIME_CODE_EVENT_PENDING 0x001000
511#define FREQUENCY_CHANGE_EVENT_PENDING 0x000800
512#define END_OF_BUFFER_EVENTS_PENDING 0x000400
513#define FATAL_DSP_ERROR 0xff0000
514
515/* Stream Format Header Defines */
516#define HEADER_FMT_BASE 0xFED00000
517#define HEADER_FMT_MONO 0x000000C0
518#define HEADER_FMT_INTEL 0x00008000
519#define HEADER_FMT_16BITS 0x00002000
520#define HEADER_FMT_24BITS 0x00004000
521#define HEADER_FMT_UPTO11 0x00000200 /* frequency is less or equ. to 11k.*/
522#define HEADER_FMT_UPTO32 0x00000100 /* frequency is over 11k and less then 32k.*/
523
524/* Constants used to access the Codec */
525#define XX_CODEC_SELECTOR 0x20
526/* codec commands */
527#define XX_CODEC_ADC_CONTROL_REGISTER 0x01
528#define XX_CODEC_DAC_CONTROL_REGISTER 0x02
529#define XX_CODEC_LEVEL_LEFT_REGISTER 0x03
530#define XX_CODEC_LEVEL_RIGHT_REGISTER 0x04
531#define XX_CODEC_PORT_MODE_REGISTER 0x05
532#define XX_CODEC_STATUS_REPORT_REGISTER 0x06
533#define XX_CODEC_CLOCK_CONTROL_REGISTER 0x07
534
535/*
536 * Audio-level control values
537 */
538#define CVAL_M110DB 0x000 /* -110dB */
539#define CVAL_M99DB 0x02C
540#define CVAL_M21DB 0x163
541#define CVAL_M18DB 0x16F
542#define CVAL_M10DB 0x18F
543#define CVAL_0DB 0x1B7
544#define CVAL_18DB 0x1FF /* +18dB */
545#define CVAL_MAX 0x1FF
546
547#define AUDIO_IO_HAS_MUTE_LEVEL 0x400000
548#define AUDIO_IO_HAS_MUTE_MONITORING_1 0x200000
549#define AUDIO_IO_HAS_MUTE_MONITORING_2 0x100000
550#define VALID_AUDIO_IO_DIGITAL_LEVEL 0x01
551#define VALID_AUDIO_IO_MONITORING_LEVEL 0x02
552#define VALID_AUDIO_IO_MUTE_LEVEL 0x04
553#define VALID_AUDIO_IO_MUTE_MONITORING_1 0x08
554#define VALID_AUDIO_IO_MUTE_MONITORING_2 0x10
555
556
557#endif /* __SOUND_VX_COMMON_H */
1/* SPDX-License-Identifier: GPL-2.0-or-later */
2/*
3 * Driver for Digigram VX soundcards
4 *
5 * Hardware core part
6 *
7 * Copyright (c) 2002 by Takashi Iwai <tiwai@suse.de>
8 */
9
10#ifndef __SOUND_VX_COMMON_H
11#define __SOUND_VX_COMMON_H
12
13#include <sound/pcm.h>
14#include <sound/hwdep.h>
15#include <linux/interrupt.h>
16
17struct firmware;
18struct device;
19
20#define VX_DRIVER_VERSION 0x010000 /* 1.0.0 */
21
22/*
23 */
24#define SIZE_MAX_CMD 0x10
25#define SIZE_MAX_STATUS 0x10
26
27struct vx_rmh {
28 u16 LgCmd; /* length of the command to send (WORDs) */
29 u16 LgStat; /* length of the status received (WORDs) */
30 u32 Cmd[SIZE_MAX_CMD];
31 u32 Stat[SIZE_MAX_STATUS];
32 u16 DspStat; /* status type, RMP_SSIZE_XXX */
33};
34
35typedef u64 pcx_time_t;
36
37#define VX_MAX_PIPES 16
38#define VX_MAX_PERIODS 32
39#define VX_MAX_CODECS 2
40
41struct vx_ibl_info {
42 int size; /* the current IBL size (0 = query) in bytes */
43 int max_size; /* max. IBL size in bytes */
44 int min_size; /* min. IBL size in bytes */
45 int granularity; /* granularity */
46};
47
48struct vx_pipe {
49 int number;
50 unsigned int is_capture: 1;
51 unsigned int data_mode: 1;
52 unsigned int running: 1;
53 unsigned int prepared: 1;
54 int channels;
55 unsigned int differed_type;
56 pcx_time_t pcx_time;
57 struct snd_pcm_substream *substream;
58
59 int hbuf_size; /* H-buffer size in bytes */
60 int buffer_bytes; /* the ALSA pcm buffer size in bytes */
61 int period_bytes; /* the ALSA pcm period size in bytes */
62 int hw_ptr; /* the current hardware pointer in bytes */
63 int position; /* the current position in frames (playback only) */
64 int transferred; /* the transferred size (per period) in frames */
65 int align; /* size of alignment */
66 u64 cur_count; /* current sample position (for playback) */
67
68 unsigned int references; /* an output pipe may be used for monitoring and/or playback */
69 struct vx_pipe *monitoring_pipe; /* pointer to the monitoring pipe (capture pipe only)*/
70};
71
72struct vx_core;
73
74struct snd_vx_ops {
75 /* low-level i/o */
76 unsigned char (*in8)(struct vx_core *chip, int reg);
77 unsigned int (*in32)(struct vx_core *chip, int reg);
78 void (*out8)(struct vx_core *chip, int reg, unsigned char val);
79 void (*out32)(struct vx_core *chip, int reg, unsigned int val);
80 /* irq */
81 int (*test_and_ack)(struct vx_core *chip);
82 void (*validate_irq)(struct vx_core *chip, int enable);
83 /* codec */
84 void (*write_codec)(struct vx_core *chip, int codec, unsigned int data);
85 void (*akm_write)(struct vx_core *chip, int reg, unsigned int data);
86 void (*reset_codec)(struct vx_core *chip);
87 void (*change_audio_source)(struct vx_core *chip, int src);
88 void (*set_clock_source)(struct vx_core *chp, int src);
89 /* chip init */
90 int (*load_dsp)(struct vx_core *chip, int idx, const struct firmware *fw);
91 void (*reset_dsp)(struct vx_core *chip);
92 void (*reset_board)(struct vx_core *chip, int cold_reset);
93 int (*add_controls)(struct vx_core *chip);
94 /* pcm */
95 void (*dma_write)(struct vx_core *chip, struct snd_pcm_runtime *runtime,
96 struct vx_pipe *pipe, int count);
97 void (*dma_read)(struct vx_core *chip, struct snd_pcm_runtime *runtime,
98 struct vx_pipe *pipe, int count);
99};
100
101struct snd_vx_hardware {
102 const char *name;
103 int type; /* VX_TYPE_XXX */
104
105 /* hardware specs */
106 unsigned int num_codecs;
107 unsigned int num_ins;
108 unsigned int num_outs;
109 unsigned int output_level_max;
110 const unsigned int *output_level_db_scale;
111};
112
113/* hwdep id string */
114#define SND_VX_HWDEP_ID "VX Loader"
115
116/* hardware type */
117enum {
118 /* VX222 PCI */
119 VX_TYPE_BOARD, /* old VX222 PCI */
120 VX_TYPE_V2, /* VX222 V2 PCI */
121 VX_TYPE_MIC, /* VX222 Mic PCI */
122 /* VX-pocket */
123 VX_TYPE_VXPOCKET, /* VXpocket V2 */
124 VX_TYPE_VXP440, /* VXpocket 440 */
125 VX_TYPE_NUMS
126};
127
128/* chip status */
129enum {
130 VX_STAT_XILINX_LOADED = (1 << 0), /* devices are registered */
131 VX_STAT_DEVICE_INIT = (1 << 1), /* devices are registered */
132 VX_STAT_CHIP_INIT = (1 << 2), /* all operational */
133 VX_STAT_IN_SUSPEND = (1 << 10), /* in suspend phase */
134 VX_STAT_IS_STALE = (1 << 15) /* device is stale */
135};
136
137/* min/max values for analog output for old codecs */
138#define VX_ANALOG_OUT_LEVEL_MAX 0xe3
139
140struct vx_core {
141 /* ALSA stuff */
142 struct snd_card *card;
143 struct snd_pcm *pcm[VX_MAX_CODECS];
144 int type; /* VX_TYPE_XXX */
145
146 int irq;
147 /* ports are defined externally */
148
149 /* low-level functions */
150 struct snd_vx_hardware *hw;
151 struct snd_vx_ops *ops;
152
153 struct mutex lock;
154
155 unsigned int chip_status;
156 unsigned int pcm_running;
157
158 struct device *dev;
159 struct snd_hwdep *hwdep;
160
161 struct vx_rmh irq_rmh; /* RMH used in interrupts */
162
163 unsigned int audio_info; /* see VX_AUDIO_INFO */
164 unsigned int audio_ins;
165 unsigned int audio_outs;
166 struct vx_pipe **playback_pipes;
167 struct vx_pipe **capture_pipes;
168
169 /* clock and audio sources */
170 unsigned int audio_source; /* current audio input source */
171 unsigned int audio_source_target;
172 unsigned int clock_mode; /* clock mode (VX_CLOCK_MODE_XXX) */
173 unsigned int clock_source; /* current clock source (INTERNAL_QUARTZ or UER_SYNC) */
174 unsigned int freq; /* current frequency */
175 unsigned int freq_detected; /* detected frequency from digital in */
176 unsigned int uer_detected; /* VX_UER_MODE_XXX */
177 unsigned int uer_bits; /* IEC958 status bits */
178 struct vx_ibl_info ibl; /* IBL information */
179
180 /* mixer setting */
181 int output_level[VX_MAX_CODECS][2]; /* analog output level */
182 int audio_gain[2][4]; /* digital audio level (playback/capture) */
183 unsigned char audio_active[4]; /* mute/unmute on digital playback */
184 int audio_monitor[4]; /* playback hw-monitor level */
185 unsigned char audio_monitor_active[4]; /* playback hw-monitor mute/unmute */
186
187 struct mutex mixer_mutex;
188
189 const struct firmware *firmware[4]; /* loaded firmware data */
190};
191
192
193/*
194 * constructor
195 */
196struct vx_core *snd_vx_create(struct snd_card *card, struct snd_vx_hardware *hw,
197 struct snd_vx_ops *ops, int extra_size);
198int snd_vx_setup_firmware(struct vx_core *chip);
199int snd_vx_load_boot_image(struct vx_core *chip, const struct firmware *dsp);
200int snd_vx_dsp_boot(struct vx_core *chip, const struct firmware *dsp);
201int snd_vx_dsp_load(struct vx_core *chip, const struct firmware *dsp);
202
203void snd_vx_free_firmware(struct vx_core *chip);
204
205/*
206 * interrupt handler; exported for pcmcia
207 */
208irqreturn_t snd_vx_irq_handler(int irq, void *dev);
209irqreturn_t snd_vx_threaded_irq_handler(int irq, void *dev);
210
211/*
212 * lowlevel functions
213 */
214static inline int vx_test_and_ack(struct vx_core *chip)
215{
216 return chip->ops->test_and_ack(chip);
217}
218
219static inline void vx_validate_irq(struct vx_core *chip, int enable)
220{
221 chip->ops->validate_irq(chip, enable);
222}
223
224static inline unsigned char snd_vx_inb(struct vx_core *chip, int reg)
225{
226 return chip->ops->in8(chip, reg);
227}
228
229static inline unsigned int snd_vx_inl(struct vx_core *chip, int reg)
230{
231 return chip->ops->in32(chip, reg);
232}
233
234static inline void snd_vx_outb(struct vx_core *chip, int reg, unsigned char val)
235{
236 chip->ops->out8(chip, reg, val);
237}
238
239static inline void snd_vx_outl(struct vx_core *chip, int reg, unsigned int val)
240{
241 chip->ops->out32(chip, reg, val);
242}
243
244#define vx_inb(chip,reg) snd_vx_inb(chip, VX_##reg)
245#define vx_outb(chip,reg,val) snd_vx_outb(chip, VX_##reg,val)
246#define vx_inl(chip,reg) snd_vx_inl(chip, VX_##reg)
247#define vx_outl(chip,reg,val) snd_vx_outl(chip, VX_##reg,val)
248
249static inline void vx_reset_dsp(struct vx_core *chip)
250{
251 chip->ops->reset_dsp(chip);
252}
253
254int vx_send_msg(struct vx_core *chip, struct vx_rmh *rmh);
255int vx_send_msg_nolock(struct vx_core *chip, struct vx_rmh *rmh);
256int vx_send_rih(struct vx_core *chip, int cmd);
257int vx_send_rih_nolock(struct vx_core *chip, int cmd);
258
259void vx_reset_codec(struct vx_core *chip, int cold_reset);
260
261/*
262 * check the bit on the specified register
263 * returns zero if a bit matches, or a negative error code.
264 * exported for vxpocket driver
265 */
266int snd_vx_check_reg_bit(struct vx_core *chip, int reg, int mask, int bit, int time);
267#define vx_check_isr(chip,mask,bit,time) snd_vx_check_reg_bit(chip, VX_ISR, mask, bit, time)
268#define vx_wait_isr_bit(chip,bit) vx_check_isr(chip, bit, bit, 200)
269#define vx_wait_for_rx_full(chip) vx_wait_isr_bit(chip, ISR_RX_FULL)
270
271
272/*
273 * pseudo-DMA transfer
274 */
275static inline void vx_pseudo_dma_write(struct vx_core *chip, struct snd_pcm_runtime *runtime,
276 struct vx_pipe *pipe, int count)
277{
278 chip->ops->dma_write(chip, runtime, pipe, count);
279}
280
281static inline void vx_pseudo_dma_read(struct vx_core *chip, struct snd_pcm_runtime *runtime,
282 struct vx_pipe *pipe, int count)
283{
284 chip->ops->dma_read(chip, runtime, pipe, count);
285}
286
287
288
289/* error with hardware code,
290 * the return value is -(VX_ERR_MASK | actual-hw-error-code)
291 */
292#define VX_ERR_MASK 0x1000000
293#define vx_get_error(err) (-(err) & ~VX_ERR_MASK)
294
295
296/*
297 * pcm stuff
298 */
299int snd_vx_pcm_new(struct vx_core *chip);
300void vx_pcm_update_intr(struct vx_core *chip, unsigned int events);
301
302/*
303 * mixer stuff
304 */
305int snd_vx_mixer_new(struct vx_core *chip);
306void vx_toggle_dac_mute(struct vx_core *chip, int mute);
307int vx_sync_audio_source(struct vx_core *chip);
308int vx_set_monitor_level(struct vx_core *chip, int audio, int level, int active);
309
310/*
311 * IEC958 & clock stuff
312 */
313void vx_set_iec958_status(struct vx_core *chip, unsigned int bits);
314int vx_set_clock(struct vx_core *chip, unsigned int freq);
315void vx_set_internal_clock(struct vx_core *chip, unsigned int freq);
316int vx_change_frequency(struct vx_core *chip);
317
318
319/*
320 * PM
321 */
322int snd_vx_suspend(struct vx_core *card);
323int snd_vx_resume(struct vx_core *card);
324
325/*
326 * hardware constants
327 */
328
329#define vx_has_new_dsp(chip) ((chip)->type != VX_TYPE_BOARD)
330#define vx_is_pcmcia(chip) ((chip)->type >= VX_TYPE_VXPOCKET)
331
332/* audio input source */
333enum {
334 VX_AUDIO_SRC_DIGITAL,
335 VX_AUDIO_SRC_LINE,
336 VX_AUDIO_SRC_MIC
337};
338
339/* clock source */
340enum {
341 INTERNAL_QUARTZ,
342 UER_SYNC
343};
344
345/* clock mode */
346enum {
347 VX_CLOCK_MODE_AUTO, /* depending on the current audio source */
348 VX_CLOCK_MODE_INTERNAL, /* fixed to internal quartz */
349 VX_CLOCK_MODE_EXTERNAL /* fixed to UER sync */
350};
351
352/* SPDIF/UER type */
353enum {
354 VX_UER_MODE_CONSUMER,
355 VX_UER_MODE_PROFESSIONAL,
356 VX_UER_MODE_NOT_PRESENT,
357};
358
359/* register indices */
360enum {
361 VX_ICR,
362 VX_CVR,
363 VX_ISR,
364 VX_IVR,
365 VX_RXH,
366 VX_TXH = VX_RXH,
367 VX_RXM,
368 VX_TXM = VX_RXM,
369 VX_RXL,
370 VX_TXL = VX_RXL,
371 VX_DMA,
372 VX_CDSP,
373 VX_RFREQ,
374 VX_RUER_V2,
375 VX_GAIN,
376 VX_DATA = VX_GAIN,
377 VX_MEMIRQ,
378 VX_ACQ,
379 VX_BIT0,
380 VX_BIT1,
381 VX_MIC0,
382 VX_MIC1,
383 VX_MIC2,
384 VX_MIC3,
385 VX_PLX0,
386 VX_PLX1,
387 VX_PLX2,
388
389 VX_LOFREQ, // V2: ACQ, VP: RFREQ
390 VX_HIFREQ, // V2: BIT0, VP: RUER_V2
391 VX_CSUER, // V2: BIT1, VP: BIT0
392 VX_RUER, // V2: RUER_V2, VP: BIT1
393
394 VX_REG_MAX,
395
396 /* aliases for VX board */
397 VX_RESET_DMA = VX_ISR,
398 VX_CFG = VX_RFREQ,
399 VX_STATUS = VX_MEMIRQ,
400 VX_SELMIC = VX_MIC0,
401 VX_COMPOT = VX_MIC1,
402 VX_SCOMPR = VX_MIC2,
403 VX_GLIMIT = VX_MIC3,
404 VX_INTCSR = VX_PLX0,
405 VX_CNTRL = VX_PLX1,
406 VX_GPIOC = VX_PLX2,
407
408 /* aliases for VXPOCKET board */
409 VX_MICRO = VX_MEMIRQ,
410 VX_CODEC2 = VX_MEMIRQ,
411 VX_DIALOG = VX_ACQ,
412
413};
414
415/* RMH status type */
416enum {
417 RMH_SSIZE_FIXED = 0, /* status size given by the driver (in LgStat) */
418 RMH_SSIZE_ARG = 1, /* status size given in the LSB byte */
419 RMH_SSIZE_MASK = 2, /* status size given in bitmask */
420};
421
422
423/* bits for ICR register */
424#define ICR_HF1 0x10
425#define ICR_HF0 0x08
426#define ICR_TREQ 0x02 /* Interrupt mode + HREQ set on for transfer (->DSP) request */
427#define ICR_RREQ 0x01 /* Interrupt mode + RREQ set on for transfer (->PC) request */
428
429/* bits for CVR register */
430#define CVR_HC 0x80
431
432/* bits for ISR register */
433#define ISR_HF3 0x10
434#define ISR_HF2 0x08
435#define ISR_CHK 0x10
436#define ISR_ERR 0x08
437#define ISR_TX_READY 0x04
438#define ISR_TX_EMPTY 0x02
439#define ISR_RX_FULL 0x01
440
441/* Constants used to access the DATA register */
442#define VX_DATA_CODEC_MASK 0x80
443#define VX_DATA_XICOR_MASK 0x80
444
445/* Constants used to access the CSUER register (both for VX2 and VXP) */
446#define VX_SUER_FREQ_MASK 0x0c
447#define VX_SUER_FREQ_32KHz_MASK 0x0c
448#define VX_SUER_FREQ_44KHz_MASK 0x00
449#define VX_SUER_FREQ_48KHz_MASK 0x04
450#define VX_SUER_DATA_PRESENT_MASK 0x02
451#define VX_SUER_CLOCK_PRESENT_MASK 0x01
452
453#define VX_CUER_HH_BITC_SEL_MASK 0x08
454#define VX_CUER_MH_BITC_SEL_MASK 0x04
455#define VX_CUER_ML_BITC_SEL_MASK 0x02
456#define VX_CUER_LL_BITC_SEL_MASK 0x01
457
458#define XX_UER_CBITS_OFFSET_MASK 0x1f
459
460
461/* bits for audio_info */
462#define VX_AUDIO_INFO_REAL_TIME (1<<0) /* real-time processing available */
463#define VX_AUDIO_INFO_OFFLINE (1<<1) /* offline processing available */
464#define VX_AUDIO_INFO_MPEG1 (1<<5)
465#define VX_AUDIO_INFO_MPEG2 (1<<6)
466#define VX_AUDIO_INFO_LINEAR_8 (1<<7)
467#define VX_AUDIO_INFO_LINEAR_16 (1<<8)
468#define VX_AUDIO_INFO_LINEAR_24 (1<<9)
469
470/* DSP Interrupt Request values */
471#define VXP_IRQ_OFFSET 0x40 /* add 0x40 offset for vxpocket and vx222/v2 */
472/* call with vx_send_irq_dsp() */
473#define IRQ_MESS_WRITE_END 0x30
474#define IRQ_MESS_WRITE_NEXT 0x32
475#define IRQ_MESS_READ_NEXT 0x34
476#define IRQ_MESS_READ_END 0x36
477#define IRQ_MESSAGE 0x38
478#define IRQ_RESET_CHK 0x3A
479#define IRQ_CONNECT_STREAM_NEXT 0x26
480#define IRQ_CONNECT_STREAM_END 0x28
481#define IRQ_PAUSE_START_CONNECT 0x2A
482#define IRQ_END_CONNECTION 0x2C
483
484/* Is there async. events pending ( IT Source Test ) */
485#define ASYNC_EVENTS_PENDING 0x008000
486#define HBUFFER_EVENTS_PENDING 0x004000 // Not always accurate
487#define NOTIF_EVENTS_PENDING 0x002000
488#define TIME_CODE_EVENT_PENDING 0x001000
489#define FREQUENCY_CHANGE_EVENT_PENDING 0x000800
490#define END_OF_BUFFER_EVENTS_PENDING 0x000400
491#define FATAL_DSP_ERROR 0xff0000
492
493/* Stream Format Header Defines */
494#define HEADER_FMT_BASE 0xFED00000
495#define HEADER_FMT_MONO 0x000000C0
496#define HEADER_FMT_INTEL 0x00008000
497#define HEADER_FMT_16BITS 0x00002000
498#define HEADER_FMT_24BITS 0x00004000
499#define HEADER_FMT_UPTO11 0x00000200 /* frequency is less or equ. to 11k.*/
500#define HEADER_FMT_UPTO32 0x00000100 /* frequency is over 11k and less then 32k.*/
501
502/* Constants used to access the Codec */
503#define XX_CODEC_SELECTOR 0x20
504/* codec commands */
505#define XX_CODEC_ADC_CONTROL_REGISTER 0x01
506#define XX_CODEC_DAC_CONTROL_REGISTER 0x02
507#define XX_CODEC_LEVEL_LEFT_REGISTER 0x03
508#define XX_CODEC_LEVEL_RIGHT_REGISTER 0x04
509#define XX_CODEC_PORT_MODE_REGISTER 0x05
510#define XX_CODEC_STATUS_REPORT_REGISTER 0x06
511#define XX_CODEC_CLOCK_CONTROL_REGISTER 0x07
512
513/*
514 * Audio-level control values
515 */
516#define CVAL_M110DB 0x000 /* -110dB */
517#define CVAL_M99DB 0x02C
518#define CVAL_M21DB 0x163
519#define CVAL_M18DB 0x16F
520#define CVAL_M10DB 0x18F
521#define CVAL_0DB 0x1B7
522#define CVAL_18DB 0x1FF /* +18dB */
523#define CVAL_MAX 0x1FF
524
525#define AUDIO_IO_HAS_MUTE_LEVEL 0x400000
526#define AUDIO_IO_HAS_MUTE_MONITORING_1 0x200000
527#define AUDIO_IO_HAS_MUTE_MONITORING_2 0x100000
528#define VALID_AUDIO_IO_DIGITAL_LEVEL 0x01
529#define VALID_AUDIO_IO_MONITORING_LEVEL 0x02
530#define VALID_AUDIO_IO_MUTE_LEVEL 0x04
531#define VALID_AUDIO_IO_MUTE_MONITORING_1 0x08
532#define VALID_AUDIO_IO_MUTE_MONITORING_2 0x10
533
534
535#endif /* __SOUND_VX_COMMON_H */