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1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (C) STMicroelectronics 2018 - All Rights Reserved
4 * Author: Ludovic Barre <ludovic.barre@st.com> for STMicroelectronics.
5 */
6#include <linux/bitfield.h>
7#include <linux/clk.h>
8#include <linux/dmaengine.h>
9#include <linux/dma-mapping.h>
10#include <linux/errno.h>
11#include <linux/io.h>
12#include <linux/iopoll.h>
13#include <linux/interrupt.h>
14#include <linux/module.h>
15#include <linux/mutex.h>
16#include <linux/of.h>
17#include <linux/of_device.h>
18#include <linux/pinctrl/consumer.h>
19#include <linux/platform_device.h>
20#include <linux/reset.h>
21#include <linux/sizes.h>
22#include <linux/spi/spi-mem.h>
23
24#define QSPI_CR 0x00
25#define CR_EN BIT(0)
26#define CR_ABORT BIT(1)
27#define CR_DMAEN BIT(2)
28#define CR_TCEN BIT(3)
29#define CR_SSHIFT BIT(4)
30#define CR_DFM BIT(6)
31#define CR_FSEL BIT(7)
32#define CR_FTHRES_SHIFT 8
33#define CR_TEIE BIT(16)
34#define CR_TCIE BIT(17)
35#define CR_FTIE BIT(18)
36#define CR_SMIE BIT(19)
37#define CR_TOIE BIT(20)
38#define CR_PRESC_MASK GENMASK(31, 24)
39
40#define QSPI_DCR 0x04
41#define DCR_FSIZE_MASK GENMASK(20, 16)
42
43#define QSPI_SR 0x08
44#define SR_TEF BIT(0)
45#define SR_TCF BIT(1)
46#define SR_FTF BIT(2)
47#define SR_SMF BIT(3)
48#define SR_TOF BIT(4)
49#define SR_BUSY BIT(5)
50#define SR_FLEVEL_MASK GENMASK(13, 8)
51
52#define QSPI_FCR 0x0c
53#define FCR_CTEF BIT(0)
54#define FCR_CTCF BIT(1)
55
56#define QSPI_DLR 0x10
57
58#define QSPI_CCR 0x14
59#define CCR_INST_MASK GENMASK(7, 0)
60#define CCR_IMODE_MASK GENMASK(9, 8)
61#define CCR_ADMODE_MASK GENMASK(11, 10)
62#define CCR_ADSIZE_MASK GENMASK(13, 12)
63#define CCR_DCYC_MASK GENMASK(22, 18)
64#define CCR_DMODE_MASK GENMASK(25, 24)
65#define CCR_FMODE_MASK GENMASK(27, 26)
66#define CCR_FMODE_INDW (0U << 26)
67#define CCR_FMODE_INDR (1U << 26)
68#define CCR_FMODE_APM (2U << 26)
69#define CCR_FMODE_MM (3U << 26)
70#define CCR_BUSWIDTH_0 0x0
71#define CCR_BUSWIDTH_1 0x1
72#define CCR_BUSWIDTH_2 0x2
73#define CCR_BUSWIDTH_4 0x3
74
75#define QSPI_AR 0x18
76#define QSPI_ABR 0x1c
77#define QSPI_DR 0x20
78#define QSPI_PSMKR 0x24
79#define QSPI_PSMAR 0x28
80#define QSPI_PIR 0x2c
81#define QSPI_LPTR 0x30
82
83#define STM32_QSPI_MAX_MMAP_SZ SZ_256M
84#define STM32_QSPI_MAX_NORCHIP 2
85
86#define STM32_FIFO_TIMEOUT_US 30000
87#define STM32_BUSY_TIMEOUT_US 100000
88#define STM32_ABT_TIMEOUT_US 100000
89#define STM32_COMP_TIMEOUT_MS 1000
90
91struct stm32_qspi_flash {
92 struct stm32_qspi *qspi;
93 u32 cs;
94 u32 presc;
95};
96
97struct stm32_qspi {
98 struct device *dev;
99 struct spi_controller *ctrl;
100 phys_addr_t phys_base;
101 void __iomem *io_base;
102 void __iomem *mm_base;
103 resource_size_t mm_size;
104 struct clk *clk;
105 u32 clk_rate;
106 struct stm32_qspi_flash flash[STM32_QSPI_MAX_NORCHIP];
107 struct completion data_completion;
108 u32 fmode;
109
110 struct dma_chan *dma_chtx;
111 struct dma_chan *dma_chrx;
112 struct completion dma_completion;
113
114 u32 cr_reg;
115 u32 dcr_reg;
116
117 /*
118 * to protect device configuration, could be different between
119 * 2 flash access (bk1, bk2)
120 */
121 struct mutex lock;
122};
123
124static irqreturn_t stm32_qspi_irq(int irq, void *dev_id)
125{
126 struct stm32_qspi *qspi = (struct stm32_qspi *)dev_id;
127 u32 cr, sr;
128
129 sr = readl_relaxed(qspi->io_base + QSPI_SR);
130
131 if (sr & (SR_TEF | SR_TCF)) {
132 /* disable irq */
133 cr = readl_relaxed(qspi->io_base + QSPI_CR);
134 cr &= ~CR_TCIE & ~CR_TEIE;
135 writel_relaxed(cr, qspi->io_base + QSPI_CR);
136 complete(&qspi->data_completion);
137 }
138
139 return IRQ_HANDLED;
140}
141
142static void stm32_qspi_read_fifo(u8 *val, void __iomem *addr)
143{
144 *val = readb_relaxed(addr);
145}
146
147static void stm32_qspi_write_fifo(u8 *val, void __iomem *addr)
148{
149 writeb_relaxed(*val, addr);
150}
151
152static int stm32_qspi_tx_poll(struct stm32_qspi *qspi,
153 const struct spi_mem_op *op)
154{
155 void (*tx_fifo)(u8 *val, void __iomem *addr);
156 u32 len = op->data.nbytes, sr;
157 u8 *buf;
158 int ret;
159
160 if (op->data.dir == SPI_MEM_DATA_IN) {
161 tx_fifo = stm32_qspi_read_fifo;
162 buf = op->data.buf.in;
163
164 } else {
165 tx_fifo = stm32_qspi_write_fifo;
166 buf = (u8 *)op->data.buf.out;
167 }
168
169 while (len--) {
170 ret = readl_relaxed_poll_timeout_atomic(qspi->io_base + QSPI_SR,
171 sr, (sr & SR_FTF), 1,
172 STM32_FIFO_TIMEOUT_US);
173 if (ret) {
174 dev_err(qspi->dev, "fifo timeout (len:%d stat:%#x)\n",
175 len, sr);
176 return ret;
177 }
178 tx_fifo(buf++, qspi->io_base + QSPI_DR);
179 }
180
181 return 0;
182}
183
184static int stm32_qspi_tx_mm(struct stm32_qspi *qspi,
185 const struct spi_mem_op *op)
186{
187 memcpy_fromio(op->data.buf.in, qspi->mm_base + op->addr.val,
188 op->data.nbytes);
189 return 0;
190}
191
192static void stm32_qspi_dma_callback(void *arg)
193{
194 struct completion *dma_completion = arg;
195
196 complete(dma_completion);
197}
198
199static int stm32_qspi_tx_dma(struct stm32_qspi *qspi,
200 const struct spi_mem_op *op)
201{
202 struct dma_async_tx_descriptor *desc;
203 enum dma_transfer_direction dma_dir;
204 struct dma_chan *dma_ch;
205 struct sg_table sgt;
206 dma_cookie_t cookie;
207 u32 cr, t_out;
208 int err;
209
210 if (op->data.dir == SPI_MEM_DATA_IN) {
211 dma_dir = DMA_DEV_TO_MEM;
212 dma_ch = qspi->dma_chrx;
213 } else {
214 dma_dir = DMA_MEM_TO_DEV;
215 dma_ch = qspi->dma_chtx;
216 }
217
218 /*
219 * spi_map_buf return -EINVAL if the buffer is not DMA-able
220 * (DMA-able: in vmalloc | kmap | virt_addr_valid)
221 */
222 err = spi_controller_dma_map_mem_op_data(qspi->ctrl, op, &sgt);
223 if (err)
224 return err;
225
226 desc = dmaengine_prep_slave_sg(dma_ch, sgt.sgl, sgt.nents,
227 dma_dir, DMA_PREP_INTERRUPT);
228 if (!desc) {
229 err = -ENOMEM;
230 goto out_unmap;
231 }
232
233 cr = readl_relaxed(qspi->io_base + QSPI_CR);
234
235 reinit_completion(&qspi->dma_completion);
236 desc->callback = stm32_qspi_dma_callback;
237 desc->callback_param = &qspi->dma_completion;
238 cookie = dmaengine_submit(desc);
239 err = dma_submit_error(cookie);
240 if (err)
241 goto out;
242
243 dma_async_issue_pending(dma_ch);
244
245 writel_relaxed(cr | CR_DMAEN, qspi->io_base + QSPI_CR);
246
247 t_out = sgt.nents * STM32_COMP_TIMEOUT_MS;
248 if (!wait_for_completion_timeout(&qspi->dma_completion,
249 msecs_to_jiffies(t_out)))
250 err = -ETIMEDOUT;
251
252 if (err)
253 dmaengine_terminate_all(dma_ch);
254
255out:
256 writel_relaxed(cr & ~CR_DMAEN, qspi->io_base + QSPI_CR);
257out_unmap:
258 spi_controller_dma_unmap_mem_op_data(qspi->ctrl, op, &sgt);
259
260 return err;
261}
262
263static int stm32_qspi_tx(struct stm32_qspi *qspi, const struct spi_mem_op *op)
264{
265 if (!op->data.nbytes)
266 return 0;
267
268 if (qspi->fmode == CCR_FMODE_MM)
269 return stm32_qspi_tx_mm(qspi, op);
270 else if ((op->data.dir == SPI_MEM_DATA_IN && qspi->dma_chrx) ||
271 (op->data.dir == SPI_MEM_DATA_OUT && qspi->dma_chtx))
272 if (!stm32_qspi_tx_dma(qspi, op))
273 return 0;
274
275 return stm32_qspi_tx_poll(qspi, op);
276}
277
278static int stm32_qspi_wait_nobusy(struct stm32_qspi *qspi)
279{
280 u32 sr;
281
282 return readl_relaxed_poll_timeout_atomic(qspi->io_base + QSPI_SR, sr,
283 !(sr & SR_BUSY), 1,
284 STM32_BUSY_TIMEOUT_US);
285}
286
287static int stm32_qspi_wait_cmd(struct stm32_qspi *qspi,
288 const struct spi_mem_op *op)
289{
290 u32 cr, sr;
291 int err = 0;
292
293 if (!op->data.nbytes)
294 return stm32_qspi_wait_nobusy(qspi);
295
296 if (readl_relaxed(qspi->io_base + QSPI_SR) & SR_TCF)
297 goto out;
298
299 reinit_completion(&qspi->data_completion);
300 cr = readl_relaxed(qspi->io_base + QSPI_CR);
301 writel_relaxed(cr | CR_TCIE | CR_TEIE, qspi->io_base + QSPI_CR);
302
303 if (!wait_for_completion_timeout(&qspi->data_completion,
304 msecs_to_jiffies(STM32_COMP_TIMEOUT_MS))) {
305 err = -ETIMEDOUT;
306 } else {
307 sr = readl_relaxed(qspi->io_base + QSPI_SR);
308 if (sr & SR_TEF)
309 err = -EIO;
310 }
311
312out:
313 /* clear flags */
314 writel_relaxed(FCR_CTCF | FCR_CTEF, qspi->io_base + QSPI_FCR);
315
316 return err;
317}
318
319static int stm32_qspi_get_mode(struct stm32_qspi *qspi, u8 buswidth)
320{
321 if (buswidth == 4)
322 return CCR_BUSWIDTH_4;
323
324 return buswidth;
325}
326
327static int stm32_qspi_send(struct spi_mem *mem, const struct spi_mem_op *op)
328{
329 struct stm32_qspi *qspi = spi_controller_get_devdata(mem->spi->master);
330 struct stm32_qspi_flash *flash = &qspi->flash[mem->spi->chip_select];
331 u32 ccr, cr, addr_max;
332 int timeout, err = 0;
333
334 dev_dbg(qspi->dev, "cmd:%#x mode:%d.%d.%d.%d addr:%#llx len:%#x\n",
335 op->cmd.opcode, op->cmd.buswidth, op->addr.buswidth,
336 op->dummy.buswidth, op->data.buswidth,
337 op->addr.val, op->data.nbytes);
338
339 err = stm32_qspi_wait_nobusy(qspi);
340 if (err)
341 goto abort;
342
343 addr_max = op->addr.val + op->data.nbytes + 1;
344
345 if (op->data.dir == SPI_MEM_DATA_IN) {
346 if (addr_max < qspi->mm_size &&
347 op->addr.buswidth)
348 qspi->fmode = CCR_FMODE_MM;
349 else
350 qspi->fmode = CCR_FMODE_INDR;
351 } else {
352 qspi->fmode = CCR_FMODE_INDW;
353 }
354
355 cr = readl_relaxed(qspi->io_base + QSPI_CR);
356 cr &= ~CR_PRESC_MASK & ~CR_FSEL;
357 cr |= FIELD_PREP(CR_PRESC_MASK, flash->presc);
358 cr |= FIELD_PREP(CR_FSEL, flash->cs);
359 writel_relaxed(cr, qspi->io_base + QSPI_CR);
360
361 if (op->data.nbytes)
362 writel_relaxed(op->data.nbytes - 1,
363 qspi->io_base + QSPI_DLR);
364 else
365 qspi->fmode = CCR_FMODE_INDW;
366
367 ccr = qspi->fmode;
368 ccr |= FIELD_PREP(CCR_INST_MASK, op->cmd.opcode);
369 ccr |= FIELD_PREP(CCR_IMODE_MASK,
370 stm32_qspi_get_mode(qspi, op->cmd.buswidth));
371
372 if (op->addr.nbytes) {
373 ccr |= FIELD_PREP(CCR_ADMODE_MASK,
374 stm32_qspi_get_mode(qspi, op->addr.buswidth));
375 ccr |= FIELD_PREP(CCR_ADSIZE_MASK, op->addr.nbytes - 1);
376 }
377
378 if (op->dummy.buswidth && op->dummy.nbytes)
379 ccr |= FIELD_PREP(CCR_DCYC_MASK,
380 op->dummy.nbytes * 8 / op->dummy.buswidth);
381
382 if (op->data.nbytes) {
383 ccr |= FIELD_PREP(CCR_DMODE_MASK,
384 stm32_qspi_get_mode(qspi, op->data.buswidth));
385 }
386
387 writel_relaxed(ccr, qspi->io_base + QSPI_CCR);
388
389 if (op->addr.nbytes && qspi->fmode != CCR_FMODE_MM)
390 writel_relaxed(op->addr.val, qspi->io_base + QSPI_AR);
391
392 err = stm32_qspi_tx(qspi, op);
393
394 /*
395 * Abort in:
396 * -error case
397 * -read memory map: prefetching must be stopped if we read the last
398 * byte of device (device size - fifo size). like device size is not
399 * knows, the prefetching is always stop.
400 */
401 if (err || qspi->fmode == CCR_FMODE_MM)
402 goto abort;
403
404 /* wait end of tx in indirect mode */
405 err = stm32_qspi_wait_cmd(qspi, op);
406 if (err)
407 goto abort;
408
409 return 0;
410
411abort:
412 cr = readl_relaxed(qspi->io_base + QSPI_CR) | CR_ABORT;
413 writel_relaxed(cr, qspi->io_base + QSPI_CR);
414
415 /* wait clear of abort bit by hw */
416 timeout = readl_relaxed_poll_timeout_atomic(qspi->io_base + QSPI_CR,
417 cr, !(cr & CR_ABORT), 1,
418 STM32_ABT_TIMEOUT_US);
419
420 writel_relaxed(FCR_CTCF, qspi->io_base + QSPI_FCR);
421
422 if (err || timeout)
423 dev_err(qspi->dev, "%s err:%d abort timeout:%d\n",
424 __func__, err, timeout);
425
426 return err;
427}
428
429static int stm32_qspi_exec_op(struct spi_mem *mem, const struct spi_mem_op *op)
430{
431 struct stm32_qspi *qspi = spi_controller_get_devdata(mem->spi->master);
432 int ret;
433
434 mutex_lock(&qspi->lock);
435 ret = stm32_qspi_send(mem, op);
436 mutex_unlock(&qspi->lock);
437
438 return ret;
439}
440
441static int stm32_qspi_setup(struct spi_device *spi)
442{
443 struct spi_controller *ctrl = spi->master;
444 struct stm32_qspi *qspi = spi_controller_get_devdata(ctrl);
445 struct stm32_qspi_flash *flash;
446 u32 presc;
447
448 if (ctrl->busy)
449 return -EBUSY;
450
451 if (!spi->max_speed_hz)
452 return -EINVAL;
453
454 presc = DIV_ROUND_UP(qspi->clk_rate, spi->max_speed_hz) - 1;
455
456 flash = &qspi->flash[spi->chip_select];
457 flash->qspi = qspi;
458 flash->cs = spi->chip_select;
459 flash->presc = presc;
460
461 mutex_lock(&qspi->lock);
462 qspi->cr_reg = 3 << CR_FTHRES_SHIFT | CR_SSHIFT | CR_EN;
463 writel_relaxed(qspi->cr_reg, qspi->io_base + QSPI_CR);
464
465 /* set dcr fsize to max address */
466 qspi->dcr_reg = DCR_FSIZE_MASK;
467 writel_relaxed(qspi->dcr_reg, qspi->io_base + QSPI_DCR);
468 mutex_unlock(&qspi->lock);
469
470 return 0;
471}
472
473static void stm32_qspi_dma_setup(struct stm32_qspi *qspi)
474{
475 struct dma_slave_config dma_cfg;
476 struct device *dev = qspi->dev;
477
478 memset(&dma_cfg, 0, sizeof(dma_cfg));
479
480 dma_cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
481 dma_cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
482 dma_cfg.src_addr = qspi->phys_base + QSPI_DR;
483 dma_cfg.dst_addr = qspi->phys_base + QSPI_DR;
484 dma_cfg.src_maxburst = 4;
485 dma_cfg.dst_maxburst = 4;
486
487 qspi->dma_chrx = dma_request_slave_channel(dev, "rx");
488 if (qspi->dma_chrx) {
489 if (dmaengine_slave_config(qspi->dma_chrx, &dma_cfg)) {
490 dev_err(dev, "dma rx config failed\n");
491 dma_release_channel(qspi->dma_chrx);
492 qspi->dma_chrx = NULL;
493 }
494 }
495
496 qspi->dma_chtx = dma_request_slave_channel(dev, "tx");
497 if (qspi->dma_chtx) {
498 if (dmaengine_slave_config(qspi->dma_chtx, &dma_cfg)) {
499 dev_err(dev, "dma tx config failed\n");
500 dma_release_channel(qspi->dma_chtx);
501 qspi->dma_chtx = NULL;
502 }
503 }
504
505 init_completion(&qspi->dma_completion);
506}
507
508static void stm32_qspi_dma_free(struct stm32_qspi *qspi)
509{
510 if (qspi->dma_chtx)
511 dma_release_channel(qspi->dma_chtx);
512 if (qspi->dma_chrx)
513 dma_release_channel(qspi->dma_chrx);
514}
515
516/*
517 * no special host constraint, so use default spi_mem_default_supports_op
518 * to check supported mode.
519 */
520static const struct spi_controller_mem_ops stm32_qspi_mem_ops = {
521 .exec_op = stm32_qspi_exec_op,
522};
523
524static void stm32_qspi_release(struct stm32_qspi *qspi)
525{
526 /* disable qspi */
527 writel_relaxed(0, qspi->io_base + QSPI_CR);
528 stm32_qspi_dma_free(qspi);
529 mutex_destroy(&qspi->lock);
530 clk_disable_unprepare(qspi->clk);
531 spi_master_put(qspi->ctrl);
532}
533
534static int stm32_qspi_probe(struct platform_device *pdev)
535{
536 struct device *dev = &pdev->dev;
537 struct spi_controller *ctrl;
538 struct reset_control *rstc;
539 struct stm32_qspi *qspi;
540 struct resource *res;
541 int ret, irq;
542
543 ctrl = spi_alloc_master(dev, sizeof(*qspi));
544 if (!ctrl)
545 return -ENOMEM;
546
547 qspi = spi_controller_get_devdata(ctrl);
548 qspi->ctrl = ctrl;
549
550 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "qspi");
551 qspi->io_base = devm_ioremap_resource(dev, res);
552 if (IS_ERR(qspi->io_base)) {
553 ret = PTR_ERR(qspi->io_base);
554 goto err;
555 }
556
557 qspi->phys_base = res->start;
558
559 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "qspi_mm");
560 qspi->mm_base = devm_ioremap_resource(dev, res);
561 if (IS_ERR(qspi->mm_base)) {
562 ret = PTR_ERR(qspi->mm_base);
563 goto err;
564 }
565
566 qspi->mm_size = resource_size(res);
567 if (qspi->mm_size > STM32_QSPI_MAX_MMAP_SZ) {
568 ret = -EINVAL;
569 goto err;
570 }
571
572 irq = platform_get_irq(pdev, 0);
573 if (irq < 0)
574 return irq;
575
576 ret = devm_request_irq(dev, irq, stm32_qspi_irq, 0,
577 dev_name(dev), qspi);
578 if (ret) {
579 dev_err(dev, "failed to request irq\n");
580 goto err;
581 }
582
583 init_completion(&qspi->data_completion);
584
585 qspi->clk = devm_clk_get(dev, NULL);
586 if (IS_ERR(qspi->clk)) {
587 ret = PTR_ERR(qspi->clk);
588 goto err;
589 }
590
591 qspi->clk_rate = clk_get_rate(qspi->clk);
592 if (!qspi->clk_rate) {
593 ret = -EINVAL;
594 goto err;
595 }
596
597 ret = clk_prepare_enable(qspi->clk);
598 if (ret) {
599 dev_err(dev, "can not enable the clock\n");
600 goto err;
601 }
602
603 rstc = devm_reset_control_get_exclusive(dev, NULL);
604 if (!IS_ERR(rstc)) {
605 reset_control_assert(rstc);
606 udelay(2);
607 reset_control_deassert(rstc);
608 }
609
610 qspi->dev = dev;
611 platform_set_drvdata(pdev, qspi);
612 stm32_qspi_dma_setup(qspi);
613 mutex_init(&qspi->lock);
614
615 ctrl->mode_bits = SPI_RX_DUAL | SPI_RX_QUAD
616 | SPI_TX_DUAL | SPI_TX_QUAD;
617 ctrl->setup = stm32_qspi_setup;
618 ctrl->bus_num = -1;
619 ctrl->mem_ops = &stm32_qspi_mem_ops;
620 ctrl->num_chipselect = STM32_QSPI_MAX_NORCHIP;
621 ctrl->dev.of_node = dev->of_node;
622
623 ret = devm_spi_register_master(dev, ctrl);
624 if (!ret)
625 return 0;
626
627err:
628 stm32_qspi_release(qspi);
629 return ret;
630}
631
632static int stm32_qspi_remove(struct platform_device *pdev)
633{
634 struct stm32_qspi *qspi = platform_get_drvdata(pdev);
635
636 stm32_qspi_release(qspi);
637 return 0;
638}
639
640static int __maybe_unused stm32_qspi_suspend(struct device *dev)
641{
642 struct stm32_qspi *qspi = dev_get_drvdata(dev);
643
644 clk_disable_unprepare(qspi->clk);
645 pinctrl_pm_select_sleep_state(dev);
646
647 return 0;
648}
649
650static int __maybe_unused stm32_qspi_resume(struct device *dev)
651{
652 struct stm32_qspi *qspi = dev_get_drvdata(dev);
653
654 pinctrl_pm_select_default_state(dev);
655 clk_prepare_enable(qspi->clk);
656
657 writel_relaxed(qspi->cr_reg, qspi->io_base + QSPI_CR);
658 writel_relaxed(qspi->dcr_reg, qspi->io_base + QSPI_DCR);
659
660 return 0;
661}
662
663static SIMPLE_DEV_PM_OPS(stm32_qspi_pm_ops, stm32_qspi_suspend, stm32_qspi_resume);
664
665static const struct of_device_id stm32_qspi_match[] = {
666 {.compatible = "st,stm32f469-qspi"},
667 {}
668};
669MODULE_DEVICE_TABLE(of, stm32_qspi_match);
670
671static struct platform_driver stm32_qspi_driver = {
672 .probe = stm32_qspi_probe,
673 .remove = stm32_qspi_remove,
674 .driver = {
675 .name = "stm32-qspi",
676 .of_match_table = stm32_qspi_match,
677 .pm = &stm32_qspi_pm_ops,
678 },
679};
680module_platform_driver(stm32_qspi_driver);
681
682MODULE_AUTHOR("Ludovic Barre <ludovic.barre@st.com>");
683MODULE_DESCRIPTION("STMicroelectronics STM32 quad spi driver");
684MODULE_LICENSE("GPL v2");