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1/*
2 * Copyright (C) 2017 Spreadtrum Communications Inc.
3 *
4 * SPDX-License-Identifier: GPL-2.0
5 */
6
7#include <linux/delay.h>
8#include <linux/hwspinlock.h>
9#include <linux/init.h>
10#include <linux/io.h>
11#include <linux/kernel.h>
12#include <linux/module.h>
13#include <linux/of.h>
14#include <linux/of_device.h>
15#include <linux/platform_device.h>
16#include <linux/reboot.h>
17#include <linux/spi/spi.h>
18#include <linux/sizes.h>
19
20/* Registers definitions for ADI controller */
21#define REG_ADI_CTRL0 0x4
22#define REG_ADI_CHN_PRIL 0x8
23#define REG_ADI_CHN_PRIH 0xc
24#define REG_ADI_INT_EN 0x10
25#define REG_ADI_INT_RAW 0x14
26#define REG_ADI_INT_MASK 0x18
27#define REG_ADI_INT_CLR 0x1c
28#define REG_ADI_GSSI_CFG0 0x20
29#define REG_ADI_GSSI_CFG1 0x24
30#define REG_ADI_RD_CMD 0x28
31#define REG_ADI_RD_DATA 0x2c
32#define REG_ADI_ARM_FIFO_STS 0x30
33#define REG_ADI_STS 0x34
34#define REG_ADI_EVT_FIFO_STS 0x38
35#define REG_ADI_ARM_CMD_STS 0x3c
36#define REG_ADI_CHN_EN 0x40
37#define REG_ADI_CHN_ADDR(id) (0x44 + (id - 2) * 4)
38#define REG_ADI_CHN_EN1 0x20c
39
40/* Bits definitions for register REG_ADI_GSSI_CFG0 */
41#define BIT_CLK_ALL_ON BIT(30)
42
43/* Bits definitions for register REG_ADI_RD_DATA */
44#define BIT_RD_CMD_BUSY BIT(31)
45#define RD_ADDR_SHIFT 16
46#define RD_VALUE_MASK GENMASK(15, 0)
47#define RD_ADDR_MASK GENMASK(30, 16)
48
49/* Bits definitions for register REG_ADI_ARM_FIFO_STS */
50#define BIT_FIFO_FULL BIT(11)
51#define BIT_FIFO_EMPTY BIT(10)
52
53/*
54 * ADI slave devices include RTC, ADC, regulator, charger, thermal and so on.
55 * The slave devices address offset is always 0x8000 and size is 4K.
56 */
57#define ADI_SLAVE_ADDR_SIZE SZ_4K
58#define ADI_SLAVE_OFFSET 0x8000
59
60/* Timeout (ms) for the trylock of hardware spinlocks */
61#define ADI_HWSPINLOCK_TIMEOUT 5000
62/*
63 * ADI controller has 50 channels including 2 software channels
64 * and 48 hardware channels.
65 */
66#define ADI_HW_CHNS 50
67
68#define ADI_FIFO_DRAIN_TIMEOUT 1000
69#define ADI_READ_TIMEOUT 2000
70#define REG_ADDR_LOW_MASK GENMASK(11, 0)
71
72/* Registers definitions for PMIC watchdog controller */
73#define REG_WDG_LOAD_LOW 0x80
74#define REG_WDG_LOAD_HIGH 0x84
75#define REG_WDG_CTRL 0x88
76#define REG_WDG_LOCK 0xa0
77
78/* Bits definitions for register REG_WDG_CTRL */
79#define BIT_WDG_RUN BIT(1)
80#define BIT_WDG_RST BIT(3)
81
82/* Registers definitions for PMIC */
83#define PMIC_RST_STATUS 0xee8
84#define PMIC_MODULE_EN 0xc08
85#define PMIC_CLK_EN 0xc18
86#define BIT_WDG_EN BIT(2)
87
88/* Definition of PMIC reset status register */
89#define HWRST_STATUS_SECURITY 0x02
90#define HWRST_STATUS_RECOVERY 0x20
91#define HWRST_STATUS_NORMAL 0x40
92#define HWRST_STATUS_ALARM 0x50
93#define HWRST_STATUS_SLEEP 0x60
94#define HWRST_STATUS_FASTBOOT 0x30
95#define HWRST_STATUS_SPECIAL 0x70
96#define HWRST_STATUS_PANIC 0x80
97#define HWRST_STATUS_CFTREBOOT 0x90
98#define HWRST_STATUS_AUTODLOADER 0xa0
99#define HWRST_STATUS_IQMODE 0xb0
100#define HWRST_STATUS_SPRDISK 0xc0
101#define HWRST_STATUS_FACTORYTEST 0xe0
102#define HWRST_STATUS_WATCHDOG 0xf0
103
104/* Use default timeout 50 ms that converts to watchdog values */
105#define WDG_LOAD_VAL ((50 * 1000) / 32768)
106#define WDG_LOAD_MASK GENMASK(15, 0)
107#define WDG_UNLOCK_KEY 0xe551
108
109struct sprd_adi {
110 struct spi_controller *ctlr;
111 struct device *dev;
112 void __iomem *base;
113 struct hwspinlock *hwlock;
114 unsigned long slave_vbase;
115 unsigned long slave_pbase;
116 struct notifier_block restart_handler;
117};
118
119static int sprd_adi_check_paddr(struct sprd_adi *sadi, u32 paddr)
120{
121 if (paddr < sadi->slave_pbase || paddr >
122 (sadi->slave_pbase + ADI_SLAVE_ADDR_SIZE)) {
123 dev_err(sadi->dev,
124 "slave physical address is incorrect, addr = 0x%x\n",
125 paddr);
126 return -EINVAL;
127 }
128
129 return 0;
130}
131
132static unsigned long sprd_adi_to_vaddr(struct sprd_adi *sadi, u32 paddr)
133{
134 return (paddr - sadi->slave_pbase + sadi->slave_vbase);
135}
136
137static int sprd_adi_drain_fifo(struct sprd_adi *sadi)
138{
139 u32 timeout = ADI_FIFO_DRAIN_TIMEOUT;
140 u32 sts;
141
142 do {
143 sts = readl_relaxed(sadi->base + REG_ADI_ARM_FIFO_STS);
144 if (sts & BIT_FIFO_EMPTY)
145 break;
146
147 cpu_relax();
148 } while (--timeout);
149
150 if (timeout == 0) {
151 dev_err(sadi->dev, "drain write fifo timeout\n");
152 return -EBUSY;
153 }
154
155 return 0;
156}
157
158static int sprd_adi_fifo_is_full(struct sprd_adi *sadi)
159{
160 return readl_relaxed(sadi->base + REG_ADI_ARM_FIFO_STS) & BIT_FIFO_FULL;
161}
162
163static int sprd_adi_read(struct sprd_adi *sadi, u32 reg_paddr, u32 *read_val)
164{
165 int read_timeout = ADI_READ_TIMEOUT;
166 unsigned long flags;
167 u32 val, rd_addr;
168 int ret = 0;
169
170 if (sadi->hwlock) {
171 ret = hwspin_lock_timeout_irqsave(sadi->hwlock,
172 ADI_HWSPINLOCK_TIMEOUT,
173 &flags);
174 if (ret) {
175 dev_err(sadi->dev, "get the hw lock failed\n");
176 return ret;
177 }
178 }
179
180 /*
181 * Set the physical register address need to read into RD_CMD register,
182 * then ADI controller will start to transfer automatically.
183 */
184 writel_relaxed(reg_paddr, sadi->base + REG_ADI_RD_CMD);
185
186 /*
187 * Wait read operation complete, the BIT_RD_CMD_BUSY will be set
188 * simultaneously when writing read command to register, and the
189 * BIT_RD_CMD_BUSY will be cleared after the read operation is
190 * completed.
191 */
192 do {
193 val = readl_relaxed(sadi->base + REG_ADI_RD_DATA);
194 if (!(val & BIT_RD_CMD_BUSY))
195 break;
196
197 cpu_relax();
198 } while (--read_timeout);
199
200 if (read_timeout == 0) {
201 dev_err(sadi->dev, "ADI read timeout\n");
202 ret = -EBUSY;
203 goto out;
204 }
205
206 /*
207 * The return value includes data and read register address, from bit 0
208 * to bit 15 are data, and from bit 16 to bit 30 are read register
209 * address. Then we can check the returned register address to validate
210 * data.
211 */
212 rd_addr = (val & RD_ADDR_MASK ) >> RD_ADDR_SHIFT;
213
214 if (rd_addr != (reg_paddr & REG_ADDR_LOW_MASK)) {
215 dev_err(sadi->dev, "read error, reg addr = 0x%x, val = 0x%x\n",
216 reg_paddr, val);
217 ret = -EIO;
218 goto out;
219 }
220
221 *read_val = val & RD_VALUE_MASK;
222
223out:
224 if (sadi->hwlock)
225 hwspin_unlock_irqrestore(sadi->hwlock, &flags);
226 return ret;
227}
228
229static int sprd_adi_write(struct sprd_adi *sadi, u32 reg_paddr, u32 val)
230{
231 unsigned long reg = sprd_adi_to_vaddr(sadi, reg_paddr);
232 u32 timeout = ADI_FIFO_DRAIN_TIMEOUT;
233 unsigned long flags;
234 int ret;
235
236 if (sadi->hwlock) {
237 ret = hwspin_lock_timeout_irqsave(sadi->hwlock,
238 ADI_HWSPINLOCK_TIMEOUT,
239 &flags);
240 if (ret) {
241 dev_err(sadi->dev, "get the hw lock failed\n");
242 return ret;
243 }
244 }
245
246 ret = sprd_adi_drain_fifo(sadi);
247 if (ret < 0)
248 goto out;
249
250 /*
251 * we should wait for write fifo is empty before writing data to PMIC
252 * registers.
253 */
254 do {
255 if (!sprd_adi_fifo_is_full(sadi)) {
256 writel_relaxed(val, (void __iomem *)reg);
257 break;
258 }
259
260 cpu_relax();
261 } while (--timeout);
262
263 if (timeout == 0) {
264 dev_err(sadi->dev, "write fifo is full\n");
265 ret = -EBUSY;
266 }
267
268out:
269 if (sadi->hwlock)
270 hwspin_unlock_irqrestore(sadi->hwlock, &flags);
271 return ret;
272}
273
274static int sprd_adi_transfer_one(struct spi_controller *ctlr,
275 struct spi_device *spi_dev,
276 struct spi_transfer *t)
277{
278 struct sprd_adi *sadi = spi_controller_get_devdata(ctlr);
279 u32 phy_reg, val;
280 int ret;
281
282 if (t->rx_buf) {
283 phy_reg = *(u32 *)t->rx_buf + sadi->slave_pbase;
284
285 ret = sprd_adi_check_paddr(sadi, phy_reg);
286 if (ret)
287 return ret;
288
289 ret = sprd_adi_read(sadi, phy_reg, &val);
290 if (ret)
291 return ret;
292
293 *(u32 *)t->rx_buf = val;
294 } else if (t->tx_buf) {
295 u32 *p = (u32 *)t->tx_buf;
296
297 /*
298 * Get the physical register address need to write and convert
299 * the physical address to virtual address. Since we need
300 * virtual register address to write.
301 */
302 phy_reg = *p++ + sadi->slave_pbase;
303 ret = sprd_adi_check_paddr(sadi, phy_reg);
304 if (ret)
305 return ret;
306
307 val = *p;
308 ret = sprd_adi_write(sadi, phy_reg, val);
309 if (ret)
310 return ret;
311 } else {
312 dev_err(sadi->dev, "no buffer for transfer\n");
313 return -EINVAL;
314 }
315
316 return 0;
317}
318
319static void sprd_adi_set_wdt_rst_mode(struct sprd_adi *sadi)
320{
321#ifdef CONFIG_SPRD_WATCHDOG
322 u32 val;
323
324 /* Set default watchdog reboot mode */
325 sprd_adi_read(sadi, sadi->slave_pbase + PMIC_RST_STATUS, &val);
326 val |= HWRST_STATUS_WATCHDOG;
327 sprd_adi_write(sadi, sadi->slave_pbase + PMIC_RST_STATUS, val);
328#endif
329}
330
331static int sprd_adi_restart_handler(struct notifier_block *this,
332 unsigned long mode, void *cmd)
333{
334 struct sprd_adi *sadi = container_of(this, struct sprd_adi,
335 restart_handler);
336 u32 val, reboot_mode = 0;
337
338 if (!cmd)
339 reboot_mode = HWRST_STATUS_NORMAL;
340 else if (!strncmp(cmd, "recovery", 8))
341 reboot_mode = HWRST_STATUS_RECOVERY;
342 else if (!strncmp(cmd, "alarm", 5))
343 reboot_mode = HWRST_STATUS_ALARM;
344 else if (!strncmp(cmd, "fastsleep", 9))
345 reboot_mode = HWRST_STATUS_SLEEP;
346 else if (!strncmp(cmd, "bootloader", 10))
347 reboot_mode = HWRST_STATUS_FASTBOOT;
348 else if (!strncmp(cmd, "panic", 5))
349 reboot_mode = HWRST_STATUS_PANIC;
350 else if (!strncmp(cmd, "special", 7))
351 reboot_mode = HWRST_STATUS_SPECIAL;
352 else if (!strncmp(cmd, "cftreboot", 9))
353 reboot_mode = HWRST_STATUS_CFTREBOOT;
354 else if (!strncmp(cmd, "autodloader", 11))
355 reboot_mode = HWRST_STATUS_AUTODLOADER;
356 else if (!strncmp(cmd, "iqmode", 6))
357 reboot_mode = HWRST_STATUS_IQMODE;
358 else if (!strncmp(cmd, "sprdisk", 7))
359 reboot_mode = HWRST_STATUS_SPRDISK;
360 else if (!strncmp(cmd, "tospanic", 8))
361 reboot_mode = HWRST_STATUS_SECURITY;
362 else if (!strncmp(cmd, "factorytest", 11))
363 reboot_mode = HWRST_STATUS_FACTORYTEST;
364 else
365 reboot_mode = HWRST_STATUS_NORMAL;
366
367 /* Record the reboot mode */
368 sprd_adi_read(sadi, sadi->slave_pbase + PMIC_RST_STATUS, &val);
369 val &= ~HWRST_STATUS_WATCHDOG;
370 val |= reboot_mode;
371 sprd_adi_write(sadi, sadi->slave_pbase + PMIC_RST_STATUS, val);
372
373 /* Enable the interface clock of the watchdog */
374 sprd_adi_read(sadi, sadi->slave_pbase + PMIC_MODULE_EN, &val);
375 val |= BIT_WDG_EN;
376 sprd_adi_write(sadi, sadi->slave_pbase + PMIC_MODULE_EN, val);
377
378 /* Enable the work clock of the watchdog */
379 sprd_adi_read(sadi, sadi->slave_pbase + PMIC_CLK_EN, &val);
380 val |= BIT_WDG_EN;
381 sprd_adi_write(sadi, sadi->slave_pbase + PMIC_CLK_EN, val);
382
383 /* Unlock the watchdog */
384 sprd_adi_write(sadi, sadi->slave_pbase + REG_WDG_LOCK, WDG_UNLOCK_KEY);
385
386 /* Load the watchdog timeout value, 50ms is always enough. */
387 sprd_adi_write(sadi, sadi->slave_pbase + REG_WDG_LOAD_LOW,
388 WDG_LOAD_VAL & WDG_LOAD_MASK);
389 sprd_adi_write(sadi, sadi->slave_pbase + REG_WDG_LOAD_HIGH, 0);
390
391 /* Start the watchdog to reset system */
392 sprd_adi_read(sadi, sadi->slave_pbase + REG_WDG_CTRL, &val);
393 val |= BIT_WDG_RUN | BIT_WDG_RST;
394 sprd_adi_write(sadi, sadi->slave_pbase + REG_WDG_CTRL, val);
395
396 mdelay(1000);
397
398 dev_emerg(sadi->dev, "Unable to restart system\n");
399 return NOTIFY_DONE;
400}
401
402static void sprd_adi_hw_init(struct sprd_adi *sadi)
403{
404 struct device_node *np = sadi->dev->of_node;
405 int i, size, chn_cnt;
406 const __be32 *list;
407 u32 tmp;
408
409 /* Set all channels as default priority */
410 writel_relaxed(0, sadi->base + REG_ADI_CHN_PRIL);
411 writel_relaxed(0, sadi->base + REG_ADI_CHN_PRIH);
412
413 /* Set clock auto gate mode */
414 tmp = readl_relaxed(sadi->base + REG_ADI_GSSI_CFG0);
415 tmp &= ~BIT_CLK_ALL_ON;
416 writel_relaxed(tmp, sadi->base + REG_ADI_GSSI_CFG0);
417
418 /* Set hardware channels setting */
419 list = of_get_property(np, "sprd,hw-channels", &size);
420 if (!list || !size) {
421 dev_info(sadi->dev, "no hw channels setting in node\n");
422 return;
423 }
424
425 chn_cnt = size / 8;
426 for (i = 0; i < chn_cnt; i++) {
427 u32 value;
428 u32 chn_id = be32_to_cpu(*list++);
429 u32 chn_config = be32_to_cpu(*list++);
430
431 /* Channel 0 and 1 are software channels */
432 if (chn_id < 2)
433 continue;
434
435 writel_relaxed(chn_config, sadi->base +
436 REG_ADI_CHN_ADDR(chn_id));
437
438 if (chn_id < 32) {
439 value = readl_relaxed(sadi->base + REG_ADI_CHN_EN);
440 value |= BIT(chn_id);
441 writel_relaxed(value, sadi->base + REG_ADI_CHN_EN);
442 } else if (chn_id < ADI_HW_CHNS) {
443 value = readl_relaxed(sadi->base + REG_ADI_CHN_EN1);
444 value |= BIT(chn_id - 32);
445 writel_relaxed(value, sadi->base + REG_ADI_CHN_EN1);
446 }
447 }
448}
449
450static int sprd_adi_probe(struct platform_device *pdev)
451{
452 struct device_node *np = pdev->dev.of_node;
453 struct spi_controller *ctlr;
454 struct sprd_adi *sadi;
455 struct resource *res;
456 u32 num_chipselect;
457 int ret;
458
459 if (!np) {
460 dev_err(&pdev->dev, "can not find the adi bus node\n");
461 return -ENODEV;
462 }
463
464 pdev->id = of_alias_get_id(np, "spi");
465 num_chipselect = of_get_child_count(np);
466
467 ctlr = spi_alloc_master(&pdev->dev, sizeof(struct sprd_adi));
468 if (!ctlr)
469 return -ENOMEM;
470
471 dev_set_drvdata(&pdev->dev, ctlr);
472 sadi = spi_controller_get_devdata(ctlr);
473
474 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
475 sadi->base = devm_ioremap_resource(&pdev->dev, res);
476 if (IS_ERR(sadi->base)) {
477 ret = PTR_ERR(sadi->base);
478 goto put_ctlr;
479 }
480
481 sadi->slave_vbase = (unsigned long)sadi->base + ADI_SLAVE_OFFSET;
482 sadi->slave_pbase = res->start + ADI_SLAVE_OFFSET;
483 sadi->ctlr = ctlr;
484 sadi->dev = &pdev->dev;
485 ret = of_hwspin_lock_get_id(np, 0);
486 if (ret > 0 || (IS_ENABLED(CONFIG_HWSPINLOCK) && ret == 0)) {
487 sadi->hwlock =
488 devm_hwspin_lock_request_specific(&pdev->dev, ret);
489 if (!sadi->hwlock) {
490 ret = -ENXIO;
491 goto put_ctlr;
492 }
493 } else {
494 switch (ret) {
495 case -ENOENT:
496 dev_info(&pdev->dev, "no hardware spinlock supplied\n");
497 break;
498 default:
499 dev_err(&pdev->dev,
500 "failed to find hwlock id, %d\n", ret);
501 /* fall-through */
502 case -EPROBE_DEFER:
503 goto put_ctlr;
504 }
505 }
506
507 sprd_adi_hw_init(sadi);
508 sprd_adi_set_wdt_rst_mode(sadi);
509
510 ctlr->dev.of_node = pdev->dev.of_node;
511 ctlr->bus_num = pdev->id;
512 ctlr->num_chipselect = num_chipselect;
513 ctlr->flags = SPI_MASTER_HALF_DUPLEX;
514 ctlr->bits_per_word_mask = 0;
515 ctlr->transfer_one = sprd_adi_transfer_one;
516
517 ret = devm_spi_register_controller(&pdev->dev, ctlr);
518 if (ret) {
519 dev_err(&pdev->dev, "failed to register SPI controller\n");
520 goto put_ctlr;
521 }
522
523 sadi->restart_handler.notifier_call = sprd_adi_restart_handler;
524 sadi->restart_handler.priority = 128;
525 ret = register_restart_handler(&sadi->restart_handler);
526 if (ret) {
527 dev_err(&pdev->dev, "can not register restart handler\n");
528 goto put_ctlr;
529 }
530
531 return 0;
532
533put_ctlr:
534 spi_controller_put(ctlr);
535 return ret;
536}
537
538static int sprd_adi_remove(struct platform_device *pdev)
539{
540 struct spi_controller *ctlr = dev_get_drvdata(&pdev->dev);
541 struct sprd_adi *sadi = spi_controller_get_devdata(ctlr);
542
543 unregister_restart_handler(&sadi->restart_handler);
544 return 0;
545}
546
547static const struct of_device_id sprd_adi_of_match[] = {
548 {
549 .compatible = "sprd,sc9860-adi",
550 },
551 { },
552};
553MODULE_DEVICE_TABLE(of, sprd_adi_of_match);
554
555static struct platform_driver sprd_adi_driver = {
556 .driver = {
557 .name = "sprd-adi",
558 .of_match_table = sprd_adi_of_match,
559 },
560 .probe = sprd_adi_probe,
561 .remove = sprd_adi_remove,
562};
563module_platform_driver(sprd_adi_driver);
564
565MODULE_DESCRIPTION("Spreadtrum ADI Controller Driver");
566MODULE_AUTHOR("Baolin Wang <Baolin.Wang@spreadtrum.com>");
567MODULE_LICENSE("GPL v2");