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1// SPDX-License-Identifier: GPL-2.0
2// Copyright (c) 2017-2018, The Linux foundation. All rights reserved.
3
4#include <linux/clk.h>
5#include <linux/interrupt.h>
6#include <linux/io.h>
7#include <linux/module.h>
8#include <linux/of.h>
9#include <linux/of_platform.h>
10#include <linux/pm_runtime.h>
11#include <linux/spi/spi.h>
12#include <linux/spi/spi-mem.h>
13
14
15#define QSPI_NUM_CS 2
16#define QSPI_BYTES_PER_WORD 4
17
18#define MSTR_CONFIG 0x0000
19#define FULL_CYCLE_MODE BIT(3)
20#define FB_CLK_EN BIT(4)
21#define PIN_HOLDN BIT(6)
22#define PIN_WPN BIT(7)
23#define DMA_ENABLE BIT(8)
24#define BIG_ENDIAN_MODE BIT(9)
25#define SPI_MODE_MSK 0xc00
26#define SPI_MODE_SHFT 10
27#define CHIP_SELECT_NUM BIT(12)
28#define SBL_EN BIT(13)
29#define LPA_BASE_MSK 0x3c000
30#define LPA_BASE_SHFT 14
31#define TX_DATA_DELAY_MSK 0xc0000
32#define TX_DATA_DELAY_SHFT 18
33#define TX_CLK_DELAY_MSK 0x300000
34#define TX_CLK_DELAY_SHFT 20
35#define TX_CS_N_DELAY_MSK 0xc00000
36#define TX_CS_N_DELAY_SHFT 22
37#define TX_DATA_OE_DELAY_MSK 0x3000000
38#define TX_DATA_OE_DELAY_SHFT 24
39
40#define AHB_MASTER_CFG 0x0004
41#define HMEM_TYPE_START_MID_TRANS_MSK 0x7
42#define HMEM_TYPE_START_MID_TRANS_SHFT 0
43#define HMEM_TYPE_LAST_TRANS_MSK 0x38
44#define HMEM_TYPE_LAST_TRANS_SHFT 3
45#define USE_HMEMTYPE_LAST_ON_DESC_OR_CHAIN_MSK 0xc0
46#define USE_HMEMTYPE_LAST_ON_DESC_OR_CHAIN_SHFT 6
47#define HMEMTYPE_READ_TRANS_MSK 0x700
48#define HMEMTYPE_READ_TRANS_SHFT 8
49#define HSHARED BIT(11)
50#define HINNERSHARED BIT(12)
51
52#define MSTR_INT_EN 0x000C
53#define MSTR_INT_STATUS 0x0010
54#define RESP_FIFO_UNDERRUN BIT(0)
55#define RESP_FIFO_NOT_EMPTY BIT(1)
56#define RESP_FIFO_RDY BIT(2)
57#define HRESP_FROM_NOC_ERR BIT(3)
58#define WR_FIFO_EMPTY BIT(9)
59#define WR_FIFO_FULL BIT(10)
60#define WR_FIFO_OVERRUN BIT(11)
61#define TRANSACTION_DONE BIT(16)
62#define QSPI_ERR_IRQS (RESP_FIFO_UNDERRUN | HRESP_FROM_NOC_ERR | \
63 WR_FIFO_OVERRUN)
64#define QSPI_ALL_IRQS (QSPI_ERR_IRQS | RESP_FIFO_RDY | \
65 WR_FIFO_EMPTY | WR_FIFO_FULL | \
66 TRANSACTION_DONE)
67
68#define PIO_XFER_CTRL 0x0014
69#define REQUEST_COUNT_MSK 0xffff
70
71#define PIO_XFER_CFG 0x0018
72#define TRANSFER_DIRECTION BIT(0)
73#define MULTI_IO_MODE_MSK 0xe
74#define MULTI_IO_MODE_SHFT 1
75#define TRANSFER_FRAGMENT BIT(8)
76#define SDR_1BIT 1
77#define SDR_2BIT 2
78#define SDR_4BIT 3
79#define DDR_1BIT 5
80#define DDR_2BIT 6
81#define DDR_4BIT 7
82#define DMA_DESC_SINGLE_SPI 1
83#define DMA_DESC_DUAL_SPI 2
84#define DMA_DESC_QUAD_SPI 3
85
86#define PIO_XFER_STATUS 0x001c
87#define WR_FIFO_BYTES_MSK 0xffff0000
88#define WR_FIFO_BYTES_SHFT 16
89
90#define PIO_DATAOUT_1B 0x0020
91#define PIO_DATAOUT_4B 0x0024
92
93#define RD_FIFO_CFG 0x0028
94#define CONTINUOUS_MODE BIT(0)
95
96#define RD_FIFO_STATUS 0x002c
97#define FIFO_EMPTY BIT(11)
98#define WR_CNTS_MSK 0x7f0
99#define WR_CNTS_SHFT 4
100#define RDY_64BYTE BIT(3)
101#define RDY_32BYTE BIT(2)
102#define RDY_16BYTE BIT(1)
103#define FIFO_RDY BIT(0)
104
105#define RD_FIFO_RESET 0x0030
106#define RESET_FIFO BIT(0)
107
108#define CUR_MEM_ADDR 0x0048
109#define HW_VERSION 0x004c
110#define RD_FIFO 0x0050
111#define SAMPLING_CLK_CFG 0x0090
112#define SAMPLING_CLK_STATUS 0x0094
113
114
115enum qspi_dir {
116 QSPI_READ,
117 QSPI_WRITE,
118};
119
120struct qspi_xfer {
121 union {
122 const void *tx_buf;
123 void *rx_buf;
124 };
125 unsigned int rem_bytes;
126 unsigned int buswidth;
127 enum qspi_dir dir;
128 bool is_last;
129};
130
131enum qspi_clocks {
132 QSPI_CLK_CORE,
133 QSPI_CLK_IFACE,
134 QSPI_NUM_CLKS
135};
136
137struct qcom_qspi {
138 void __iomem *base;
139 struct device *dev;
140 struct clk_bulk_data clks[QSPI_NUM_CLKS];
141 struct qspi_xfer xfer;
142 /* Lock to protect xfer and IRQ accessed registers */
143 spinlock_t lock;
144};
145
146static u32 qspi_buswidth_to_iomode(struct qcom_qspi *ctrl,
147 unsigned int buswidth)
148{
149 switch (buswidth) {
150 case 1:
151 return SDR_1BIT << MULTI_IO_MODE_SHFT;
152 case 2:
153 return SDR_2BIT << MULTI_IO_MODE_SHFT;
154 case 4:
155 return SDR_4BIT << MULTI_IO_MODE_SHFT;
156 default:
157 dev_warn_once(ctrl->dev,
158 "Unexpected bus width: %u\n", buswidth);
159 return SDR_1BIT << MULTI_IO_MODE_SHFT;
160 }
161}
162
163static void qcom_qspi_pio_xfer_cfg(struct qcom_qspi *ctrl)
164{
165 u32 pio_xfer_cfg;
166 const struct qspi_xfer *xfer;
167
168 xfer = &ctrl->xfer;
169 pio_xfer_cfg = readl(ctrl->base + PIO_XFER_CFG);
170 pio_xfer_cfg &= ~TRANSFER_DIRECTION;
171 pio_xfer_cfg |= xfer->dir;
172 if (xfer->is_last)
173 pio_xfer_cfg &= ~TRANSFER_FRAGMENT;
174 else
175 pio_xfer_cfg |= TRANSFER_FRAGMENT;
176 pio_xfer_cfg &= ~MULTI_IO_MODE_MSK;
177 pio_xfer_cfg |= qspi_buswidth_to_iomode(ctrl, xfer->buswidth);
178
179 writel(pio_xfer_cfg, ctrl->base + PIO_XFER_CFG);
180}
181
182static void qcom_qspi_pio_xfer_ctrl(struct qcom_qspi *ctrl)
183{
184 u32 pio_xfer_ctrl;
185
186 pio_xfer_ctrl = readl(ctrl->base + PIO_XFER_CTRL);
187 pio_xfer_ctrl &= ~REQUEST_COUNT_MSK;
188 pio_xfer_ctrl |= ctrl->xfer.rem_bytes;
189 writel(pio_xfer_ctrl, ctrl->base + PIO_XFER_CTRL);
190}
191
192static void qcom_qspi_pio_xfer(struct qcom_qspi *ctrl)
193{
194 u32 ints;
195
196 qcom_qspi_pio_xfer_cfg(ctrl);
197
198 /* Ack any previous interrupts that might be hanging around */
199 writel(QSPI_ALL_IRQS, ctrl->base + MSTR_INT_STATUS);
200
201 /* Setup new interrupts */
202 if (ctrl->xfer.dir == QSPI_WRITE)
203 ints = QSPI_ERR_IRQS | WR_FIFO_EMPTY;
204 else
205 ints = QSPI_ERR_IRQS | RESP_FIFO_RDY;
206 writel(ints, ctrl->base + MSTR_INT_EN);
207
208 /* Kick off the transfer */
209 qcom_qspi_pio_xfer_ctrl(ctrl);
210}
211
212static void qcom_qspi_handle_err(struct spi_master *master,
213 struct spi_message *msg)
214{
215 struct qcom_qspi *ctrl = spi_master_get_devdata(master);
216 unsigned long flags;
217
218 spin_lock_irqsave(&ctrl->lock, flags);
219 writel(0, ctrl->base + MSTR_INT_EN);
220 ctrl->xfer.rem_bytes = 0;
221 spin_unlock_irqrestore(&ctrl->lock, flags);
222}
223
224static int qcom_qspi_transfer_one(struct spi_master *master,
225 struct spi_device *slv,
226 struct spi_transfer *xfer)
227{
228 struct qcom_qspi *ctrl = spi_master_get_devdata(master);
229 int ret;
230 unsigned long speed_hz;
231 unsigned long flags;
232
233 speed_hz = slv->max_speed_hz;
234 if (xfer->speed_hz)
235 speed_hz = xfer->speed_hz;
236
237 /* In regular operation (SBL_EN=1) core must be 4x transfer clock */
238 ret = clk_set_rate(ctrl->clks[QSPI_CLK_CORE].clk, speed_hz * 4);
239 if (ret) {
240 dev_err(ctrl->dev, "Failed to set core clk %d\n", ret);
241 return ret;
242 }
243
244 spin_lock_irqsave(&ctrl->lock, flags);
245
246 /* We are half duplex, so either rx or tx will be set */
247 if (xfer->rx_buf) {
248 ctrl->xfer.dir = QSPI_READ;
249 ctrl->xfer.buswidth = xfer->rx_nbits;
250 ctrl->xfer.rx_buf = xfer->rx_buf;
251 } else {
252 ctrl->xfer.dir = QSPI_WRITE;
253 ctrl->xfer.buswidth = xfer->tx_nbits;
254 ctrl->xfer.tx_buf = xfer->tx_buf;
255 }
256 ctrl->xfer.is_last = list_is_last(&xfer->transfer_list,
257 &master->cur_msg->transfers);
258 ctrl->xfer.rem_bytes = xfer->len;
259 qcom_qspi_pio_xfer(ctrl);
260
261 spin_unlock_irqrestore(&ctrl->lock, flags);
262
263 /* We'll call spi_finalize_current_transfer() when done */
264 return 1;
265}
266
267static int qcom_qspi_prepare_message(struct spi_master *master,
268 struct spi_message *message)
269{
270 u32 mstr_cfg;
271 struct qcom_qspi *ctrl;
272 int tx_data_oe_delay = 1;
273 int tx_data_delay = 1;
274 unsigned long flags;
275
276 ctrl = spi_master_get_devdata(master);
277 spin_lock_irqsave(&ctrl->lock, flags);
278
279 mstr_cfg = readl(ctrl->base + MSTR_CONFIG);
280 mstr_cfg &= ~CHIP_SELECT_NUM;
281 if (message->spi->chip_select)
282 mstr_cfg |= CHIP_SELECT_NUM;
283
284 mstr_cfg |= FB_CLK_EN | PIN_WPN | PIN_HOLDN | SBL_EN | FULL_CYCLE_MODE;
285 mstr_cfg &= ~(SPI_MODE_MSK | TX_DATA_OE_DELAY_MSK | TX_DATA_DELAY_MSK);
286 mstr_cfg |= message->spi->mode << SPI_MODE_SHFT;
287 mstr_cfg |= tx_data_oe_delay << TX_DATA_OE_DELAY_SHFT;
288 mstr_cfg |= tx_data_delay << TX_DATA_DELAY_SHFT;
289 mstr_cfg &= ~DMA_ENABLE;
290
291 writel(mstr_cfg, ctrl->base + MSTR_CONFIG);
292 spin_unlock_irqrestore(&ctrl->lock, flags);
293
294 return 0;
295}
296
297static irqreturn_t pio_read(struct qcom_qspi *ctrl)
298{
299 u32 rd_fifo_status;
300 u32 rd_fifo;
301 unsigned int wr_cnts;
302 unsigned int bytes_to_read;
303 unsigned int words_to_read;
304 u32 *word_buf;
305 u8 *byte_buf;
306 int i;
307
308 rd_fifo_status = readl(ctrl->base + RD_FIFO_STATUS);
309
310 if (!(rd_fifo_status & FIFO_RDY)) {
311 dev_dbg(ctrl->dev, "Spurious IRQ %#x\n", rd_fifo_status);
312 return IRQ_NONE;
313 }
314
315 wr_cnts = (rd_fifo_status & WR_CNTS_MSK) >> WR_CNTS_SHFT;
316 wr_cnts = min(wr_cnts, ctrl->xfer.rem_bytes);
317
318 words_to_read = wr_cnts / QSPI_BYTES_PER_WORD;
319 bytes_to_read = wr_cnts % QSPI_BYTES_PER_WORD;
320
321 if (words_to_read) {
322 word_buf = ctrl->xfer.rx_buf;
323 ctrl->xfer.rem_bytes -= words_to_read * QSPI_BYTES_PER_WORD;
324 ioread32_rep(ctrl->base + RD_FIFO, word_buf, words_to_read);
325 ctrl->xfer.rx_buf = word_buf + words_to_read;
326 }
327
328 if (bytes_to_read) {
329 byte_buf = ctrl->xfer.rx_buf;
330 rd_fifo = readl(ctrl->base + RD_FIFO);
331 ctrl->xfer.rem_bytes -= bytes_to_read;
332 for (i = 0; i < bytes_to_read; i++)
333 *byte_buf++ = rd_fifo >> (i * BITS_PER_BYTE);
334 ctrl->xfer.rx_buf = byte_buf;
335 }
336
337 return IRQ_HANDLED;
338}
339
340static irqreturn_t pio_write(struct qcom_qspi *ctrl)
341{
342 const void *xfer_buf = ctrl->xfer.tx_buf;
343 const int *word_buf;
344 const char *byte_buf;
345 unsigned int wr_fifo_bytes;
346 unsigned int wr_fifo_words;
347 unsigned int wr_size;
348 unsigned int rem_words;
349
350 wr_fifo_bytes = readl(ctrl->base + PIO_XFER_STATUS);
351 wr_fifo_bytes >>= WR_FIFO_BYTES_SHFT;
352
353 if (ctrl->xfer.rem_bytes < QSPI_BYTES_PER_WORD) {
354 /* Process the last 1-3 bytes */
355 wr_size = min(wr_fifo_bytes, ctrl->xfer.rem_bytes);
356 ctrl->xfer.rem_bytes -= wr_size;
357
358 byte_buf = xfer_buf;
359 while (wr_size--)
360 writel(*byte_buf++,
361 ctrl->base + PIO_DATAOUT_1B);
362 ctrl->xfer.tx_buf = byte_buf;
363 } else {
364 /*
365 * Process all the whole words; to keep things simple we'll
366 * just wait for the next interrupt to handle the last 1-3
367 * bytes if we don't have an even number of words.
368 */
369 rem_words = ctrl->xfer.rem_bytes / QSPI_BYTES_PER_WORD;
370 wr_fifo_words = wr_fifo_bytes / QSPI_BYTES_PER_WORD;
371
372 wr_size = min(rem_words, wr_fifo_words);
373 ctrl->xfer.rem_bytes -= wr_size * QSPI_BYTES_PER_WORD;
374
375 word_buf = xfer_buf;
376 iowrite32_rep(ctrl->base + PIO_DATAOUT_4B, word_buf, wr_size);
377 ctrl->xfer.tx_buf = word_buf + wr_size;
378
379 }
380
381 return IRQ_HANDLED;
382}
383
384static irqreturn_t qcom_qspi_irq(int irq, void *dev_id)
385{
386 u32 int_status;
387 struct qcom_qspi *ctrl = dev_id;
388 irqreturn_t ret = IRQ_NONE;
389 unsigned long flags;
390
391 spin_lock_irqsave(&ctrl->lock, flags);
392
393 int_status = readl(ctrl->base + MSTR_INT_STATUS);
394 writel(int_status, ctrl->base + MSTR_INT_STATUS);
395
396 if (ctrl->xfer.dir == QSPI_WRITE) {
397 if (int_status & WR_FIFO_EMPTY)
398 ret = pio_write(ctrl);
399 } else {
400 if (int_status & RESP_FIFO_RDY)
401 ret = pio_read(ctrl);
402 }
403
404 if (int_status & QSPI_ERR_IRQS) {
405 if (int_status & RESP_FIFO_UNDERRUN)
406 dev_err(ctrl->dev, "IRQ error: FIFO underrun\n");
407 if (int_status & WR_FIFO_OVERRUN)
408 dev_err(ctrl->dev, "IRQ error: FIFO overrun\n");
409 if (int_status & HRESP_FROM_NOC_ERR)
410 dev_err(ctrl->dev, "IRQ error: NOC response error\n");
411 ret = IRQ_HANDLED;
412 }
413
414 if (!ctrl->xfer.rem_bytes) {
415 writel(0, ctrl->base + MSTR_INT_EN);
416 spi_finalize_current_transfer(dev_get_drvdata(ctrl->dev));
417 }
418
419 spin_unlock_irqrestore(&ctrl->lock, flags);
420 return ret;
421}
422
423static int qcom_qspi_probe(struct platform_device *pdev)
424{
425 int ret;
426 struct device *dev;
427 struct spi_master *master;
428 struct qcom_qspi *ctrl;
429
430 dev = &pdev->dev;
431
432 master = spi_alloc_master(dev, sizeof(*ctrl));
433 if (!master)
434 return -ENOMEM;
435
436 platform_set_drvdata(pdev, master);
437
438 ctrl = spi_master_get_devdata(master);
439
440 spin_lock_init(&ctrl->lock);
441 ctrl->dev = dev;
442 ctrl->base = devm_platform_ioremap_resource(pdev, 0);
443 if (IS_ERR(ctrl->base)) {
444 ret = PTR_ERR(ctrl->base);
445 goto exit_probe_master_put;
446 }
447
448 ctrl->clks[QSPI_CLK_CORE].id = "core";
449 ctrl->clks[QSPI_CLK_IFACE].id = "iface";
450 ret = devm_clk_bulk_get(dev, QSPI_NUM_CLKS, ctrl->clks);
451 if (ret)
452 goto exit_probe_master_put;
453
454 ret = platform_get_irq(pdev, 0);
455 if (ret < 0)
456 goto exit_probe_master_put;
457 ret = devm_request_irq(dev, ret, qcom_qspi_irq,
458 IRQF_TRIGGER_HIGH, dev_name(dev), ctrl);
459 if (ret) {
460 dev_err(dev, "Failed to request irq %d\n", ret);
461 goto exit_probe_master_put;
462 }
463
464 master->max_speed_hz = 300000000;
465 master->num_chipselect = QSPI_NUM_CS;
466 master->bus_num = -1;
467 master->dev.of_node = pdev->dev.of_node;
468 master->mode_bits = SPI_MODE_0 |
469 SPI_TX_DUAL | SPI_RX_DUAL |
470 SPI_TX_QUAD | SPI_RX_QUAD;
471 master->flags = SPI_MASTER_HALF_DUPLEX;
472 master->prepare_message = qcom_qspi_prepare_message;
473 master->transfer_one = qcom_qspi_transfer_one;
474 master->handle_err = qcom_qspi_handle_err;
475 master->auto_runtime_pm = true;
476
477 pm_runtime_enable(dev);
478
479 ret = spi_register_master(master);
480 if (!ret)
481 return 0;
482
483 pm_runtime_disable(dev);
484
485exit_probe_master_put:
486 spi_master_put(master);
487
488 return ret;
489}
490
491static int qcom_qspi_remove(struct platform_device *pdev)
492{
493 struct spi_master *master = platform_get_drvdata(pdev);
494
495 /* Unregister _before_ disabling pm_runtime() so we stop transfers */
496 spi_unregister_master(master);
497
498 pm_runtime_disable(&pdev->dev);
499
500 return 0;
501}
502
503static int __maybe_unused qcom_qspi_runtime_suspend(struct device *dev)
504{
505 struct spi_master *master = dev_get_drvdata(dev);
506 struct qcom_qspi *ctrl = spi_master_get_devdata(master);
507
508 clk_bulk_disable_unprepare(QSPI_NUM_CLKS, ctrl->clks);
509
510 return 0;
511}
512
513static int __maybe_unused qcom_qspi_runtime_resume(struct device *dev)
514{
515 struct spi_master *master = dev_get_drvdata(dev);
516 struct qcom_qspi *ctrl = spi_master_get_devdata(master);
517
518 return clk_bulk_prepare_enable(QSPI_NUM_CLKS, ctrl->clks);
519}
520
521static int __maybe_unused qcom_qspi_suspend(struct device *dev)
522{
523 struct spi_master *master = dev_get_drvdata(dev);
524 int ret;
525
526 ret = spi_master_suspend(master);
527 if (ret)
528 return ret;
529
530 ret = pm_runtime_force_suspend(dev);
531 if (ret)
532 spi_master_resume(master);
533
534 return ret;
535}
536
537static int __maybe_unused qcom_qspi_resume(struct device *dev)
538{
539 struct spi_master *master = dev_get_drvdata(dev);
540 int ret;
541
542 ret = pm_runtime_force_resume(dev);
543 if (ret)
544 return ret;
545
546 ret = spi_master_resume(master);
547 if (ret)
548 pm_runtime_force_suspend(dev);
549
550 return ret;
551}
552
553static const struct dev_pm_ops qcom_qspi_dev_pm_ops = {
554 SET_RUNTIME_PM_OPS(qcom_qspi_runtime_suspend,
555 qcom_qspi_runtime_resume, NULL)
556 SET_SYSTEM_SLEEP_PM_OPS(qcom_qspi_suspend, qcom_qspi_resume)
557};
558
559static const struct of_device_id qcom_qspi_dt_match[] = {
560 { .compatible = "qcom,qspi-v1", },
561 { }
562};
563MODULE_DEVICE_TABLE(of, qcom_qspi_dt_match);
564
565static struct platform_driver qcom_qspi_driver = {
566 .driver = {
567 .name = "qcom_qspi",
568 .pm = &qcom_qspi_dev_pm_ops,
569 .of_match_table = qcom_qspi_dt_match,
570 },
571 .probe = qcom_qspi_probe,
572 .remove = qcom_qspi_remove,
573};
574module_platform_driver(qcom_qspi_driver);
575
576MODULE_DESCRIPTION("SPI driver for QSPI cores");
577MODULE_LICENSE("GPL v2");