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1/*
2 * Memory-mapped interface driver for DW SPI Core
3 *
4 * Copyright (c) 2010, Octasic semiconductor.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 */
10
11#include <linux/clk.h>
12#include <linux/err.h>
13#include <linux/interrupt.h>
14#include <linux/platform_device.h>
15#include <linux/slab.h>
16#include <linux/spi/spi.h>
17#include <linux/scatterlist.h>
18
19#include "spi-dw.h"
20
21#define DRIVER_NAME "dw_spi_mmio"
22
23struct dw_spi_mmio {
24 struct dw_spi dws;
25 struct clk *clk;
26};
27
28static int __devinit dw_spi_mmio_probe(struct platform_device *pdev)
29{
30 struct dw_spi_mmio *dwsmmio;
31 struct dw_spi *dws;
32 struct resource *mem, *ioarea;
33 int ret;
34
35 dwsmmio = kzalloc(sizeof(struct dw_spi_mmio), GFP_KERNEL);
36 if (!dwsmmio) {
37 ret = -ENOMEM;
38 goto err_end;
39 }
40
41 dws = &dwsmmio->dws;
42
43 /* Get basic io resource and map it */
44 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
45 if (!mem) {
46 dev_err(&pdev->dev, "no mem resource?\n");
47 ret = -EINVAL;
48 goto err_kfree;
49 }
50
51 ioarea = request_mem_region(mem->start, resource_size(mem),
52 pdev->name);
53 if (!ioarea) {
54 dev_err(&pdev->dev, "SPI region already claimed\n");
55 ret = -EBUSY;
56 goto err_kfree;
57 }
58
59 dws->regs = ioremap_nocache(mem->start, resource_size(mem));
60 if (!dws->regs) {
61 dev_err(&pdev->dev, "SPI region already mapped\n");
62 ret = -ENOMEM;
63 goto err_release_reg;
64 }
65
66 dws->irq = platform_get_irq(pdev, 0);
67 if (dws->irq < 0) {
68 dev_err(&pdev->dev, "no irq resource?\n");
69 ret = dws->irq; /* -ENXIO */
70 goto err_unmap;
71 }
72
73 dwsmmio->clk = clk_get(&pdev->dev, NULL);
74 if (IS_ERR(dwsmmio->clk)) {
75 ret = PTR_ERR(dwsmmio->clk);
76 goto err_irq;
77 }
78 clk_enable(dwsmmio->clk);
79
80 dws->parent_dev = &pdev->dev;
81 dws->bus_num = 0;
82 dws->num_cs = 4;
83 dws->max_freq = clk_get_rate(dwsmmio->clk);
84
85 ret = dw_spi_add_host(dws);
86 if (ret)
87 goto err_clk;
88
89 platform_set_drvdata(pdev, dwsmmio);
90 return 0;
91
92err_clk:
93 clk_disable(dwsmmio->clk);
94 clk_put(dwsmmio->clk);
95 dwsmmio->clk = NULL;
96err_irq:
97 free_irq(dws->irq, dws);
98err_unmap:
99 iounmap(dws->regs);
100err_release_reg:
101 release_mem_region(mem->start, resource_size(mem));
102err_kfree:
103 kfree(dwsmmio);
104err_end:
105 return ret;
106}
107
108static int __devexit dw_spi_mmio_remove(struct platform_device *pdev)
109{
110 struct dw_spi_mmio *dwsmmio = platform_get_drvdata(pdev);
111 struct resource *mem;
112
113 platform_set_drvdata(pdev, NULL);
114
115 clk_disable(dwsmmio->clk);
116 clk_put(dwsmmio->clk);
117 dwsmmio->clk = NULL;
118
119 free_irq(dwsmmio->dws.irq, &dwsmmio->dws);
120 dw_spi_remove_host(&dwsmmio->dws);
121 iounmap(dwsmmio->dws.regs);
122 kfree(dwsmmio);
123
124 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
125 release_mem_region(mem->start, resource_size(mem));
126 return 0;
127}
128
129static struct platform_driver dw_spi_mmio_driver = {
130 .remove = __devexit_p(dw_spi_mmio_remove),
131 .driver = {
132 .name = DRIVER_NAME,
133 .owner = THIS_MODULE,
134 },
135};
136
137static int __init dw_spi_mmio_init(void)
138{
139 return platform_driver_probe(&dw_spi_mmio_driver, dw_spi_mmio_probe);
140}
141module_init(dw_spi_mmio_init);
142
143static void __exit dw_spi_mmio_exit(void)
144{
145 platform_driver_unregister(&dw_spi_mmio_driver);
146}
147module_exit(dw_spi_mmio_exit);
148
149MODULE_AUTHOR("Jean-Hugues Deschenes <jean-hugues.deschenes@octasic.com>");
150MODULE_DESCRIPTION("Memory-mapped I/O interface driver for DW SPI Core");
151MODULE_LICENSE("GPL v2");
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Memory-mapped interface driver for DW SPI Core
4 *
5 * Copyright (c) 2010, Octasic semiconductor.
6 */
7
8#include <linux/clk.h>
9#include <linux/err.h>
10#include <linux/interrupt.h>
11#include <linux/platform_device.h>
12#include <linux/slab.h>
13#include <linux/spi/spi.h>
14#include <linux/scatterlist.h>
15#include <linux/mfd/syscon.h>
16#include <linux/module.h>
17#include <linux/of.h>
18#include <linux/of_platform.h>
19#include <linux/acpi.h>
20#include <linux/property.h>
21#include <linux/regmap.h>
22
23#include "spi-dw.h"
24
25#define DRIVER_NAME "dw_spi_mmio"
26
27struct dw_spi_mmio {
28 struct dw_spi dws;
29 struct clk *clk;
30 struct clk *pclk;
31 void *priv;
32};
33
34#define MSCC_CPU_SYSTEM_CTRL_GENERAL_CTRL 0x24
35#define OCELOT_IF_SI_OWNER_OFFSET 4
36#define JAGUAR2_IF_SI_OWNER_OFFSET 6
37#define MSCC_IF_SI_OWNER_MASK GENMASK(1, 0)
38#define MSCC_IF_SI_OWNER_SISL 0
39#define MSCC_IF_SI_OWNER_SIBM 1
40#define MSCC_IF_SI_OWNER_SIMC 2
41
42#define MSCC_SPI_MST_SW_MODE 0x14
43#define MSCC_SPI_MST_SW_MODE_SW_PIN_CTRL_MODE BIT(13)
44#define MSCC_SPI_MST_SW_MODE_SW_SPI_CS(x) (x << 5)
45
46struct dw_spi_mscc {
47 struct regmap *syscon;
48 void __iomem *spi_mst;
49};
50
51/*
52 * The Designware SPI controller (referred to as master in the documentation)
53 * automatically deasserts chip select when the tx fifo is empty. The chip
54 * selects then needs to be either driven as GPIOs or, for the first 4 using the
55 * the SPI boot controller registers. the final chip select is an OR gate
56 * between the Designware SPI controller and the SPI boot controller.
57 */
58static void dw_spi_mscc_set_cs(struct spi_device *spi, bool enable)
59{
60 struct dw_spi *dws = spi_master_get_devdata(spi->master);
61 struct dw_spi_mmio *dwsmmio = container_of(dws, struct dw_spi_mmio, dws);
62 struct dw_spi_mscc *dwsmscc = dwsmmio->priv;
63 u32 cs = spi->chip_select;
64
65 if (cs < 4) {
66 u32 sw_mode = MSCC_SPI_MST_SW_MODE_SW_PIN_CTRL_MODE;
67
68 if (!enable)
69 sw_mode |= MSCC_SPI_MST_SW_MODE_SW_SPI_CS(BIT(cs));
70
71 writel(sw_mode, dwsmscc->spi_mst + MSCC_SPI_MST_SW_MODE);
72 }
73
74 dw_spi_set_cs(spi, enable);
75}
76
77static int dw_spi_mscc_init(struct platform_device *pdev,
78 struct dw_spi_mmio *dwsmmio,
79 const char *cpu_syscon, u32 if_si_owner_offset)
80{
81 struct dw_spi_mscc *dwsmscc;
82
83 dwsmscc = devm_kzalloc(&pdev->dev, sizeof(*dwsmscc), GFP_KERNEL);
84 if (!dwsmscc)
85 return -ENOMEM;
86
87 dwsmscc->spi_mst = devm_platform_ioremap_resource(pdev, 1);
88 if (IS_ERR(dwsmscc->spi_mst)) {
89 dev_err(&pdev->dev, "SPI_MST region map failed\n");
90 return PTR_ERR(dwsmscc->spi_mst);
91 }
92
93 dwsmscc->syscon = syscon_regmap_lookup_by_compatible(cpu_syscon);
94 if (IS_ERR(dwsmscc->syscon))
95 return PTR_ERR(dwsmscc->syscon);
96
97 /* Deassert all CS */
98 writel(0, dwsmscc->spi_mst + MSCC_SPI_MST_SW_MODE);
99
100 /* Select the owner of the SI interface */
101 regmap_update_bits(dwsmscc->syscon, MSCC_CPU_SYSTEM_CTRL_GENERAL_CTRL,
102 MSCC_IF_SI_OWNER_MASK << if_si_owner_offset,
103 MSCC_IF_SI_OWNER_SIMC << if_si_owner_offset);
104
105 dwsmmio->dws.set_cs = dw_spi_mscc_set_cs;
106 dwsmmio->priv = dwsmscc;
107
108 return 0;
109}
110
111static int dw_spi_mscc_ocelot_init(struct platform_device *pdev,
112 struct dw_spi_mmio *dwsmmio)
113{
114 return dw_spi_mscc_init(pdev, dwsmmio, "mscc,ocelot-cpu-syscon",
115 OCELOT_IF_SI_OWNER_OFFSET);
116}
117
118static int dw_spi_mscc_jaguar2_init(struct platform_device *pdev,
119 struct dw_spi_mmio *dwsmmio)
120{
121 return dw_spi_mscc_init(pdev, dwsmmio, "mscc,jaguar2-cpu-syscon",
122 JAGUAR2_IF_SI_OWNER_OFFSET);
123}
124
125static int dw_spi_alpine_init(struct platform_device *pdev,
126 struct dw_spi_mmio *dwsmmio)
127{
128 dwsmmio->dws.cs_override = 1;
129
130 return 0;
131}
132
133static int dw_spi_mmio_probe(struct platform_device *pdev)
134{
135 int (*init_func)(struct platform_device *pdev,
136 struct dw_spi_mmio *dwsmmio);
137 struct dw_spi_mmio *dwsmmio;
138 struct dw_spi *dws;
139 int ret;
140 int num_cs;
141
142 dwsmmio = devm_kzalloc(&pdev->dev, sizeof(struct dw_spi_mmio),
143 GFP_KERNEL);
144 if (!dwsmmio)
145 return -ENOMEM;
146
147 dws = &dwsmmio->dws;
148
149 /* Get basic io resource and map it */
150 dws->regs = devm_platform_ioremap_resource(pdev, 0);
151 if (IS_ERR(dws->regs)) {
152 dev_err(&pdev->dev, "SPI region map failed\n");
153 return PTR_ERR(dws->regs);
154 }
155
156 dws->irq = platform_get_irq(pdev, 0);
157 if (dws->irq < 0)
158 return dws->irq; /* -ENXIO */
159
160 dwsmmio->clk = devm_clk_get(&pdev->dev, NULL);
161 if (IS_ERR(dwsmmio->clk))
162 return PTR_ERR(dwsmmio->clk);
163 ret = clk_prepare_enable(dwsmmio->clk);
164 if (ret)
165 return ret;
166
167 /* Optional clock needed to access the registers */
168 dwsmmio->pclk = devm_clk_get_optional(&pdev->dev, "pclk");
169 if (IS_ERR(dwsmmio->pclk)) {
170 ret = PTR_ERR(dwsmmio->pclk);
171 goto out_clk;
172 }
173 ret = clk_prepare_enable(dwsmmio->pclk);
174 if (ret)
175 goto out_clk;
176
177 dws->bus_num = pdev->id;
178
179 dws->max_freq = clk_get_rate(dwsmmio->clk);
180
181 device_property_read_u32(&pdev->dev, "reg-io-width", &dws->reg_io_width);
182
183 num_cs = 4;
184
185 device_property_read_u32(&pdev->dev, "num-cs", &num_cs);
186
187 dws->num_cs = num_cs;
188
189 init_func = device_get_match_data(&pdev->dev);
190 if (init_func) {
191 ret = init_func(pdev, dwsmmio);
192 if (ret)
193 goto out;
194 }
195
196 ret = dw_spi_add_host(&pdev->dev, dws);
197 if (ret)
198 goto out;
199
200 platform_set_drvdata(pdev, dwsmmio);
201 return 0;
202
203out:
204 clk_disable_unprepare(dwsmmio->pclk);
205out_clk:
206 clk_disable_unprepare(dwsmmio->clk);
207 return ret;
208}
209
210static int dw_spi_mmio_remove(struct platform_device *pdev)
211{
212 struct dw_spi_mmio *dwsmmio = platform_get_drvdata(pdev);
213
214 dw_spi_remove_host(&dwsmmio->dws);
215 clk_disable_unprepare(dwsmmio->pclk);
216 clk_disable_unprepare(dwsmmio->clk);
217
218 return 0;
219}
220
221static const struct of_device_id dw_spi_mmio_of_match[] = {
222 { .compatible = "snps,dw-apb-ssi", },
223 { .compatible = "mscc,ocelot-spi", .data = dw_spi_mscc_ocelot_init},
224 { .compatible = "mscc,jaguar2-spi", .data = dw_spi_mscc_jaguar2_init},
225 { .compatible = "amazon,alpine-dw-apb-ssi", .data = dw_spi_alpine_init},
226 { /* end of table */}
227};
228MODULE_DEVICE_TABLE(of, dw_spi_mmio_of_match);
229
230static const struct acpi_device_id dw_spi_mmio_acpi_match[] = {
231 {"HISI0173", 0},
232 {},
233};
234MODULE_DEVICE_TABLE(acpi, dw_spi_mmio_acpi_match);
235
236static struct platform_driver dw_spi_mmio_driver = {
237 .probe = dw_spi_mmio_probe,
238 .remove = dw_spi_mmio_remove,
239 .driver = {
240 .name = DRIVER_NAME,
241 .of_match_table = dw_spi_mmio_of_match,
242 .acpi_match_table = ACPI_PTR(dw_spi_mmio_acpi_match),
243 },
244};
245module_platform_driver(dw_spi_mmio_driver);
246
247MODULE_AUTHOR("Jean-Hugues Deschenes <jean-hugues.deschenes@octasic.com>");
248MODULE_DESCRIPTION("Memory-mapped I/O interface driver for DW SPI Core");
249MODULE_LICENSE("GPL v2");